WO2000057470A1 - Procede pour disposer un circuit lsi - Google Patents
Procede pour disposer un circuit lsi Download PDFInfo
- Publication number
- WO2000057470A1 WO2000057470A1 PCT/JP2000/001794 JP0001794W WO0057470A1 WO 2000057470 A1 WO2000057470 A1 WO 2000057470A1 JP 0001794 W JP0001794 W JP 0001794W WO 0057470 A1 WO0057470 A1 WO 0057470A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- power supply
- cell
- lsi
- logic gate
- capacitance
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000013461 design Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 abstract description 3
- 230000001629 suppression Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 208000032365 Electromagnetic interference Diseases 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 229910001374 Invar Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Definitions
- the present invention relates to a power supply stabilization method in LSI design using automatic placement and routing of standard cells.
- the power supply noise of the LSI tends to increase as the consumption current of the LSI increases.
- the demand for power saving in the field has led to the progress of lowering the voltage of the LSI, and accordingly, the operation margin for power supply noise of the LSI internal circuit has also been deteriorating.
- Such an increase in the power supply noise of the LSI causes the internal circuit of the LSI to suffer from (1) degradation in operating speed, (2) malfunction of the circuit, and (3) system noise due to EMI (Electro Magnetic Inter-ference) noise. There is a concern that adverse effects such as malfunctions may occur.
- EMI Electro Magnetic Inter-ference
- Japanese Patent Application Laid-Open No. 5-21711 discloses a method of stabilizing the power supply by arranging a power supply capacitance in a portion where no LSI functional circuit is present.
- Japanese Patent Application Laid-Open No. 5-2831615 discloses a method for effectively adding a power supply capacitance by using a capacitance between power supply aluminum wirings of LSI.
- FIG. 9 shows a circuit diagram of a general CM-S integrated circuit.
- 9 3 PMOS (P-channel MOS) transistor switch
- 92 is an NMOS (N-channel MOS) transistor switch
- 93 is a ground electrode
- 94 is a power supply capacity.
- 95 indicates the load capacitance
- 96 indicates the power supply ( ⁇ 3) pad
- 97 indicates the power supply (V ss) pad
- 98 indicates the charging current
- 99 indicates the parasitic inductance.
- Power supply capacitance 94 has stored charge energy.
- the current (Ic) can be supplied from the power supply capacity 94 in addition to the current supply (Ivdd) from the power supply pad 96.
- Power supply (Vdd) The amount of change in current supply from the pad 96 can be suppressed.
- the inductance component (L) of aluminum wiring inside LSI tends to increase.
- a parasitic inductor 99 occurs, which causes power supply noise. That is, the power supply noise (AV) can be expressed by the following equation.
- di / dt indicates a current change amount. From (Equation 1), to reduce the power supply noise ( ⁇ ), the current change (di / d It can be seen that it is effective to reduce t) or reduce the parasitic inductor component L. In other words, since the parasitic inductor component L increases in proportion to the length of the aluminum wiring, it is effective to shorten the power supply line where current changes occur.
- An object of the present invention is to provide a method for arranging an LSI which has a sufficient power supply noise suppressing effect and can realize a sufficient power supply stabilization in a standard cell type LSI design to solve the above problems. I do.
- an LSI placement method provides a power supply capacity cell as one of the standard cells in an LSI design by automatic placement and routing of a standard cell.
- the capacitance value is determined according to the drive load capacitance value of the logic gate cell where the power supply capacitance cell is to be disposed, and the power supply capacitance cell is disposed near the logic gate cell.
- the capacitance value of the power supply capacitance cell is set to approximately twice the drive load capacitance value of the logic gate cell. If it is set to about twice the total load capacity of the logic gate standard cell, the power supply noise will be reduced to about 1/10 or less of the power supply voltage. Because it can be
- the power supply capacitance cell is arranged near a logic gate cell which simultaneously changes in synchronization with a clock.
- the area and area can be minimized and power supply noise can be suppressed efficiently.
- an LSI placement method comprises, in an LSI design by automatic placement and routing of standard cells, a power supply capacity cell as one of the standard cells, and each of the automatically placed and routed blocks.
- the power supply capacity cell is arranged in the area where the standard cell is not arranged.
- FIG. 1 is a block diagram of LSI.
- FIG. 2 is an automatic layout and wiring diagram of blocks.
- FIG. 3 is an automatic placement and wiring diagram provided with a power capacity standard cell in the LSI placement method according to the first embodiment of the present invention.
- FIG. 4 is an explanatory diagram of the determination of the optimum power supply capacity in the LSI placement method according to the first embodiment of the present invention.
- FIG. 5 is an exemplary diagram of a configuration of a power supply capacity in a CMOS semiconductor integrated circuit.
- FIG. 6 is an exemplary diagram of a circuit designed for CTS.
- FIG. 7 is an illustration of an example of a conventional block layout by automatic placement and routing using standard cells.
- FIG. 8 is an exemplary diagram of a block layout by automatic placement and routing using standard cells in the LSI placement method according to the second embodiment of the present invention.
- FIG. 9 is a circuit diagram of a conventional CMOS integrated circuit.
- FIG. 1 is a general LSI block diagram
- FIG. 2 is an automatic arrangement and wiring diagram in block A
- FIG. 3 is an automatic arrangement and wiring having a power supply standard cell in the LSI arrangement method according to the first embodiment of the present invention.
- FIG. 1 indicates LSI, and 11 to 13 indicate circuit blocks when block layout is performed using standard cells.
- each block is synthesized by standard cells, and each block is laid out in a rectangular shape.
- the present invention is characterized in that a standard cell 22 composed of only a power supply capacity is prepared in advance as a standard cell.
- the power supply capacity standard cell 22 is arranged near the logic gate standard cell 21 as shown in FIG. 3 according to the load capacity of each logic gate standard cell 21.
- “near” means adjacent to each logic gate standard cell 21 for driving a load, and means that they are arranged on the same power supply line. Therefore, if it is located on another power supply line, it is not understood that it is located “nearby” even if it is located at a position close to the distance.
- the power supply capacity standard cell 22 near the logic gate standard cell 21
- the charging current to the load capacity generated when each logic gate standard cell is switched can be reduced by the power supply capacity near the logic gate standard cell 21. Since most of the power is supplied from the capacitance, it is expressed by (Equation 1) due to the power inductor component L. The generated power noise becomes smaller.
- the power supply noise ( ⁇ ) is set to be about twice the total load capacitance of the logic gate standard cell 21, ⁇ can be suppressed to about 1/10 or less of the power supply voltage (Vdd). It is known. (RLarsson, "di / dt Noise m CMOS Integrated Circuits., Analog Integrated Circuits and Processing, An International Journal Vol.14, pp.113-129, 1997.)
- the fact that the noise is equal to or lower than 1 Z10 of the power supply voltage corresponds to a voltage value of about 1 Z2 of the CMOS threshold voltage from another viewpoint. Therefore, keeping power supply noise to a threshold voltage of 1 Z2 is a particularly important factor in guaranteeing the reliability of LSI operation.
- the drive load capacitance (C1 + C2) of each logic gate is estimated, and the drive A power supply capacity standard cell 21 having a power supply capacity C d that is about twice or more the load capacity is arranged near each logic gate. That is, the power supply capacity standard cell 21 is arranged so as to satisfy Cd> 2 (C1 + C2). With this arrangement, it is possible to guarantee that the power supply noise ( ⁇ ) of each logic gate circuit is kept at 1/10 or less of the power supply voltage, so that the maximum value of the power supply noise in the entire LSI is guaranteed. Becomes possible.
- the configuration of FIG. 5 is the most suitable as the configuration of the power supply capacity in the CMOS integrated circuit. That is, in the p-sub wafer, n-wel1 is fixed to Vss, and the polysilicon gate electrode is fixed to Vdd. Since the gate electrode potential is forward-biased with respect to n-we11, no depletion layer capacitance is generated.Thus, a power supply capacitor with a large capacitance value despite its small area must be realized. Can be.
- power supply standard cells 22 are placed for all logic gates. Doing so creates a large area loss. In addition, power supply noise is greatest when multiple logic gates switch simultaneously. In general, in LSIs that operate in a completely clock-synchronous type, many logic gates switch at the rising edge of the clock. This is because DFF (D Flip-Flop) is designed to operate at the rising edge of the clock. Also, with the recent increase in the speed of LSIs, reduction of clock skew is desired.
- DFF D Flip-Flop
- CTS Lock Tree Synthesis
- This method is one of the methods that can adjust the timing so that the phases of all DFF operations become equal.
- the timing adjustment can be performed by an overnight delay in consideration of a wiring delay.
- Fig. 6 shows a typical example of LSI design using CTS.
- reference numeral 23 denotes a DFF standard cell
- reference numeral 24 denotes an Invar overnight standard cell. It is possible to adjust the clock phase of all DFFs to be equal by changing the size of the inverter and the like according to the load capacity, or by adjusting the number of delay stages of the inverter.
- the method of arranging the power supply standard cell 22 using the above-mentioned CTS only in the synchronous logic gates (DFF gate, inverter gate for CTS, etc.) is effective in reducing the area of the entire LSI and suppressing noise. This is the most effective method when considering the balance of
- a new power supply capacity cell is prepared, and a power supply capacity having an optimum size according to the load capacity of the logic gate cell is provided. Placing the cell near the logic gate cell increases the power supply noise due to the parasitic inductor. The power supply noise component can be reduced. Also, by adopting the above method only for the logic gate of the clock synchronous system, it is possible to minimize the area loss and efficiently suppress the power supply noise.
- Fig. 7 shows blocks automatically placed and routed using conventional standard cells.
- the block width of the standard cells of each power supply line that constitutes a block differs for each block.
- a power supply capacity cell can be added without increasing the area of the entire block. This involves preparing a standard cell called power supply standard cell 22 and calculating the number of power supply standard cells 22 that can be placed based on the width of the power supply dead space and the width of power supply standard cell 22. It can be easily realized by arranging as much as possible.
- a new power supply capacity standard cell 22 is prepared, and each of the existing power supply capacity standard cells 22 By placing the power supply standard cells 22 in the dead space 7 1 of the circuit block as much as possible, the power supply impedance can be reduced without increasing the area of the entire block, and the power supply noise is effectively reduced. It becomes possible.
- the quality of the semiconductor integrated circuit is improved by applying the semiconductor integrated circuit to various systems and devices. It is possible to provide systems and devices with high performance.
- a power supply capacity cell having an optimum size corresponding to the load capacity of the logic gate cell is located near the logic gate cell.
- the L component of the power supply wiring can be reduced as compared with the conventional LSI arrangement method, and power supply noise can be effectively suppressed.
- the LSI placement method according to the present invention by adopting the above method only for the gate gate of the clock synchronous system, the area loss can be minimized, and the power supply noise can be efficiently reduced. It becomes possible to suppress.
- the power supply impedance is reduced without increasing the area of the entire block by arranging the power supply capacity cells in the dead space of each of the conventional circuit blocks. Can be reduced.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00911324A EP1083598A4 (en) | 1999-03-24 | 2000-03-23 | METHOD FOR ARRANGING A LSI CIRCUIT |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11/79927 | 1999-03-24 | ||
JP07992799A JP3450739B2 (ja) | 1999-03-24 | 1999-03-24 | Lsi配置方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000057470A1 true WO2000057470A1 (fr) | 2000-09-28 |
Family
ID=13703955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/001794 WO2000057470A1 (fr) | 1999-03-24 | 2000-03-23 | Procede pour disposer un circuit lsi |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1083598A4 (ja) |
JP (1) | JP3450739B2 (ja) |
KR (1) | KR100389235B1 (ja) |
CN (1) | CN1149657C (ja) |
WO (1) | WO2000057470A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6732335B2 (en) | 2002-04-23 | 2004-05-04 | Oki Electric Industry Co., Ltd. | Semiconductor IC with an inside capacitor for a power supply circuit and a method of automatically designing the same |
JP2004055954A (ja) * | 2002-07-23 | 2004-02-19 | Nec Micro Systems Ltd | 半導体集積回路およびそのレイアウト方法 |
CN1294642C (zh) * | 2002-08-21 | 2007-01-10 | 矽统科技股份有限公司 | 电源杂讯的分析方法及降低方法 |
JP4204444B2 (ja) | 2003-11-04 | 2009-01-07 | パナソニック株式会社 | 半導体集積回路の設計方法 |
JP4205662B2 (ja) | 2004-12-28 | 2009-01-07 | パナソニック株式会社 | 半導体集積回路の設計方法 |
JP5092263B2 (ja) * | 2006-03-31 | 2012-12-05 | 富士通セミコンダクター株式会社 | デカップリングコンデンサ及び半導体集積回路装置 |
JP4967534B2 (ja) * | 2006-08-28 | 2012-07-04 | 富士通セミコンダクター株式会社 | 半導体装置のレイアウト方法およびレイアウトプログラム |
JP5653001B2 (ja) | 2009-03-16 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及び半導体装置の補償容量の配置方法 |
JP5552775B2 (ja) * | 2009-08-28 | 2014-07-16 | ソニー株式会社 | 半導体集積回路 |
JP5640712B2 (ja) * | 2010-12-10 | 2014-12-17 | 日本電気株式会社 | 半導体装置の設計支援装置、キャパシタ配置方法、及びプログラム |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07106521A (ja) * | 1993-10-07 | 1995-04-21 | Nec Corp | セルベース設計半導体集積回路装置 |
JPH10107235A (ja) * | 1996-09-27 | 1998-04-24 | Hitachi Ltd | ゲートアレーlsiの構成方法とこれを用いた回路装置 |
JPH10150148A (ja) * | 1996-09-18 | 1998-06-02 | Denso Corp | 半導体集積回路 |
JPH10326833A (ja) * | 1997-05-23 | 1998-12-08 | Nec Corp | 半導体集積回路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5631492A (en) * | 1994-01-21 | 1997-05-20 | Motorola | Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation |
JPH10284605A (ja) * | 1997-04-08 | 1998-10-23 | Mitsubishi Electric Corp | 半導体集積回路およびセルベース方式によりレイアウト設計された半導体集積回路 |
-
1999
- 1999-03-24 JP JP07992799A patent/JP3450739B2/ja not_active Expired - Fee Related
-
2000
- 2000-03-23 EP EP00911324A patent/EP1083598A4/en not_active Withdrawn
- 2000-03-23 WO PCT/JP2000/001794 patent/WO2000057470A1/ja active Application Filing
- 2000-03-23 KR KR10-2000-7013241A patent/KR100389235B1/ko not_active IP Right Cessation
- 2000-03-23 CN CNB008009791A patent/CN1149657C/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07106521A (ja) * | 1993-10-07 | 1995-04-21 | Nec Corp | セルベース設計半導体集積回路装置 |
JPH10150148A (ja) * | 1996-09-18 | 1998-06-02 | Denso Corp | 半導体集積回路 |
JPH10107235A (ja) * | 1996-09-27 | 1998-04-24 | Hitachi Ltd | ゲートアレーlsiの構成方法とこれを用いた回路装置 |
JPH10326833A (ja) * | 1997-05-23 | 1998-12-08 | Nec Corp | 半導体集積回路 |
Non-Patent Citations (2)
Title |
---|
P. LARSSON: "di/dt Noise in CMOS Intergrated Circuits", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 14, 1997, pages 113 - 129, XP002928831 * |
See also references of EP1083598A4 * |
Also Published As
Publication number | Publication date |
---|---|
JP3450739B2 (ja) | 2003-09-29 |
KR100389235B1 (ko) | 2003-06-27 |
EP1083598A4 (en) | 2005-12-21 |
EP1083598A1 (en) | 2001-03-14 |
CN1149657C (zh) | 2004-05-12 |
CN1310862A (zh) | 2001-08-29 |
KR20010043810A (ko) | 2001-05-25 |
JP2000277618A (ja) | 2000-10-06 |
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