WO2000045431A1 - Method of packaging semiconductor device using anisotropic conductive adhesive - Google Patents

Method of packaging semiconductor device using anisotropic conductive adhesive Download PDF

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Publication number
WO2000045431A1
WO2000045431A1 PCT/JP2000/000420 JP0000420W WO0045431A1 WO 2000045431 A1 WO2000045431 A1 WO 2000045431A1 JP 0000420 W JP0000420 W JP 0000420W WO 0045431 A1 WO0045431 A1 WO 0045431A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
circuit board
anisotropic conductive
adhesive resin
conductive adhesive
Prior art date
Application number
PCT/JP2000/000420
Other languages
English (en)
French (fr)
Inventor
Makoto Watanabe
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Priority to DE60001776T priority Critical patent/DE60001776T2/de
Priority to EP00901937A priority patent/EP1067598B1/en
Priority to BR0004470-9A priority patent/BR0004470A/pt
Priority to US09/646,964 priority patent/US6498051B1/en
Publication of WO2000045431A1 publication Critical patent/WO2000045431A1/ja

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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    • H01L2924/01061—Promethium [Pm]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder

Definitions

  • the present invention relates to a semiconductor device mounting method for connecting and fixing a semiconductor device on a circuit board using an anisotropic conductive adhesive.
  • 11 to 14 are cross-sectional views showing each step of a conventional method for mounting a semiconductor device.
  • a wiring pattern 15 provided on a circuit board 17 is connected to a protruding electrode 14 formed on a semiconductor device 16.
  • the conductive particles 12 having conductivity contained in the anisotropic conductive adhesive 13 are sandwiched between the wiring pattern 15 and the protruding electrodes 14, and the conductive particles 12 are used to form the conductive particles 12.
  • the anisotropic conductive adhesive 13 is made by mixing conductive particles 12 into a thermosetting adhesive resin 11 made of an epoxy-based adhesive to provide conductivity, and a film is formed on a base film. Formed on top and protected with a cover film.
  • the conductive particles 12 are metal particles made of silver or solder having a diameter of 5 to 10 ⁇ m, or resin particles made of plastic and the surface of which is coated with gold (Au).
  • the circuit board 17 has a wiring pattern 15 formed on a board made of glass epoxy resin, ceramic or glass.
  • the wiring pattern 15 is made of copper or gold, or an ITO (oxide of indium and tin) film used in a liquid crystal panel or the like.
  • the process of mounting the semiconductor device is as follows. First, as shown in FIG. 11, an anisotropic conductive adhesive 13 is transferred to a portion of the circuit board 17 where the semiconductor device 16 is connected.
  • the wiring pattern 15 of the circuit board 17 and the protruding electrode 14 formed on the semiconductor device 16 are aligned, and the semiconductor device 16 is opposed to the circuit board. Mounted on 17
  • the semiconductor device 16 is thermocompression-bonded to the circuit board 17 by applying heat while applying a pressure P using a heating and pressing jig 18 having a built-in heater.
  • the adhesive resin 11 of the isotropic conductive adhesive 13 is cured.
  • the adhesive resin 11 is cured, as shown in FIG. 14, the semiconductor device 16 is adhered and fixed on the circuit board 17, and the conductive particles 12 of the anisotropic conductive adhesive 13 are used. The continuity between the protruding electrode 14 of the semiconductor device 16 and the wiring pattern 15 is maintained.
  • thermocompression bonding is performed from the beginning at the temperature required to cure the adhesive resin 11 using a heating and pressing jig 18, but a thermosetting adhesive resin such as an epoxy-based adhesive is used.
  • a thermosetting adhesive resin such as an epoxy-based adhesive is used.
  • FIG. 15 shows a state when the semiconductor device 16 is mounted on the circuit board 17, that is, a state before heating and pressing by the heating and pressing jig 18 shown in FIG.
  • the semiconductor device 16 and a part of the circuit board 17 are enlarged to show the state of the conductive particles 12 existing between the electrode 14 and the wiring pattern 15.
  • the adhesive resin 11 remains on the transferred film because it is before the heating and pressing.
  • the semiconductor device 16 is heated and heated to a temperature at which the adhesive resin 11 undergoes a curing reaction by a heating and pressing jig 18 in order to cure the adhesive resin 11.
  • pressure P is applied, the adhesive resin 1 1 rapidly cures and is crushed. It flows and protrudes from the semiconductor device 16. Since the distance between the protruding electrode 14 and the wiring pattern 15 is the smallest, the adhesive resin 11 near the protruding electrode 14 is strongly pushed out by the protruding electrode 14 and flows the most.
  • the conductive particles 12 are also pushed out of the protruding electrodes 14 together with the flow of the adhesive resin 11, so that when the adhesive resin 11 is cured and thermocompression bonding is completed, the conductive particles 1 2 Are more present in portions protruding outside the lower surface of the protruding electrode 14. Therefore, the number of conductive particles remaining between the protruding electrode 14 and the wiring pattern 15 becomes small.
  • the temporary softening phenomenon before the adhesive resin 11 of the anisotropic conductive adhesive 13 is hardened by the heating at the time of thermocompression bonding, and the pressing force applied to the semiconductor device.
  • the conductive particles 12 are extruded, and the number of conductive particles 12 remaining between the protruding electrode 14 and the wiring pattern 15 is reduced, so that the connection resistance between the protruding electrode 14 and the wiring pattern 15 is high. There was a problem that would be.
  • connection resistance low, it is necessary to leave as many conductive particles 12 between the protruding electrodes 14 and the wiring pattern 15 as possible. It is necessary to increase the area of the connecting portion between the two so as to be captured.
  • the conventional mounting method described above has a high connection resistance value and tends to cause unstable connection, and is not suitable for high-density mounting.
  • the present invention has been made in order to solve such a problem in a method of mounting a semiconductor device using an anisotropic conductive adhesive, and a method of capturing a semiconductor device between a projecting electrode of a semiconductor device and a wiring pattern of a circuit board.
  • the aim is to reduce the number of conductive particles used to achieve stable connection with low connection resistance even if the area of the connection is small, and to make it suitable for high-density mounting. Target.
  • a method of mounting a semiconductor device using an anisotropic conductive adhesive according to the present invention includes the following steps (1) to (4) in order to achieve the above object.
  • the step of temporarily compressing the semiconductor device to the circuit board allows electrical conduction between the protruding electrode of the semiconductor device and the wiring pattern of the circuit board.
  • step (4) can be performed by thermocompression bonding using a heating and pressing jig set at a temperature at which the adhesive resin cures.
  • the step (4) may be performed by placing the circuit board on which the semiconductor device has been temporarily press-fitted in a furnace set at a temperature at which the adhesive resin cures, or by using a hot plate set at a similar temperature. It can also be done on top.
  • the conductive particles may be brought into contact with the bump electrode and the wiring pattern.
  • the temporary compression bonding is performed at a temperature at which the adhesive resin of the anisotropic conductive adhesive has a low fluidity. Conductive particles are sandwiched between the protruding electrode and the wiring pattern with the adhesive resin's low viscosity And many remain between the protruding electrode and the wiring pattern. After that, the adhesive resin is fully cured, so that the connection resistance is low and stable connection is possible with many conductive particles remaining at the connection part. Furthermore, since a large number of conductive particles can be left at the connection portion, the area of the connection portion can be reduced, and connection at a finer connection pitch than before can be achieved.
  • FIG. 1 is an enlarged schematic cross-sectional view showing a part of an anisotropic conductive adhesive used in a method for mounting a semiconductor device according to the present invention.
  • FIG. 2 to FIG. 5 are schematic cross-sectional views sequentially showing each step for describing one embodiment of a semiconductor device mounting method according to the present invention.
  • FIG. 6 and FIG. 7 are schematic cross-sectional views showing, on an enlarged scale, main parts of the steps shown in FIG. 3 and FIG. 4, respectively.
  • FIG. 8 is a diagram showing the number of conductive particles sandwiched between a protruding electrode of a semiconductor device mounted by the method of mounting a semiconductor device according to the present invention and a wiring pattern of a circuit board in comparison with a conventional example. .
  • FIG. 9 is a schematic cross-sectional view showing an example of another step in place of the step shown in FIG. 4 in the method of mounting a semiconductor device according to the present invention.
  • FIG. 10 is a schematic cross-sectional view showing an example of still another step in place of the step shown in FIG. 4 in the semiconductor device mounting method according to the present invention.
  • FIG. 11 to FIG. 14 are schematic cross-sectional views showing, in order, respective steps for describing a conventional method of mounting a semiconductor device.
  • FIG. 15 and FIG. 16 are schematic cross-sectional views showing an enlarged main part of each step shown in FIG. 12 and FIG. 13, respectively.
  • FIG. 1 is an enlarged schematic cross-sectional view showing a part of an anisotropic conductive adhesive used in a method for mounting a semiconductor device according to the present invention.
  • the anisotropic conductive adhesive Prior to use, the anisotropic conductive adhesive is formed in a film shape on a base film, and the opposite surface is protected by a cover film, but these are not shown.
  • This anisotropic conductive adhesive 13 is made of an adhesive resin 11 having a thickness of about 15 ⁇ m to about 100 ⁇ m, and a conductive particle 1 having a diameter of about 3 ⁇ m to about several tens / zm. It has a structure in which a large number of 2 are mixed to provide conductivity in the thickness direction.
  • the thickness of the adhesive resin 11 is about 15 ⁇ to about 100 jum, but the specific thickness is the protrusion formed on the semiconductor device 16 to be mounted as shown in FIG.
  • the height is determined according to the height of the electrode 14 (height from the board) and the height of the wiring pattern 15 provided on the circuit board 17 (height from the board). For example, if the height of the protruding electrode is 20 ⁇ m and the height of the wiring pattern is 18 ⁇ m, the adhesive resin 11 is thicker than the total height (thickness) of both.
  • the thickness should be set to 38 ⁇ m or more, which is the sum of the two.
  • the adhesive resin is formed in a film shape by a printing method, a transfer method, or the like, but is actually formed to be about 10 ⁇ m thick in consideration of the accuracy of the formation. Therefore, the adhesive resin 11 in the above case is formed to have a thickness of about 50 / m by increasing 38 ⁇ m by about 10 ⁇ m.
  • an insulating thermosetting resin such as an epoxy resin or a phenol resin, for example, an epoxy thermosetting resin is used.
  • the conductive particles 12 mixed into the adhesive resin 11 have a diameter of about 3 to several tens / im and have metal particles made of silver, solder, or the like, or gold (P) on the surface of plastic resin particles. A u) Particles subjected to plating.
  • the size of the conductive particles 1 and 2 depends on the gap between the wiring patterns 15 to be connected. (Interval). For example, if the gap is 10 ⁇ m, the diameter of the conductive particles 12 is set to be smaller than 10 m so that no short circuit occurs between the patterns.
  • the conductive particles 12 are added in an amount of 4 wt% (weight / o) to the adhesive resin 11 and kneaded to form an anisotropic conductive adhesive 13.
  • a wiring pattern 15 is formed on a board made of glass epoxy resin, ceramic, or glass.
  • the wiring pattern 15 is made of copper or gold, or an ITO (oxide of indium and tin) film used in a liquid crystal panel or the like.
  • the wiring pattern 15 provided on the circuit board 17 and the protruding electrodes 14 formed on the semiconductor device 16 are connected as in the related art.
  • the conductive particles 12 having conductivity are sandwiched between the wiring pattern 15 and the protruding electrodes 14 so that the conductive particles 12 allow conduction between them.
  • the protruding electrode 14 is formed by a plating method, a vacuum deposition method, or the like using a material such as solder, gold, or copper.
  • anisotropic conductive adhesive 13 is placed by transfer or the like on a portion of circuit board 17 where a wiring pattern for mounting semiconductor device 16 is formed.
  • the anisotropic conductive adhesive 13 is arranged in the same magnitude and force as the semiconductor device 16 to be mounted or in a range of about 2 mm larger (wider) over the entire circumference than the outer shape.
  • a force is applied in advance to an area where the anisotropic conductive adhesive 13 is to be transferred, and the force is applied. This is performed by disposing the anisotropic conductive adhesive 13 in the transfer area.
  • the anisotropic conductive adhesive 13 disposed is thermocompression-bonded to the circuit board 1. Transfer onto 7 The pressure at this time should be such that the anisotropic conductive adhesive 13 can be attached to the circuit board 17. After that, the base film is peeled off.
  • the wiring pattern 15 formed on the circuit board 17 and the projecting electrodes 14 formed on the semiconductor device 16 are aligned, and the semiconductor device 16 is assembled.
  • the semiconductor device 16 is pressurized at a predetermined pressure P i from the back side where the protruding electrodes 14 are not formed by a heating and pressing jig 18 with a built-in heater.
  • Adhesive resin (1) The semiconductor device (16) is mounted on the circuit board (17) by thermocompression bonding (called "temporary bonding") at a temperature (1) lower than the temperature at which the curing reaction of 1 (1) starts I do.
  • the heating and pressing jig 18 includes a heater and a thermocouple, and has a structure in which the heater can be heated and the temperature can be controlled by the thermocouple.
  • This temporary pressure bonding is performed at a temperature at which the fluidity of the adhesive resin 11 is low and a high viscosity state can be maintained.
  • the temperature is lower than the curing temperature of the adhesive resin 11 of the anisotropic conductive adhesive 13, specifically, a temperature of about 30 ° C. to 80 ° C.
  • the pressure P i of the temporary pressure bonding is a pressure of about 200 to 100 kg Zcm 2 with respect to the area of the portion to which the protruding electrode 14 is connected.
  • the pressure of the temporary press-bonding is such that the conductive particles 12 in the anisotropic conductive adhesive 13 are brought into contact with the protruding electrodes 14 of the semiconductor device 16 and the wiring patterns 15 of the circuit board 1, and between them. It is recommended that the pressure be high enough to provide electrical continuity.
  • the adhesive resin is slightly softened and has low fluidity and does not easily flow out between the protruding electrode 14 and the wiring pattern 15, a large number of conductive particles 12 are sandwiched between the two. be able to.
  • the heating jig 1 8 the pressure P is pressurized gala at 2, an anisotropic conductive adhesive 1 3 of the adhesive resin 1 1 of a temperature not lower than the curing temperature T Heat in 2
  • the pressure P 2 to be applied is a pressure of about 200 to 100 kg Zcm 2 with respect to the area of the semiconductor device 16 to which the protruding electrodes 14 are connected.
  • the pressure P 2 may be different from the pressure P at the time of temporary pressure bonding described above, greater than P i (Write P i P is preferred.
  • the semiconductor device is mounted by performing two-stage heating and pressurizing steps of temporarily bonding and then curing the adhesive resin 11.
  • the following functions and effects different from the above are obtained. The operation and effect will be described with reference to FIGS. 6 and 7.
  • FIGS. 6 and 7 are enlarged parts of the process shown in FIGS. 3 and 4 so that the conductive particles 12 sandwiched between the protruding electrodes 14 and the wiring patterns 15 can be seen.
  • FIG. 2 is a schematic cross-sectional view shown as follows. According to the present invention, as described above, when the semiconductor device 16 is mounted on the circuit board 17, as in the related art, the thermocompression bonding for curing the adhesive resin 11 of the anisotropic conductive adhesive 13 is performed. Not at once, but before that, sufficient pressure is applied through the temporary crimping process shown in Fig. 6.
  • the conductive particles 12 are slightly deformed (crushed) between the protruding electrodes 14 and the wiring patterns 15, the contact between the conductive particles 12 and the protruding electrodes 14 and the wiring patterns 15 is caused.
  • the area increases. Therefore, the conductivity is further improved, and the connection resistance is reduced.
  • FIG. 8 shows the number of conductive particles present between the protruding electrode and the wiring pattern when the semiconductor device is mounted by the conventional semiconductor device mounting method and when the semiconductor device is mounted by the semiconductor device mounting method according to the present invention. Shown in comparison.
  • the vertical axis of this figure indicates the number of conductive particles. From this figure, it can be seen that there are an average of eight conductive particles when mounted by the mounting method of the present invention, but about 5.5 on the conventional mounting method. Therefore, it can be seen that in the mounting method according to the present invention, more conductive particles remain in the connection portion.
  • the semiconductor device was mounted on a transparent glass plate by the method of the present invention and the conventional method so that the connection between the protruding electrode and the wiring pattern could be observed. The number of 2 was measured.
  • the step of completely curing the adhesive resin 11 of the anisotropic conductive adhesive 13 was performed by the pressurizing and heating step using the heating and pressing jig 18.
  • the circuit board 17 on which the semiconductor device 16 was temporarily crimped was placed in a furnace 20 set at a temperature of 150 ° C. to 250 ° C., which is a temperature at which the adhesive resin 11 hardened.
  • heat may be supplied from the heat source 21 of the furnace 20.
  • the semiconductor device 16 was temporarily press-fitted on a hot plate 30 set at a temperature of 150 ° C. to 250 ° C., which is a temperature at which the adhesive resin 11 hardens.
  • the circuit board 17 may be placed and heated for about 5 to 30 seconds.
  • hot play G30 incorporates a heater 30.
  • the adhesive resin is cured before the anisotropic conductive adhesive is cured. Since the temporary compression bonding is performed at a low fluidity temperature, a large number of conductive particles can be sandwiched between the protruding electrodes and the wiring pattern. Therefore, stable connection with low connection resistance is possible, and mounting with high connection reliability is possible.
  • connection portion since more conductive particles can be left in the connection portion, the area of the connection portion can be reduced while maintaining the same connection resistance as before. Therefore, it is possible to connect to finer wiring patterns than before, and it is suitable for high-density mounting.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

明 細 書
異方性導電接着剤を用いた半導体装置の実装方法 技 術 分 野
この発明は、 異方性導電接着剤を用いて回路基板上に半導体装置を接続して固定 する半導体装置の実装方法に関する。
背 景 技 術
従来から、 異方性導電接着剤を用いて回路基板上に半導体装置を接続して固定す る半導体装置の実装方法が実用化されている。 その従来の半導体装置の実装方法に ついて、 第 1 1図〜第 1 6図を用いて説明する。
第 1 1図〜第 1 4図は、 従来の半導体装置の実装方法の各工程を示す断面図であ る。 これらの図に示すように、 この実装方法では、 回路基板 1 7上に設けられた配 線パターン 1 5と半導体装置 1 6に形成された突起電極 1 4とを接続する。 その接 続の際に、 異方性導電接着剤 1 3中に含まれる導電性を有する導電粒子 1 2を配線 パターン 1 5と突起電極 1 4との間に挟み込み、 その導線粒子 1 2によって両者の 導通をとるようにしている。
異方性導電接着剤 1 3は、 エポキシ系接着剤からなる熱硬化性の接着剤樹脂 1 1 に導電粒子 1 2を混入させて導電性を持たせたものであり、 ベースフィルム上にフ イルム上に形成され、 カバ一フィルムで保護されている。 その導電性粒子 1 2は、 直径 5〜 1 0 μ mの銀やハンダなどからなる金属製粒子、 またはプラスチック製の 樹脂粒子の表面に金 （A u ) メツキを施したものである。
回路基板 1 7は、 ガラスエポキシ樹脂やセラミックまたはガラスからなる基板の 上に配線パターン 1 5が形成されている。 その配線パターン 1 5は、 銅や金からな るもの、 または液晶パネルなどで用いられている I T O (インジユウムとスズの酸 化物） 膜などからなっている。
そして、 半導体装置を実装する作業の工程は、 次の通りである。 まず、 第 1 1図に示すように、 回路基板 1 7の半導体装置 1 6を接続する部分に 異方性導電接着剤 1 3を転写する。
次に、 第 1 2図に示すように、 回路基板 1 7の配線パターン 1 5と半導体装置 1 6に形成された突起電極 1 4とを位置合わせして、 半導体装置 1 6を対向する回路 基板 1 7上に搭載する。
続いて、 第 1 3図に示すように、 ヒータを内蔵した加熱加圧治具 1 8を用いて圧 力 Pを加ながら加熱して半導体装置 1 6を回路基板 1 7に熱圧着し、 異方性導電接 着剤 1 3の接着剤樹脂 1 1を硬化させる。
そして、 接着剤樹脂 1 1が硬化すれば、 第 1 4図に示すように、 半導体装置 1 6 が回路基板 1 7上に接着固定され、 異方性導電接着剤 1 3の導電粒子 1 2によって 半導体装置 1 6の突起電極 1 4と配線パターン 1 5との間の導通が保持されること になる。
この実装方法では、 加熱加圧治具 1 8を用いて接着剤樹脂 1 1を硬化させるのに 必要な温度ではじめから熱圧着するが、 エポキシ系接着剤等の熱硬化性の接着剤樹 脂 1 1は、 ある温度以上に加熱されると急速に軟化して半溶融状態になった後に硬 化反応が進行して硬化する。 その熱圧着の前後の様子を拡大して第 1 5図及び第 1 6図に示す。
第 1 5図は、 半導体装置 1 6を回路基板 1 7上へ載置した時の状態、 すなわち第 1 3図に示した加熱加圧治具 1 8による加熱加圧前の状態を示し、 突起電極 1 4と 配線パターン 1 5間に存在する導電粒子 1 2の様子がわかるように、 半導体装置 1 6と回路基板 1 7の一部を拡大して示している。 この時点では、 加熱加圧前である から、 接着剤樹脂 1 1は転写されたフィルム上のままである。
次に、 第 1 6図に示すように、 接着剤樹脂 1 1を硬化させるために加熱加圧治具 1 8によって接着剤樹脂 1 1が硬化反応を起こす温度に加熱しながら半導体装置 1 6に圧力 Pを加えると、 接着剤樹脂 1 1が急速に硬化するとともに押しつぶされて 流動し、 半導体装置 1 6から外へはみ出してしまう。 突起電極 1 4と配線パターン 1 5との間隔は最も狭くなるため、 突起電極 1 4の付近にある接着剤樹脂 1 1は、 突起電極 1 4によって強く押し出され、 最も大きく流動する。
この接着剤樹脂 1 1の流動で導電粒子 1 2も一緒に突起電極 1 4の外へ押し出さ れてしまうため、 その後接着剤樹脂 1 1が硬化して熱圧着が完了した時、 導電粒子 1 2は、 突起電極 1 4の下面より外へはみ出した部分に多く存在するようになる。 そのため、 突起電極 1 4と配線パターン 1 5との間に残る導電粒子の数はわずかに なる。
このように、 従来の実装方法では、 熱圧着するときの加熱により異方性導電接着 剤 1 3の接着剤樹脂 1 1が硬化する前の一時的な軟化現象と、 半導体装置への加圧 力によって導電粒子 1 2が押し出され、 突起電極 1 4と配線パターン 1 5との間に 残る導電粒子 1 2の数が少なくなるため、 突起電極 1 4と配線パターン 1 5との接 続抵抗が高くなってしまうという問題があった。
その接続抵抗を低く押さえるには、 突起電極 1 4と配線パターン 1 5との間にで きるだけ多くの導電粒子 1 2を残す必要があるが、 そうするには、 多くの導電粒子 1 2を捕捉できるように両者の接続部分の面積を広くとる必要がある。
ところが、 高密度実装を行おうとすると、 接続部分の面積を小さくする必要があ るため、 突起電極 1 4と配線パターン 1 5との間に多くの導電粒子 1 2を捕捉する のは困難であり、 接続部分に残る導電粒子 1 2の数が少なくなつてしまう。 したが つて、 上述した従来の実装方法は、 接続抵抗値が高く不安定な接続になりやすく、 高密度実装には適さなかった。
この発明は、 異方性導電接着剤を用いた半導体装置の実装方法におけるこのよう な問題を解決するためになされたものであり、 半導体装置の突起電極と回路基板の 配線パターンとの間に捕捉される導電粒子の数を增やして、 接続部分の面積が小さ くても接続抵抗が低く安定な接続を可能にし、 高密度実装に適すようすることを目 的とする。
発明 の開示
この発明による異方性導電接着剤を用いた半導体装置の実装方法は、 上記の目的 を達成するため、 次の （1 ) から （4 ) の工程を有することを特徴とする。
( 1 ) 回路基板上の配線パターンが形成された部分に、 熱硬化性の接着剤樹脂に 導電粒子を混入させてなる異方性導電接着剤を配置する工程、
( 2 ) 半導体装置に設けられた突起電極を上記回路基板上の配線パターンに位置 合わせして該半導体装置を該回路基板上に搭載する工程、
( 3 ) 上記異方性導電接着剤の接着剤樹脂の硬化温度よりも低い温度で所定の圧 力を加えて上記半導体装置を上記回路基板に仮圧着する工程、
( 4 ) 上記接着剤樹脂が硬化する温度で該接着剤樹脂を硬化させ、 上記仮圧着 した半導体装置を上記回路基板上に接着する工程、
上記の半導体装置の実装方法において、 上記半導体装置を上記回路基板に仮圧着 する工程により、 半導体装置の突起電極と回路基板の配線パターンとの間の電気的 導通がとれるようにするのが望ましい。
また、 上記 （4 ) の工程を、 上記接着剤樹脂が硬化する温度に設定した、 加熱加 圧治具を用いて熱圧着することによって行なうことができる。
あるいは、 上記 （4 ) の工程を、 上記接着剤樹脂が硬化する温度に設定した炉内 に、 上記半導体装置を仮圧着した回路基板を置いて行なうか、 同様な温度に設定し たホットプレートの上に置いて行なうこともできる。
また、 半導体装置の実装方法において上記導電粒子を突起電極と配線パターンと に接触させるようにするとよい。
この発明による半導体装置の実装方法によれば、 回路基板上に半導体装置を実装 する際に、 異方性導電接着剤の接着剤樹脂の流動性が低い状態の温度で仮圧着を行 うので、 導電粒子が接着剤樹脂の粘度の低い状態で突起電極と配線パターンで挟み 込まれ、 突起電極と配線パターン間に数多く残る。 その後に接着剤樹脂を本硬化さ せるため、 接続部分に導電粒子が数多く残った状態で接続抵抗値が低く安定な接続 が可能になる。 さらに接続部分に導電粒子を数多く残せることから、 接続部分の面 積を小さくすることができ、 従来よりさらに微細な接続ピッチでの接続が可能にな る。
図面の簡単な説明
第 1図は、 この発明による半導体装置の実装方法に用いる異方性導電接着剤の一 部を拡大して示す模式的な断面図である。
第 2図〜第 5図は、 この発明による半導体装置の実装方法の一実施形態を説明す るための各工程を順に示す模式的な断面図である。
第 6図及び第 7図は、 それぞれ第 3図及び第 4図に示した工程の要部を拡大して 示す模式的な断面図である。
第 8図は、 この発明による半導体装置の実装方法により実装した半導体装置の突 起電極と回路基板の配線パターンとの間に挟まれる導電粒子数を、 従来例と比較し て示す線図である。
第 9図は、 この発明による半導体装置の実装方法における第 4図に示した工程に 代える他の工程の例を示す模式的な断面図である。
第 1 0図は、 この発明による半導体装置の実装方法における第 4図に示した工程 に代えるさらに他の工程の例を示す模式的な断面図である。
第 1 1図〜第 1 4図は、 従来の半導体装置の実装方法を説明するための各工程を 順に示す模式的な断面図である。
第 1 5図及び第 1 6図は、 それぞれ第 1 2図及び第 1 3図に示した各工程の要部 を拡大して示す模式的な断面図である。
発明を実施するための最良の形態
以下、 この発明による半導体装置の実装方法を実施するための最良の形態につい て、 第 1図から第 1 0図を用いて詳細に説明する。 なお、 第 1 1図から第 1 6図に 示した従来例と対応する部分には、 同一の符号を付している。
第 1図は、 この発明による半導体装置の実装方法に用いる異方性導電接着剤の一 部を拡大して示す模式的な断面図である。 なお、 異方性導電接着剤は、使用前では、 ベースフィルム上にフィルム状に形成され、 反対側の面をカバーフィルムによって 保護されているが、 それらの図示は省略している。 この異方性導電接着剤 1 3は、 厚さ 1 5 μ mから 1 0 0 μ m程度の接着剤樹脂 1 1の膜に直径 3 μ mから数十/ z m 程度の大きさの導電粒子 1 2を多数混入して、 厚さ方向に導電性を持たせた構造と なっている。
接着剤樹脂 1 1の厚さは 1 5 μ πιから 1 0 0 ju m程度としているが、 具体的な厚 さは、 第 6図等に示す実装しようとする半導体装置 1 6に形成された突起電極 1 4 の高さ （基板からの高さ） と、 回路基板 1 7上に設けられた配線パターン 1 5の高 さ （基板からの高さ） に応じて決定する。 たとえば、 突起電極の高さが 2 0 μ mで あり、 配線パターンの高さが 1 8 μ mであるとすると、 接着剤樹脂 1 1は、 両者を 合計した高さ （厚さ） 以上の厚さが必要となるので、 両者の合計である 3 8 μ m以 上の厚さに設定する。
また、 接着剤樹脂は印刷法や転写法などで膜状に形成されるが、 形成する際の精 度を考慮して、 実際は 1 0 μ m程度厚く形成する。 したがって上述の場合の接着剤 樹脂 1 1は、 3 8 μ mを 1 0 μ m程度厚く して 5 0 / m程度の厚さに形成する。 接着剤樹脂は、 エポキシ樹脂、 フ ノール樹脂等の絶縁性の熱硬化性樹脂、 たと えば、 エポキシ系熱硬化性樹脂を用いる。
接着剤樹脂 1 1に混入する導電粒子 1 2は、 直径 3〜数十/ i m程度の大きさを有 し、 銀やハンダなどからなる金属製粒子、 またはプラスチック製の樹脂粒子の表面 に金 （A u ) メツキを施した粒子である。
導電粒子 1 2の大きさは、 接続しょうとする配線パターン 1 5同士のギヤップ (間隔） によって変える。 たとえば、 ギャップが 1 0 μ mであるならば、 パターン 同士の間でショートが起こらないように、 導電粒子 1 2の直径を 1 0 mより小さ く設定する。 この導電粒子 1 2を接着剤樹脂 1 1に対して 4 w t % (重量。 /o ) の量 で添加した上で混練して異方性導電接着剤 1 3としている。
第 2図以降に示す回路基板 1 7は、 ガラスエポキシ樹脂やセラミックまたはガラ スからなる基板の上に配線パターン 1 5が形成されている。 その配線パターン 1 5 は、 銅や金からなるもの、 または液晶パネルなどで用いられている I T O (インジ ユウムとスズの酸化物） 膜などからなっている。
そして、 半導体装置 1 6を回路基板 1 7に実装する作業の工程は、 次の通りであ る。
この実装方法でも、 従来と同様に、 回路基板 1 7上に設けられた配線パターン 1 5と半導体装置 1 6に形成された突起電極 1 4とを接続する。 その接続の際に、 導 電性を有する導電粒子 1 2を配線パターン 1 5と突起電極 1 4との間に挟み込み、 その導線粒子 1 2によって両者の導通をとるようにしている。 なお、 その突起電極 1 4は、 半田、 金あるいは銅などの材料を用いてメツキ法や真空蒸着法などによつ て形成されたものである。
まず、 第 2図に示すように、 回路基板 1 7上の半導体装置 1 6を搭載する配線パ ターンが形成された部分に異方性導電接着剤 1 3を転写等によって配置する。 その 異方性導電接着剤 1 3は、 実装する半導体装置 1 6と平面的に同じ大きさ力 、 ある いはその外形よりも、 全周にわたって 2 m m程度大きい （広い） 範囲に配置する。 ベースフィルム上に形成された異方性導電接着剤 1 3を転写する場合には、 予め 異方性導電接着剤 1 3を転写しようとする領域に合わせて力ットし、 その力ッ トし た異方性導電接着剤 1 3を転写領域に配置して行なう。
その後、 ヒータで約 8 0 °Cから 1 0 0 °Cに加熱した加熱ヘッド （図示せず） を用 いて、 その配置した異方性導電接着剤 1 3を熱圧着することによって、 回路基板 1 7上に転写させる。 このときの圧力は、 異方性導電接着剤 1 3を回路基板 1 7に貼 り付けることができる程度の圧力でよレ、。 その後、 ベ一スフイルムを剥離する。
次に、第 3図に示すように、回路基板 1 7上に形成された配線パターン 1 5と、 半導体装置 1 6に形成された突起電極 1 4とを位置合わせして、 半導体装置 1 6を 回路基板 1 7上に搭載する。 そして、 ヒータを内蔵した加熱加圧治具 1 8により半 導体装置 1 6を突起電極 1 4が形成されていない背面側から所定の圧力 P iで加圧 するとともに、 異方性導電接着剤 1 3の接着剤樹脂 1 1の硬化反応が開始する温度 (「硬化温度」 という） よりも低い温度 1 で半導体装置 1 6を回路基板 1 7上に熱 圧着 （「仮圧着」 という） して搭載する。
加熱加圧治具 1 8は、 ヒータと熱電対を備えたもので、 ヒータで加熱し熱電対で 温度制御できる構造になっている。
この仮圧着は、 接着剤樹脂 1 1の流動性が低く高粘度状態を保てる温度で行われ る。 その温度は、 異方性導電接着剤 1 3の接着剤樹脂 1 1の硬化温度よりも低い温 度であり、 具体的には、 3 0 °Cから 8 0 °C程度の温度である。
また、 仮圧着の圧力 P iは、 突起電極 1 4の接続する部分の面積に対して、 2 0 0〜 1 0 0 0 k g Z c m2程度の圧力である。 この仮圧着の圧力は、異方性導電接着 剤 1 3内の導電粒子 1 2を半導体装置 1 6の突起電極 1 4と回路基板 1 Ίの配線パ ターン 1 5とに接触させ、 両者の間の電気的導通がとれる程度の圧力にするのが良 い。
この時、 接着剤樹脂は少し軟化する程度で流動性が低く、 突起電極 1 4と配線パ ターン 1 5との間から流出しにくいため、 両者の間に多数の導電粒子 1 2を挟持す ることができる。
続いて、 第 4図に示すように、 加熱加圧治具 1 8によって、 圧力 P 2で加圧しな がら、 異方性導電接着剤 1 3の接着剤樹脂 1 1の硬化温度以上の温度 T 2で加熱す る は 丁 この場合、 接着剤樹脂 1 1にエポキシ樹脂を用いた場合は、 この加熱する温度 τ
2は 1 5 0 °C〜 2 5 0 °C程度とし、 5秒〜 3 0秒間加熱する。 また加圧する圧力 P 2 は、 半導体装置 1 6の突起電極 1 4の接続する面積に対して 2 0 0〜 1 0 0 0 k g Z c m2程度の圧力である。 この圧力 P 2は、 前述の仮圧着時の圧力 P と異なって もよく、 P iより大きい （P i P 方が好ましい。
このように温度 T 2で加熱加圧治具 1 8による加圧加熱を行なうと、 異方性導電 接着剤 1 3の接着剤樹脂 1 1がー且軟化して半溶融状態になるが、 導電粒子 1 2は 突起電極 1 4と配線パターン 1 5との間に挟み込まれているので流出することはな く、 その後に硬化反応が進行して接着剤樹脂 1 1が硬化し、 第 5図に示すように半 導体装置 1 6が回路基板 1 7上に接着され、 半導体装置 1 6の突起電極 1 4と配線 パターン 1 5との間の導通も挟み込まれた複数の導電粒子 1 2によって確実に保持 されることになる。
以上のように、 この発明による半導体装置の実装方法では、 仮圧着してから、 接 着剤樹脂 1 1を硬化させるという 2段階の加熱加圧を行なうことによって半導体装 置を搭載するので、 従来とは異なる次のような作用効果を奏する。 その作用効果を 第 6図と第 7図を用いて説明する。
第 6図と第 7図は、 第 3図と第 4図に示した工程の要部を突起電極 1 4と配線パ ターン 1 5間に挟まれる導電粒子 1 2の様子がわかるように、 拡大して示した模式 的な断面図である。 この発明では、 前述のように、 半導体装置 1 6を回路基板 1 7 に搭載する際に、 従来のように、 異方性導電接着剤 1 3の接着剤樹脂 1 1を硬化さ せる加熱圧着を一時に行なわず、 その前に第 6図に示す仮圧着の工程を経て充分な 加圧を行なっている。
そのため、 第 7図に示すように接着剤樹脂 1 1を硬化させる加熱加圧を行なう時 には、 既に導電粒子 1 2が突起電極 1 4と配線パターン 1 5間に挟まれている （図 では 4個）。 したがって、その後に接着剤樹脂 1 1を硬化させるための加熱を行なつ ても、 導電粒子 1 2は突起電極 1 4と配線パターン 1 5の間に挟まれた状態に維持 され、 たとえ接着剤樹脂 1 1が流動することがあっても、 突起電極 1 4の外に流れ 出すことはない。 よって、 突起電極 1 4と配線パターン 1 5とに接触させつつ双方 の間により多くの導電粒子 1 2を捕捉することができる。 なお、 導電粒子 1 2は突 起電極 1 4と配線パターン 1 5との間に挟まれて若干変形 （つぶれる） ため、 導電 粒子 1 2と突起電極 1 4及び配線パターン 1 5とのそれぞれの接触面積が広くなる。 したがって、 一層導電性が良好となり、 接続抵抗が低くなる。
ここで、 第 8図に、 従来の半導体装置の実装方法により実装した場合と、 この発 明による半導体装置の実装方法により実装した場合の、 突起電極と配線パターン間 に存在する導電粒子の数を比較して示す。 この図の縦軸は導電粒子の数を示してい る。 この図から、 この発明による実装方法で実装した場合には平均 8個の導電粒子 が存在するが、 従来の実装方法による場合には、 平均 5 . 5個程度である。 したが つて、 この発明による実装方法の方が、 多くの導電粒子が接続部分に残っているこ とが分かる。
なお、 突起電極と配線パターンとの接続部分が観察できるように、 透明なガラス 板に対してこの発明および従来のそれぞれの方法で半導体装置を実装し、 突起電極 部分に残されている導電粒子 1 2の個数を測定した。
上述した実施形態では、 異方性導電接着剤 1 3の接着剤樹脂 1 1を完全に硬化さ せる工程を、 加熱加圧治具 1 8を用いた加圧加熱工程により行なったが、 第 9図に 示すように、 接着剤樹脂 1 1が硬化する温度である 1 5 0 °C〜 2 5 0 °Cに設定した 炉 2 0の中に、 半導体装置 1 6を仮圧着した回路基板 1 7を置いて、 炉 2 0の熱源 2 1から熱を供給して行ってもよい。
あるいは、 第 1 0図に示すように接着剤樹脂 1 1が硬化する温度である 1 5 0 °C 〜 2 5 0 °Cに設定したホットプレート 3 0上に、 半導体装置 1 6を仮圧着した回路 基板 1 7を置いて 5秒〜 3 0秒間程度加熱して行ってもよい。 なお、 ホッ トプレー ト 3 0は、 ヒータ 3 0を内蔵している。
産業上の利用可能性
この発明による半導体装置の実装方法では、異方性導電接着剤を用いて半導体装 置を回路基板上に熱圧着する際に、 異方性導電接着剤を硬化させる前に、 接着剤樹 脂の流動性が低い温度で仮圧着を行なうため、 導電粒子を数多く突起電極と配線パ ターン間に挟持することができる。 したがって、 接続抵抗値が低く安定な接続が可 能になり接続信頼性の高い実装が可能になる。
また、 導電粒子をより多く接続部分に残すことが出来るため、 これまでと同じ接 続抵抗を維持しながら、 接続部分の面積を小さくすることができる。 したがって、 従来より微細な配線パターンへの接続も可能になり、 高密度実装に適する。

Claims

請 求 の 範 囲
1 . 回路基板上の配線パターンが形成された部分に、 熱硬化性の接着剤樹脂に導電 粒子を混入させてなる異方性導電接着剤を配置する工程と、
半導体装置に設けられた突起電極を前記回路基板上の配線パターンに位置合わせ して該半導体装置を該回路基板上に搭載する工程と、
前記異方性導電接着剤の接着剤樹脂の硬化温度よりも低い温度で所定の圧力を加 えて前記半導体装置を前記回路基板に仮圧着する工程と、
前記接着剤樹脂が硬化する温度で該接着剤樹脂を硬化させ、 前記仮圧着した半導 体装置を前記回路基板上に接着する工程と
を有することを特徴とする異方性導電接着剤を用いた半導体装置の実装方法。
2 . 前記半導体装置を前記回路基板に仮圧着する工程により、 該半導体装置の前記 突起電極と該回路基板の前記配線パターンとの間の電気的導通がとれるようにする 請求の範囲第 1項に記載の異方性導電接着剤を用いた半導体装置の実装方法。
3 . 前記仮圧着した半導体装置を回路基板上に接着する工程を、
前記接着剤樹脂が硬化する温度に設定した、 加熱加圧治具を用いて熱圧着するこ とによつて行なう請求の範囲第 1項に記載の異方性導電接着剤を用いた半導体装置 の実装方法。
4 . 前記仮圧着した半導体装置を回路基板上に接着する工程を、
前記接着剤樹脂が硬化する温度に設定した炉内に、 前記半導体装置を仮圧着した 回路基板を置いて行なう請求の範囲第 1項または第 2項に記載の異方性導電接着剤 を用いた半導体装置の実装方法。
5 . 前記仮圧着した半導体装置を回路基板上に接着する工程を、
前記接着剤樹脂が硬化する温度に設定したホットプレート上に、 前記半導体装置 を仮圧着した回路基板を置いて行なう請求の範囲第 1項に記載の異方性導電接着剤 を用いた半導体装置の実装方法。
6 . 前記半導体装置を前記回路基板に仮圧着する工程において、 前記導電粒子を該 半導体装置の前記突起電極と該回路基板の前記配線パターンとに接触させることを 特徴とする請求の範囲第 1項に記載の異方性導電接着剤を用いた半導体装置の実装 方法。
PCT/JP2000/000420 1999-01-27 2000-01-27 Method of packaging semiconductor device using anisotropic conductive adhesive WO2000045431A1 (en)

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BR0004470-9A BR0004470A (pt) 1999-01-27 2000-01-27 Método para acondicionar um dispositivo semicondutor usando adesivo condutor anisotrópico
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204142A (ja) * 2002-01-08 2003-07-18 Sumitomo Metal Micro Devices Inc 電子部品実装方法及び電子部品実装装置
WO2017163721A1 (ja) * 2016-03-25 2017-09-28 デクセリアルズ株式会社 接続構造体の製造方法
JP2018174307A (ja) * 2017-03-30 2018-11-08 芝浦メカトロニクス株式会社 圧着装置

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3301075B2 (ja) * 1999-04-20 2002-07-15 ソニーケミカル株式会社 半導体装置の製造方法
FR2812223B1 (fr) * 2000-07-28 2003-11-07 Thomson Csf Procede de collage de substrats de circuit electronique sur une semelle et dispositif de mise en oeuvre du procede
DE10120928C1 (de) * 2001-04-30 2002-10-31 Infineon Technologies Ag Verfahren zum Erstellen einer Kontaktverbindung zwischen einem Halbleiterchip und einem Substrat, insbesondere zwischen einem Speichermodulchip und einem Speichermodulboard
JP3886401B2 (ja) * 2002-03-25 2007-02-28 ソニーケミカル＆インフォメーションデバイス株式会社 接続構造体の製造方法
JP2004260135A (ja) * 2003-02-06 2004-09-16 Sanyo Electric Co Ltd 半導体集積装置及びその製造方法
JP3835556B2 (ja) * 2003-10-27 2006-10-18 セイコーエプソン株式会社 半導体装置の製造方法及び半導体装置の製造装置
JP4432949B2 (ja) * 2006-09-15 2010-03-17 パナソニック株式会社 電気部品の接続方法
CN101303443A (zh) * 2007-05-11 2008-11-12 鸿富锦精密工业（深圳）有限公司 相机模组及其组装方法
JP5093482B2 (ja) * 2007-06-26 2012-12-12 ソニーケミカル＆インフォメーションデバイス株式会社 異方性導電材料、接続構造体及びその製造方法
JP5622137B2 (ja) * 2007-10-29 2014-11-12 デクセリアルズ株式会社 電気的接続体及びその製造方法
WO2010151600A1 (en) 2009-06-27 2010-12-29 Michael Tischler High efficiency leds and led lamps
JP5732631B2 (ja) 2009-09-18 2015-06-10 ボンドテック株式会社 接合装置および接合方法
US9480133B2 (en) 2010-01-04 2016-10-25 Cooledge Lighting Inc. Light-emitting element repair in array-based lighting devices
US8653539B2 (en) 2010-01-04 2014-02-18 Cooledge Lighting, Inc. Failure mitigation in arrays of light-emitting devices
WO2012000114A1 (en) 2010-06-29 2012-01-05 Cooledge Lightning Inc. Electronic devices with yielding substrates
JP2012204588A (ja) * 2011-03-25 2012-10-22 Disco Abrasive Syst Ltd 半導体デバイスチップの実装方法
JP2012204589A (ja) * 2011-03-25 2012-10-22 Disco Abrasive Syst Ltd 半導体デバイスウエーハの接合方法
US20130032270A1 (en) * 2011-08-01 2013-02-07 Texas Instruments Incorporated Thermal compression bonding with separate bond heads
US20130056749A1 (en) * 2011-09-07 2013-03-07 Michael Tischler Broad-area lighting systems
US8896010B2 (en) 2012-01-24 2014-11-25 Cooledge Lighting Inc. Wafer-level flip chip device packages and related methods
WO2013112435A1 (en) 2012-01-24 2013-08-01 Cooledge Lighting Inc. Light - emitting devices having discrete phosphor chips and fabrication methods
US8907362B2 (en) 2012-01-24 2014-12-09 Cooledge Lighting Inc. Light-emitting dies incorporating wavelength-conversion materials and related methods
US8877561B2 (en) 2012-06-07 2014-11-04 Cooledge Lighting Inc. Methods of fabricating wafer-level flip chip device packages
US20140069696A1 (en) * 2012-09-11 2014-03-13 Apple Inc. Methods and apparatus for attaching multi-layer flex circuits to substrates
JP6163838B2 (ja) * 2013-04-05 2017-07-19 富士電機株式会社 加圧加熱接合構造及び加圧加熱接合方法
WO2015119858A1 (en) 2014-02-05 2015-08-13 Cooledge Lighting Inc. Light-emitting dies incorporating wavelength-conversion materials and related methods
DE102014104510B4 (de) * 2014-03-31 2019-02-07 Gottfried Wilhelm Leibniz Universität Hannover Verfahren zum Fügen und Einrichtung zum Fügen einer Anordnung unter Verwendung des Verfahrens
US9720696B2 (en) 2014-09-30 2017-08-01 International Business Machines Corporation Independent mapping of threads
US10133576B2 (en) 2015-01-13 2018-11-20 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
WO2016153069A1 (ja) * 2015-03-26 2016-09-29 デクセリアルズ株式会社 可撓性実装モジュール体の製造方法
JP6935702B2 (ja) * 2016-10-24 2021-09-15 デクセリアルズ株式会社 異方性導電フィルム
US10420222B2 (en) * 2017-04-20 2019-09-17 Palo Alto Research Center Incorporated Method for bonding discrete devices using anisotropic conductive film
US10795452B2 (en) * 2018-02-07 2020-10-06 Microsoft Technology Licensing, Llc Multi-stage cure bare die light emitting diode
KR20200126269A (ko) * 2019-04-29 2020-11-06 삼성전자주식회사 접합헤드 및 이를 구비하는 접합 장치
CN114597138A (zh) * 2020-12-03 2022-06-07 群创光电股份有限公司 半导体封装的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197837U (ja) * 1984-12-04 1986-06-23
JPH09219579A (ja) * 1996-02-13 1997-08-19 Oki Electric Ind Co Ltd 電子部品の接続方法及び接続装置
JPH1032380A (ja) * 1996-07-16 1998-02-03 Hitachi Techno Eng Co Ltd 基板加熱方法及び基板加熱炉
JPH10289929A (ja) * 1997-04-14 1998-10-27 Seiko Epson Corp 表面実装部品の実装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197837A (ja) 1984-10-18 1986-05-16 Matsushita Electronics Corp 半導体エツチング装置
EP0641019A3 (en) * 1993-08-27 1995-12-20 Poly Flex Circuits Inc Flexible lead frame printed on a polymer.
TW340132B (en) * 1994-10-20 1998-09-11 Ibm Structure for use as an electrical interconnection means and process for preparing the same
JP3842362B2 (ja) * 1996-02-28 2006-11-08 株式会社東芝 熱圧着方法および熱圧着装置
US5943558A (en) * 1996-09-23 1999-08-24 Communications Technology, Inc. Method of making an assembly package having an air tight cavity and a product made by the method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197837U (ja) * 1984-12-04 1986-06-23
JPH09219579A (ja) * 1996-02-13 1997-08-19 Oki Electric Ind Co Ltd 電子部品の接続方法及び接続装置
JPH1032380A (ja) * 1996-07-16 1998-02-03 Hitachi Techno Eng Co Ltd 基板加熱方法及び基板加熱炉
JPH10289929A (ja) * 1997-04-14 1998-10-27 Seiko Epson Corp 表面実装部品の実装方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1067598A4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204142A (ja) * 2002-01-08 2003-07-18 Sumitomo Metal Micro Devices Inc 電子部品実装方法及び電子部品実装装置
WO2017163721A1 (ja) * 2016-03-25 2017-09-28 デクセリアルズ株式会社 接続構造体の製造方法
JP2017175045A (ja) * 2016-03-25 2017-09-28 デクセリアルズ株式会社 接続構造体の製造方法
TWI713423B (zh) 2016-03-25 2020-12-11 日商迪睿合股份有限公司 連接結構體之製造方法及異向性導電接著劑
US10954416B2 (en) 2016-03-25 2021-03-23 Dexerials Corporation Method for manufacturing connection structure
JP2018174307A (ja) * 2017-03-30 2018-11-08 芝浦メカトロニクス株式会社 圧着装置

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