WO1997008752A1 - Dispositif semiconducteur mis - Google Patents

Dispositif semiconducteur mis Download PDF

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Publication number
WO1997008752A1
WO1997008752A1 PCT/JP1995/001691 JP9501691W WO9708752A1 WO 1997008752 A1 WO1997008752 A1 WO 1997008752A1 JP 9501691 W JP9501691 W JP 9501691W WO 9708752 A1 WO9708752 A1 WO 9708752A1
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WO
WIPO (PCT)
Prior art keywords
type
mis
region
semiconductor
source
Prior art date
Application number
PCT/JP1995/001691
Other languages
English (en)
Japanese (ja)
Inventor
Masafumi Miyamoto
Kazuo Yano
Yasuhiko Sasaki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001691 priority Critical patent/WO1997008752A1/fr
Publication of WO1997008752A1 publication Critical patent/WO1997008752A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Definitions

  • the present invention relates to a MIS type semiconductor device, and more particularly to a pass transistor logic circuit or a selector circuit using a transistor formed in a thin film semiconductor layer on an insulating film.
  • the circuit power shown in Fig. 5 is known as a commonly used pass transistor logic circuit (K. Yano, et.al., IEEE Journal of Solid-State Cir Cuits, Vol. 25, No. 2, p P 388-395 (1990) ).
  • the logic circuit shown in Fig. 5 is formed on a so-called bulk semiconductor substrate, and the Ql and Q7 source Z drain regions of an n-type MOS transistor (NMOS) are connected to each other to form an output amplifier circuit.
  • NMOS n-type MOS transistor
  • the gate of Q1 is connected to the control signal input terminal C, and the gate of Q7 is connected to the inverted signal from the terminal C through the inverter.
  • the conventional pass transistor logic circuit described above operates at high speed with a small circuit area
  • the use of two NMOSs (Ql and Q7) in the selector circuit limits the reduction in circuit area.
  • the selector circuit is composed of NMOSs (Ql, Q7), one of the input signals C of the gates of the two NM ⁇ S (Ql, Q7) inputs the inverted control signal. Therefore, an inverter is required for this, and the area for this inverter increases. Further, in such a configuration, not only the circuit area but also the power consumption for driving the inverter increases.
  • FIG. 4 is a layout diagram of the conventional pass transistor logic circuit shown in FIG. 5, which was studied by the inventor prior to the present invention.
  • reference numeral 1 denotes a two-input selector circuit shown in FIG.
  • the N-type semiconductor region 2 and the gate electrode 4 constitute the selector circuits Q 1 and Q 7, and the N-type semiconductor region 2-6 and the gate electrode 4 constitute the control signal inverting inverter 13.
  • the PMOS constituting the inverter 13 is constituted by the P-type semiconductor region 3-6 and the gate electrode 4, and the N-type semiconductor region 2-1 and the P-type semiconductor region 3-1 and the gate electrode 4-
  • the output inverter 12 is constituted by 1, and each transistor is connected by the metal wiring 6.
  • the area of the element corresponding to the semiconductor region constituting the inverter 13 has increased.
  • the PMOS transistor must be formed on the upper side in the figure and the NMOS transistor must be formed on the lower side in the figure because of the formation of the p-well region, but since the number of NMOS transistors is larger than the number of PMOS transistors, the PMOS side As a result, an extra empty area is formed and an efficient layout cannot be achieved.
  • Japanese Unexamined Patent Publication No. Hei 6-13886 discloses that a transistor constituting a selector (corresponding to Ql and Q7 in FIG. 5) is formed by a PMOS and an NMOS. What constitutes is disclosed.
  • the PMOS gate potential is connected to the power supply, and a single-level input signal is applied to the output point of the selector circuit corresponding to the node d in FIG. When output, the potential at the output point goes low.
  • Substrate bias is applied as the bell approaches.
  • the threshold value rises due to the substrate bias effect, and the potential at the output point does not reach the complete ground level but remains at a potential substantially equal to the threshold voltage increased due to the substrate bias effect.
  • the NMOS transistor of the selector circuit using the pass transistor is connected to the ground, and when a high-level input signal is output to the output point, the potential of the output point approaches a high level.
  • a substrate bias is applied, and the potential at the output point increases only to a potential obtained by subtracting the threshold voltage increased by the substrate bias effect from the power supply voltage.
  • the amplitude of the output signal at the output point corresponding to the node d is a value obtained by subtracting the threshold values of both NMOS and PMOS, which have risen due to the body bias effect, from the power supply voltage.
  • the operating speed is extremely deteriorated under the power supply voltage (see Fig. 6 described later). For this reason, in a transistor simply formed on a bulk semiconductor substrate as in the conventional example, it is practically impossible to use both NMOS and PMOS as a selector circuit.
  • an object of the present invention is to provide a MIS type semiconductor device which satisfies demands for high speed operation and low power consumption while significantly reducing the area of a logic circuit using pass transistors.
  • Still another object of the present invention is to provide a layout of elements suitable for realizing the above-mentioned MIS semiconductor device.
  • an MIS type semiconductor device according to a representative embodiment of the present invention.
  • An output buffer circuit (1 2) having a common drain buffer region, wherein one of the source and drain regions of the first MISFET and one of the source and drain regions of the second MISFET are shared by the output buffer.
  • a gate electrode of the first MISFET and a gate electrode of the second MISFET are connected in common;
  • the first MISFET and the second MISFET are formed in a semiconductor base region (16, 17) formed on an insulating film (9).
  • the pass transistor logic circuit As described above, by forming the pass transistor logic circuit with the P-type MISFET and the N-type MISFET, an inverter for inverting the control signal is not required, thereby reducing the circuit area and the power consumption. it can. Furthermore, by forming the substrate on a so-called SOI substrate on an insulating film, it is possible to prevent a reduction in operating speed due to the substrate effect and to enable a high-speed operation even at a low power supply voltage.
  • the first input signal (X) is applied to the other source / drain region of the first MISFET
  • the second input signal (Y) is applied to the other source ⁇ drain region of the MIS FET
  • the first control signal (C 1) is commonly applied to the gate electrodes of the first and second MIS FETs. Is applied, and the first or second input signal is selectively transmitted to the first or second source / drain region according to the value of the first control signal. Can be configured.
  • the semiconductor base region includes a first region (16) and a second region (17) separated by an insulating film.
  • the first MISFET (Q 1) is formed in the first region
  • the second MISFET (Q 2) is formed in the second region
  • the first region is formed in the first region.
  • the inversion layer is formed in the channel region of the MIS FET
  • the depletion layer is completely depleted when the inversion layer is formed, and the inversion layer is formed in the channel region of the second MIS FET in the second region.
  • the semiconductor substrate region can be operated in a floating state, and a high-speed circuit operation can be realized without receiving a substrate bias effect.
  • the MIS type semiconductor device according to another representative embodiment of the present invention has an output amplifying inverter (12) and another latch (14) an inverter so that the amplitude of the output signal of the circuit can be sufficiently increased. That can be kept.
  • the gate electrodes of the MIS transistors (Ql, Q2) forming the selector are formed of a tungsten material, so that the two transistors can be connected to each other.
  • the threshold values can be made uniform, and the configuration is suitable for control by the common control signal (C1).
  • an MIS type semiconductor device electrically connects the plurality of semiconductor regions (16, 17) formed on the insulating film (9) with the plurality of semiconductor regions.
  • the second semiconductor region and the fourth semiconductor region are formed adjacent to each other in the first direction so as to planarly overlap with the power supply wiring, and the first gate electrode is The second gate electrode extends commonly on the first and second semiconductor regions, and the second gate electrode extends commonly on the third and fourth semiconductor regions.
  • One source 'drain region is connected to one source of the second MISFET.
  • the drain region is connected to the second gate electrode by a first metal wiring (6).
  • One source / drain region and one source / drain region of the fourth MISFET are connected by a second metal wiring (6-1), and the other source / drain region of the third MISFET is connected. Is connected to the ground wiring, and the other source / drain region of the fourth MISFET is connected to the power supply wiring.
  • the above-described logic circuit can be efficiently laid out on the SOI substrate.
  • a MIS semiconductor device includes a third n-type MIS FET formed in a fifth semiconductor region, which is one of the plurality of semiconductor regions.
  • the third good electrode is arranged adjacent to the second semiconductor region, the third good electrode is commonly extended on the fifth and sixth semiconductor regions, and one of the source electrodes of the third n-type MISF ET is provided.
  • the drain region is connected to one of the sources of the third p-type MISFET ⁇
  • the drain region is connected to the other source of the first n-type MISFET ⁇
  • the drain region is connected by the third metal wiring (6-2) It has been done.
  • a MIS semiconductor device includes a fourth n-type MISFET formed in a seventh semiconductor region, which is one of the plurality of semiconductor regions.
  • the fourth metal wiring is electrically connected to the first metal wiring and one of the source / drain regions of the fourth n-type MISFET and the fourth p-type MISFET. They are connected. According to the present invention, by adopting such a configuration, a selector circuit including the above-described latch inverter circuit (14) can be efficiently arranged.
  • FIG. 1 is a layout diagram showing a first embodiment which is a typical embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a first embodiment which is a typical embodiment of the present invention.
  • FIG. 3 is a view showing a process flow of a first embodiment which is a typical embodiment of the present invention.
  • FIG. 4 is a layout diagram examined by the inventor of the present invention based on a circuit diagram of a conventional example.
  • FIG. 5 is a circuit diagram showing a conventional example.
  • FIG. 6 is a diagram showing the drain voltage dependence of the gate delay time.
  • FIG. 7 is a layout diagram showing a second embodiment which is a typical embodiment of the present invention.
  • FIG. 8 is a circuit diagram showing a second embodiment which is a typical embodiment of the present invention.
  • FIG. 9 is a layout diagram showing a third embodiment which is a typical embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a second embodiment which is a typical embodiment of the present invention.
  • FIG. 11 is a layout diagram showing a fourth embodiment which is a typical embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing a fourth embodiment which is a typical embodiment of the present invention.
  • FIG. 13 is a layout diagram showing a fifth embodiment which is a typical embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing a fifth embodiment which is a typical embodiment of the present invention.
  • MOS FET silicon MOS transistor
  • MISFET MOS transistor
  • the OS transistor and the p-type MOS transistor are distinguished by the direction of the arrow shown in the channel portion.
  • FIG. 1 A first embodiment of the present invention is shown in FIG. 1, FIG. 2 and FIG.
  • FIG. 2 is a circuit diagram showing a two-input selector according to the first embodiment of the present invention. No.
  • the circuit shown in FIG. 2 is a basic configuration of a so-called two-input selector using pass transistors, and a desired logic circuit can be formed by this basic configuration or by appropriately combining this basic configuration.
  • the n-type MOS transistor Q1 and the p-type MOS transistor Q2 are formed on a thin-film SOI substrate.
  • one of the source'drain terminal of Q1 and one of the source'drain terminal of Q2 are commonly connected, and the common connection point is an inverter which is an output amplification buffer. It is connected to 12 input terminals, and is configured so that an output signal can be obtained from the output terminal OUT from INVERK 12.
  • the other input X of the source and drain terminals of Q1 is supplied with the first input signal
  • the other input signal Y of the source and drain terminals of Q2 is supplied with the second input signal
  • the gate terminals C of Q1 and Q2 are supplied.
  • the circuit in Fig. 2 shows one of the signals X and Y input to the source and drain terminals X and Y of the N-type MOS transistor (NM ⁇ S) Q1 and the P-type MOS transistor (PMOS) Q2. Is selected by the control signal C1 directly connected to the gates of Q1 and Q2, and the inverted signal is output to the OUT terminal through the output amplification inverter.
  • C1 is at the high level, the signal at the X terminal is selected, and when it is at the single level, the signal at the Y terminal is selected.
  • the inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier.
  • Q 1 and Q 2 are configured as n-type and p-type, respectively, even if the control signal C 1 is commonly supplied to each gate electrode, only one input signal is supplied to the inverter 12. This eliminates the need to invert the control signal as in the prior art.
  • this circuit becomes a logic circuit that operates as a two-input NAND circuit.
  • FIG. 1 is a layout diagram of the first embodiment formed on a thin-film SO 1 substrate, and FIG. 3 shows a manufacturing method thereof.
  • FIGS. 3 (a) to 3 (e) The cross-sectional view shown in FIG. 3 is AA ′ in FIG.
  • FIG. 3 (a) shows an SOI structure substrate on which the semiconductor device of the present invention is formed.
  • the SOI substrate has a thickness of about 400 on the semiconductor substrate 11 made of silicon single crystal.
  • An oxide film 9 which is an insulating film of nm is formed, and a thin film semiconductor layer 10 of about 100 nm serving as a base on which a MOS transistor is formed is formed thereon.
  • such a Si substrate can be thermally treated by bonding an Si (silicon) substrate having an oxide film formed thereon to another Si substrate, or by implanting oxygen ions into the Si substrate. Can be formed.
  • a protective oxide film 15 on the surface and an element isolation region 20 are formed by thermal oxidation.
  • the element isolation region 20 is a LO COS oxide film (local oxide film) formed by a so-called selective oxidation method.
  • the semiconductor regions .16 and 17 serving as bases are formed to a thickness of about 100 nm or less, and each have an impurity concentration of about 1 ⁇ 10 16 cm 3 . This is for controlling the semiconductor regions 16 and 17 to be completely depleted during the operation of the circuit, and by thus depleting the semiconductor regions to a floating state without applying a substrate potential to the semiconductor regions. This is to enable operation without being affected by the effect.
  • the element isolation region 1 is formed so as to be in contact with the insulating film 9 constituting the SOI substrate, so that the region for forming the transistor can be completely separated for each transistor to ensure electrical insulation. Can be done.
  • impurities for controlling the threshold are introduced into the region 16 where the n-channel MOS transistor is formed and the region 17 where the p-channel MOS transistor is formed.
  • the surface protective oxide film 15 protects the surface of the base when powerful impurities are introduced by ion implantation.
  • 2 ⁇ 10 12 cm 2 ion implantation of phosphorus at 30 keV is performed on the PMOS channel region 16 so as to obtain a desired threshold value.
  • boron is ion-implanted at 50 keV into 2 ⁇ 10 12 squared Z square cm.
  • a gate oxide film 7 of about 6 nm is formed by thermal oxidation.
  • tungsten is vapor-deposited on the entire surface and processed into a desired shape to form gate electrodes 4 and 4-1.
  • the work function between the high-concentration n-type silicon and the high-concentration p-type silicon is set so that the threshold values of NM OS and PMOS become the desired value (0.2 to 0.5 V in absolute value) with one gate material.
  • tungsten As a gate material, a polycrystalline silicon film into which impurities are introduced, or a laminated film of a polycrystalline silicon film and a metal material can be used.
  • the threshold voltage is lower when using n-type impurity-doped polycrystalline silicon as the NMOS gate electrode, and when using p-type impurity-doped polycrystalline silicon. (It fluctuates similarly in the case of PMOS, but the fluctuation is upside down as in the case of NMOS). Therefore, in order to match the threshold values of both MOSs, the work function between polycrystalline silicon with a high concentration of n-type impurity introduced and polycrystalline silicon with a high concentration of p-type impurity introduced must be determined. It is desirable to use W (tungsten) or the like for the gate electrode. In the case of this embodiment, since a control signal is applied to both transistors in common, it is necessary to control the value voltage to the same value.
  • TiN titanium nitride
  • Mo mobdenum
  • the tungsten used in the present embodiment is used. Is more preferable.
  • the source and drain regions of the MOS transistor are formed by ion implantation.
  • Arsenic is ion-implanted on the NMOS side at 3 O ke V at 2 ⁇ 10 15 square cm, and self-aligned using the gate electrode and isolation oxide film as a mask, the n + source / drain region 2 -Form one.
  • boron fluoride is ion-implanted at 30 keV at 2 ⁇ 10 15 square cm, and the p + source / drain region 3 is formed in a self-aligned manner.
  • an oxide film 8 is deposited in the same manner as in a normal wiring forming step, a contact hole 5 is processed, and then an anoremi is deposited and processed into a desired pattern.
  • the second-layer interlayer insulating film 16 and the second-layer metal wiring 17 are processed in the same manner and completed. If necessary, the third and fourth layers and wiring can be stacked.
  • FIG. 3 (e) shows a completed cross-sectional view of this embodiment, omitting the final passivation protective film and the like.
  • an NMOS and a PMOS are formed on a so-called SOI substrate, and these transistors form the circuit shown in FIG.
  • FIG. 1 shows a layout diagram of the present embodiment. 1 in FIG. 1 shows the layout when the two-input selector circuit shown in FIG. 2 is formed on a semiconductor substrate as a semiconductor integrated circuit.
  • FIG. 1 shows one layout diagram of a two-input selector circuit, a desired logic circuit can be obtained by appropriately arranging and wiring a plurality of selector circuits in accordance with this layout.
  • a cell 1 which is one unit circuit block is constituted by a two-input selector circuit, another cell is constituted in another 1-1 part on the right side of the drawing, and a cell row is arranged in a horizontal direction in the drawing. Is configured.
  • channel regions 101 and 102 extending in the horizontal direction are formed at the upper and lower portions of the cell column, and wiring 103, 104, 105, etc. are provided between cells and between cell columns. (Note that the wirings 102 to 105 in the figure are only schematic and detailed description is omitted. The wiring of the channel region 102 is also the same. Omitted).
  • Fig. 1, 2 and 2-1 are n-type semiconductor regions serving as source and drain regions of n-type MOS, and 3 and 3-1 are p-type semiconductor regions serving as source and drain regions of p-type MOS.
  • Reference numerals 4 and 4-1 denote gate electrodes of the MOS transistors, which are formed on the semiconductor substrate through a relatively thin gate insulating film 7 by tungsten, polycrystalline silicon, or a laminated film of polycrystalline silicon and silicide.
  • Reference numerals 6 and 6-1 denote metal wirings, which are formed of a metal material containing aluminum as a main component or the like on a wiring layer on which a gate electrode is formed via an interlayer insulating film. Further, as described above, the unit circuits and the like shown in FIG.
  • cell row 1 are repeatedly arranged in a row in the left-right direction of the drawing to form a so-called cell row. Further, a plurality of cell rows are formed as wiring areas between the cell rows. It is arranged and wired in the vertical direction of the drawing via the channel regions 101 and 102 to form a desired logic circuit.
  • the semiconductor region 2 is a semiconductor region constituting the n-type MOS transistor Q1 shown in FIG. Q 1 is configured as one of the switches of the selector circuit, and is configured so that the input signal X is supplied to the drain region of the semiconductor region 2 via the output of the adjacent cell or the wiring of the channel region. You. Further, a gate electrode 4 is formed on the semiconductor region 2, and a control signal C1 is supplied from outside the two-input selector circuit 1 via a contact through a contact.
  • the semiconductor region 3 is a semiconductor that constitutes the p-type MOS transistor Q2 shown in FIG.
  • the input signal Y is supplied to the drain region, and the control signal C 1 is supplied via the gate electrode 4.
  • the control signal C1 can be commonly supplied to both transistors without inversion, so that the gate electrode 4 is common to both transistors even in the layout. It can be that of.
  • the gate electrode 4 extends in the vertical direction with respect to the semiconductor regions 2 and 3 arranged vertically in the figure, and extends on both semiconductor regions.
  • the semiconductor regions 2-1 and 3-1 and the gate electrode 4-1 form an n-type MOS and a p-type MOS which form the inverter circuit 12 in FIG.
  • the gate electrode serving as the input of the inverter circuit 12 is connected in common with the source areas of Q1 and Q2 forming the selector, and extends in common on both semiconductor areas. Further, a portion corresponding to the drain region in both semiconductor regions is connected in common by the metal wiring 6-1 so that the output OUT can be taken out. This output is wired so that V, which is the input signal of another selector circuit, becomes a control signal as necessary.
  • wiring (V cc, GND) for supplying the power supply voltage V cc and the ground potential GND as the reference potential to the circuit extends above and below the basic circuit forming the cell in the horizontal direction of the drawing.
  • the power supply wiring and the ground wiring 6 are configured to extend along the cell row so that they can be shared by the above-described cell row.
  • the power supply voltage wiring V cc is arranged so as to overlap the p-type semiconductor region 3-1 in a plane so as to supply the power supply voltage and the ground potential to the inverter circuit 12, and the p-type semiconductor region 3 is connected via the contact hole. -Connected to one.
  • the ground potential wiring G-ND is arranged so as to overlap the n-type semiconductor region 2-1 in a plane, and is connected to the n-type semiconductor region 2-1 via a contact hole.
  • these wirings are connected to the semiconductor region 2 or 3.
  • the metal wirings 6 and 61, the power supply voltage wiring Vcc, and the ground potential wiring GND are formed in the same wiring layer.
  • the semiconductor regions 3-1 and 2-1 are spaced apart in the vertical direction in the figure. This is to ensure a contact space between the metal wiring 6 and the gate electrode wiring 4-1 between both regions. Also, the semiconductor regions 3-1 and 3 are H! The semiconductor regions 2-1 and 2 are arranged adjacent to each other in the left-right direction, and the semiconductor regions 3 and 2 have the same spacing as the semiconductor regions 3-1 and 2-1. It is arranged with.
  • the two-input selector portion using Ql and Q2 can be formed with a simple layout similar to a normal CMOS inverter, and an inverter for forming an inverted signal is not required, so that an extremely small area is required. Can be formed.
  • FIG. 4 is a layout diagram of the conventional two-input selector circuit shown in FIG. 5 studied by the inventor using a standard layout method.
  • the same reference numerals as those in FIG. 1 denote the same parts, and a detailed description thereof will be omitted. Comparing FIG. 4 with FIG. 1, it is clear that a two-input selector circuit that realizes the same circuit function can be realized with an area of approximately 1 ⁇ 2.
  • Fig. 6 shows the voltage dependence of the gate delay time (the delay time from the signal input to the output of the two-input selector circuit), with the horizontal axis representing the power supply voltage of the circuit and the vertical axis representing the gate delay. Shows time.
  • Fig. 6 (1) shows the characteristics of the circuit composed of nMOS on the Balta substrate described at the beginning of the conventional example
  • Fig. 6 (2) shows the characteristics of the circuit described on the second example of the conventional example. This shows the characteristics of a circuit formed using NMOS and PMOS
  • FIG. 6-3 shows the characteristics of the circuit according to the present embodiment. As is clear from FIG.
  • the threshold value can be reduced and the junction capacitance can be reduced, so that the gate delay time is about 30% as compared with the conventional example 1. It is possible to increase the speed. Also, in the conventional example 2, the delay time is rapidly increased at a low power supply voltage, and the present invention can also achieve a higher speed.
  • FIG. 7 shows a layout diagram of this embodiment
  • FIG. 8 shows a circuit diagram thereof.
  • FIG. 8 shows a three-input selector circuit in which the two-input selector circuit shown in FIG. 2 is connected in two stages.
  • a description of parts that are the same as in the first embodiment will be omitted, and different parts will be mainly described.
  • FIG. 7 other cells and channel regions are not shown, but can be configured in the same manner as in the first embodiment.
  • the NMOS transistors Q 3 and Q 1 and the PMOS transistors Q 4 and Q 2 are each formed on the S 0 I substrate as shown in FIG. 3 and formed by the method shown in FIG. 3. Is what you can do.
  • Q 3 and Q 4 have one of their source and drain terminals connected in common, and the other of their source and drain terminals receive input signals L and M, and a control signal C 2 is commonly shared by the gate electrodes. It is configured to receive.
  • Q 1 and Q 2 are also configured such that one source / drain terminal is commonly connected and a control signal C 1 is commonly supplied to a gate electrode.
  • the other source / drain terminal of Q1 which is one of the transistors constituting the 2-input selector, is connected to the commonly connected source / drain terminals of Q3 and Q4, and the other of Q2
  • the source ⁇ drain terminal is configured to receive another input signal N.
  • one of the signals input to the input terminals L and M of the source Z drain regions of Q 3 and Q 4 is first selected by the control signal input to the C 2 terminal, and Is output.
  • one of the input to the node e and the input to the N terminal is selected by the control signal input to the C1 terminal, and the inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier.
  • a desired logic circuit can be realized by supplying appropriate signals to the input signal and the control signal.
  • FIG. 7 shows a layout diagram of the circuit shown in FIG. As shown in FIG.
  • semiconductor region 3 is a P-type semiconductor region forming transistor Q2
  • semiconductor region 2 is an N-type semiconductor region forming transistor Q1
  • semiconductor region 3-1 forms inverter 12
  • the P-type semiconductor region and the semiconductor region 2-1 are N-type semiconductor regions that also constitute the inverter 12. This is the same as the layout diagram of the two-input selector circuit shown in FIG. 2.
  • the semiconductor regions 2-2 and Q4 forming the semiconductor regions Q3 and Q4 are formed in the two-input selector circuit.
  • a region 3-2 and 4-2 forming a common gate electrode are added.
  • the semiconductor regions 3-2 and 2-2 are formed continuously to the left of the semiconductor regions 3 and 2, and the gate electrode 4-2 extends in the vertical direction in the drawing, and Q 3 and The source / drain regions of Q4 are commonly connected by metal wiring 6-2, and are also connected to the source / drain regions of Q1.
  • the semiconductor regions 3-1 and 2-1 are arranged without an interval corresponding to the contact space. For this reason, the circuit area constituting the cell 1 is reduced, and the useless space between the semiconductor regions 3 and 2 as in the first embodiment can be eliminated.
  • the semiconductor regions 2 and 3 are connected to the gate electrode wiring 4-1 by connecting the semiconductor regions 2 and 3 with the metal wiring 6, and the metal wiring 6 and the gate electrode 4-1 are different from the metal wiring 6.
  • the three-input selector circuit of the present embodiment can also be configured by an arrangement in which a contact space is provided between the semiconductor regions 3-1 and 2-1 as shown in FIG. In this case, it is not necessary to use the second wiring layer 17 in the cell, so that the degree of freedom when wiring between cell columns is performed in the second layer can be increased.
  • the semiconductor regions 3-2 and 2-2 are arranged adjacent to the semiconductor regions 3 and 2 and on the side opposite to the semiconductor regions 3-1 and 2-1.
  • the semiconductor regions 3-2, 2-2, and 2 can be arranged close to each other, and the metal wiring 6-2 can be connected efficiently over a short distance.
  • FIG. 9 a third embodiment of the present invention is shown in FIG. 9 and FIG.
  • the case where the present invention is applied to the four-input selector circuit shown in FIG. 10 will be described.
  • portions that are the same as those in the first and second embodiments will not be described, and different portions will be mainly described.
  • FIG. 9 other cells and channel regions are omitted, but can be configured in the same manner as in the first embodiment.
  • the selector circuit shown in FIG. 10 includes an NMOS transistor Q3 and a PMOS transistor. It comprises a two-input selector circuit composed of a star Q4, a two-input selector circuit composed of a NMOS transistor Q5 and a PMOS transistor Q6, and a selector circuit for selecting their outputs.
  • the NMOS transistor and the PMOS transistor constituting the selector circuit are each formed on an SOI substrate and can be formed by the process shown in FIG.
  • Transistors Q3 and Q4 have one source / drain terminal connected in common, and the other source / drain terminals are supplied with input signals L and M, respectively.
  • the control signal C2 is commonly connected to each gate electrode.
  • Q3 and Q4 are transistors of different conductivity types, an inverter for inverting the control signal is not required, and the control signal is applied to the gate electrodes of both transistors in common. I have.
  • Transistors Q5 and Q6 have one source / drain terminal connected in common, and the other source / drain terminals are supplied with input signals 0 and P, respectively.
  • a control signal C3 is commonly applied to each gate electrode.
  • Transistors Q 1 and Q 2 also have one source and drain connected in common, but the other source 'drain of Q 1 is connected to the common connection point of Q 3 and Q 4 and the other of Q 2 The source ⁇ drain terminal is connected to the common connection point of Q5 and Q6.
  • the outputs of a two-input selector composed of NMOS, Q5, PMOS, and Q6 are further connected to the inputs of the source / drain regions of Q2 in the second embodiment.
  • One of the signals input to the input terminals 0 and P of the source / drain regions of Q5 and Q6 is first selected by the control signal input to the C3 terminal, and is output to the node f.
  • the input terminals of the source and drain regions of Q3 and Q4 one of the signals input to M is selected by the control signal input to the C2 terminal, and output to the node e .
  • one of the input of the node e and the input of the node ⁇ is selected by the control signal input to the C1 terminal, and an inverted signal is output to the OUT terminal through the inverter 12 of the output amplifier.
  • a desired logic circuit can be realized by supplying appropriate signals to the input signal and the control signal.
  • FIG. 9 shows a layout when the four-input selector circuit of this embodiment is formed on an SOI substrate.
  • FIG. The layout diagram of this embodiment has a form in which a two-input selector is further added to the left side of the layout of the three-input selector circuit in FIG.
  • the semiconductor region 2-3 is an n-type semiconductor region forming an n-type MOSQ5
  • the semiconductor region 3-3 is a p-type semiconductor region forming a p-type MOSQ6
  • 4-3 is a control signal common to Q5 and Q6. This is the gate electrode to be supplied.
  • the semiconductor regions 23 and 3-3 are commonly connected by the metal wiring 6-3, and at the same time, are connected to the semiconductor region 3 forming Q2.
  • a two-input selector is added to the left of the second embodiment, and an inverter for inverting the control signal of C3 is not required.
  • An input selector can be formed.
  • the semiconductor regions 3, 3-2, 3-3 are arranged on a substantially straight line S, and the semiconductor region 3-1 protrudes upward in FIG. .
  • the semiconductor regions 3-1 and 2-1 are vertically separated from each other in the figure, and the metal wiring 6-3 and the power supply are separated. This is to allow a sufficient margin between the wiring Vcc and the margin margin.
  • the circuit area in the vertical direction increases by the amount of the contact space between the metal wiring 6 and the gate electrode 4-1.However, wiring outside the cell must be performed using the metal wiring of the second layer as shown in Fig. 7.
  • a circuit for selecting an arbitrary number of inputs is formed by further adding a two-input selector to the input terminal in the same manner as in the second or third embodiment. It can be formed simply by adding another two-input selector on the left side of this embodiment, and it can be formed extremely simply and with a small area. Can be.
  • FIG. 11 shows a planar structure of a fourth embodiment in which the basic circuit of the present invention is combined
  • FIG. 12 is a circuit diagram thereof.
  • the circuit shown in Fig. 12 realizes the desired logic by adding a two-input selector circuit composed of transistors Q7 and Q8 and an inverter 12 to the input terminal M of the three-input selector circuit shown in Fig. 8. Circuit.
  • a description of parts that are the same as those of the first to third embodiments will be omitted, and different parts will be mainly described.
  • FIG. 11 the illustration of other cells and channel regions is omitted, but the configuration can be the same as in the first embodiment.
  • the inverter circuit (semiconductor area 2) extends in the horizontal direction with respect to the layout of the selector circuit shown in FIG. -4 and 3-4, the gate electrode 4-4) and the selector circuit (semiconductor regions 2-3 and 3-3, the gate electrode 4-3) are added, and the metal wiring (6-3, It can be realized by connecting according to 6-4).
  • a logical combination can be achieved by simply arranging and connecting the basic selector circuit and the inverter circuit in the horizontal direction. Can be realized.
  • FIG. 13 has a configuration in which a latch circuit is provided in the output amplification inverter 12 of the first embodiment shown in FIGS. 1 to 3.
  • description of portions that are the same as in the first to fourth embodiments will be omitted, and different portions will be mainly described.
  • FIG. 13 other cells and channel regions are not shown, but can be configured in the same manner as in the first embodiment.
  • the two-input selector circuit in Fig. 14 connects the input of a latch inverter 14 (consisting of a CMOS transistor) to the output of an inverter 12 for output amplification, and outputs the output to an inverter 1. It is configured to connect to node c which is the input of 2. Also, NMO S? ⁇ ! 03
  • the gate width of the FET is sufficiently smaller than that of the inverter 12 It is configured not to hinder the movement of the inverter 12. It should be noted that a similar effect is obtained even if the gate length of the inverter 14 is increased. However, at the same time, an increase in gate capacitance and the like are caused.
  • the latch inverter 14 when the latch inverter 14 is not provided, there is a possibility that the voltage of the node c becomes lower than the power supply voltage by the threshold value of NMOS, even when the value of the node c is at the high level.
  • the threshold value of NMOS when a high-level signal substantially equal to the power supply voltage is input to the input signal X and a similar high-level signal is applied as the control signal C1, the output voltage is changed from the input signal X to the NM OSFETQ1. The voltage drops by the threshold voltage. Therefore, when the power supply voltage is low, or when such a selector circuit is configured in multiple stages, the driving force of the inverter 12 is weak and the operation tends to be slow.
  • the latching inverter 14 since the latching inverter 14 is formed, the value of the output terminal OUT becomes low level and the output of the inverter 14 becomes high level, and the PMO constituting the inverter 14 becomes The node c is fully charged to the power supply voltage by the SFET and rises to the power supply voltage. Therefore, the voltage loss due to the threshold voltage of the transistor can be compensated by the inverter 14 as in the present embodiment, and the operation of the inverter 12 can be accelerated. Similarly, when a low-level signal is input to the input terminal Y of the PMOSQ 2 and a low-level control signal is also input to the gate electrode, the potential of the node c is similarly grounded by the NMOS transistor of the inverter 14. It can be lowered to the potential. -Next, Fig. 13 shows the layout that realizes this circuit.
  • a latch inverter 14 is formed on the right side of the layout shown in FIG.
  • the inverter 14 includes a semiconductor region 2-5 forming an n-type MOS, a semiconductor region 3-5 forming a p-type MOS, and a gate electrode 4-5 commonly formed by both transistors.
  • the semiconductor regions 2-5 and 3-5 are configured to have a smaller width in the vertical direction in the figure than the other semiconductor regions (for example, 2 and 3) in order to reduce the gate width of both transistors.
  • the metal wiring for supplying the power supply voltage Vcc and the ground power GND is accordingly protruded.
  • the gate electrode 4-5 which is the input of the inverter 14 is the output of the inverter circuit 12 Connected to the metal wiring 6-1.
  • a semiconductor region serving as a drain region of both transistors serving as an output of the inverter 14 is commonly connected by an umbrella wiring 6-4.
  • the connection between the output of the inverter 14 and the common connection point of the transistors Q1 and Q2 is made by the metal wiring 19 via the contacts 18 and 18-5. Since the metal wiring 17 extends in the horizontal direction in the drawing, the second-layer metal wiring which is a wiring layer different from the metal wiring 6-1 etc. so as not to overlap with the metal wiring 6-1 etc. It consists of.
  • a pass transistor logic circuit with a small increase in delay time even at a low voltage can be realized, and can be formed in a small area with an extremely simple layout.
  • an example of a two-input selector circuit is shown.
  • adding a selector circuit to the left in FIG. A selector circuit can be configured.
  • the output amplification inverter circuits 12 are arranged for each of the number of selector circuits (for example, two or three) to compensate for the reduction in drive capability due to the serial connection of the selector circuits. Is provided corresponding to the inverter circuit 12 to compensate for the output of the selector circuit. Therefore, in the other embodiments, the same effect as that of the present embodiment can be obtained by providing the inverter circuit for latching of the present embodiment in addition to the inverter circuit for output amplification.
  • the MIS type semiconductor device uses a transistor formed on a thin-film SOI substrate and uses two transistors of a two-input selector circuit. One of the transistors is set to PMOS, and the control signal input to the gate is made common to the other transistor (NMOS).
  • the underside of the channel regions 16 and 17 of the transistor formed on the so-called thin film SOI is covered with the insulating film 9 and thus connected to any potential. Not in a so-called floating state. Therefore, the body bias effect is extremely small, and the threshold value is almost constant regardless of the source potential. Even if PMOS is used for one transistor of the two-input selector as in the circuit in Fig. 2, the single-level signal input to PMOS is applied to node C. When the output is made, only the threshold when the substrate bias is not applied and the potential corresponding to the value remain.
  • the SOI transistor can lower the threshold voltage without increasing the leakage current by taking advantage of the rapid subthreshold characteristics, so that the voltage remaining at the node c is lower than when a bulk substrate is used. Become smaller. For the above reason, by using PMOS for one transistor of the two-input selector circuit formed on the SOI, the area can be reduced by eliminating the need for an inverter for generating an inverted signal. In addition, power consumption can be reduced as an inverter is not required.
  • an inverter for generating an inverted signal input to the gate of the two-input selector circuit is not required, and the area can be reduced.
  • power consumption can be reduced by eliminating the need for an inverter, and higher speeds can be achieved by taking advantage of the high drive current and low junction capacitance of SOI transistors.
  • the present invention can be widely used for logic circuits formed by semiconductor integrated circuits.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La surface d'une porte logique utilisant un transistor de trajet est fortement réduite, la vitesse de fonctionnement est augmentée et la consommation est abaissée. Il est courant qu'un signal de commande soit envoyé aux portes de deux transistors MIS d'un circuit sélecteur à deux entrées. L'un de ces transistors MIS est un PMOS, l'autre un NMOS, et tous deux sont formés sur un substrat SOI. C'est pourquoi la surface des portes logiques peut être réduite d'une manière remarquable, parce que l'inverseur servant à produire un signal d'inversion pour le circuit sélecteur à deux entrées n'est pas nécessaire. De plus, la consommation des portes peut être réduite de ce qu'aurait consommé l'inverseur et la vitesse de fonctionnement des portes peut être augmentée grâce au fort courant d'attaque et à la faible capacité de jonction des transistors MIS à structure SOI.
PCT/JP1995/001691 1995-08-25 1995-08-25 Dispositif semiconducteur mis WO1997008752A1 (fr)

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PCT/JP1995/001691 WO1997008752A1 (fr) 1995-08-25 1995-08-25 Dispositif semiconducteur mis

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JP2004006725A (ja) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd 半導体装置、その作製方法及び設計方法
JP2006157053A (ja) * 1999-04-12 2006-06-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法、並びに電子機器
US7855380B2 (en) 1999-04-12 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same

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JPS60211869A (ja) * 1984-04-05 1985-10-24 Nec Corp 半導体集積回路装置
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JP2006157053A (ja) * 1999-04-12 2006-06-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法、並びに電子機器
JP4527070B2 (ja) * 1999-04-12 2010-08-18 株式会社半導体エネルギー研究所 半導体装置およびその作製方法、並びに電子機器
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