US20050006733A1 - Lead frame and semiconductor device using the same - Google Patents

Lead frame and semiconductor device using the same Download PDF

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Publication number
US20050006733A1
US20050006733A1 US10/853,148 US85314804A US2005006733A1 US 20050006733 A1 US20050006733 A1 US 20050006733A1 US 85314804 A US85314804 A US 85314804A US 2005006733 A1 US2005006733 A1 US 2005006733A1
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United States
Prior art keywords
die stage
semiconductor chip
cutouts
semiconductor device
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/853,148
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English (en)
Inventor
Kenichi Shirasaka
Hirotaka Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Individual
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Publication date
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Assigned to YAMAHA CORPORATION reassignment YAMAHA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: EGUCHI, HIROTAKA, SHIRASAKA, KENICHI
Publication of US20050006733A1 publication Critical patent/US20050006733A1/en
Priority to US11/938,742 priority Critical patent/US7964942B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J37/00—Baking; Roasting; Grilling; Frying
    • A47J37/06—Roasters; Grills; Sandwich grills
    • A47J37/0694—Broiling racks
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J37/00—Baking; Roasting; Grilling; Frying
    • A47J37/06—Roasters; Grills; Sandwich grills
    • A47J37/067—Horizontally disposed broiling griddles
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    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to lead frames and semiconductor devices in which semiconductor chips mounted on lead frames are encapsulated in resins.
  • FIGS. 19 and 20 show an example of a semiconductor device (designated by reference numeral ‘ 20 ’) encapsulated in a resin, and comprises a lead frame 11 made of a prescribed metal such as Cu alloy and 42 alloy, a semiconductor chip 18 that is joined with the upper surface of a die stage 12 of the lead frame 11 via a joining material 17 such as Ag paste and solder paste, a plurality of bonding wires 16 that electrically connect together electrodes of the semiconductor chip 18 and leads 15 of the lead frame 11 , and a molded resin 19 made of a thermosetting resin such as epoxy resin for enclosing inner leads 15 a of the leads 15 , etc.
  • a thermosetting resin such as epoxy resin for enclosing inner leads 15 a of the leads 15 , etc.
  • the semiconductor device 20 having the aforementioned constitution is temporarily mounted at a prescribed position of a circuit board, which is installed in an electronic device, and is then subjected to reflow soldering in which solder paste is melted and then solidified so that outer leads 15 b of the leads 15 electrically join the circuit board, whereby it is possible to reliably mount the semiconductor device 20 at the prescribed position of the circuit board.
  • Sn-Pb solder (or Sn-Pb alloy) is used for the semiconductor device 20 to be mounted on the circuit board, wherein since a toxic substance such as lead (Pb) contained in the Sn-Pb solder may cause possible destruction of the natural environment and may have bad effects on human bodies, the Sn-Pb solder is recently being replaced with non-lead solder such as Sn-Ag-Cu alloy.
  • the non-lead solder may be advantageous for the protection of the environment because it does not contain toxic substance (or harmful material) such as lead (Pb); however, the melting point thereof (about 217° C.) is higher than that of the Sb-Pn solder (about 183° C.); therefore, it is necessary to increase the heating temperature in reflow soldering, whereby it is necessary to correspondingly increase the heat resistance in soldering with respect to the semiconductor device 20 .
  • toxic substance or harmful material
  • Pb lead
  • Japanese Patent Application Publication No. 2000-49272 discloses another example of a semiconductor device (designated by reference numeral ‘ 30 ’) in which as shown in FIGS. 21 to 23 , a die stage 22 of a lead frame 21 is formed in an X-shape so as to reduce the overall joining area formed between the die stage 22 and a molded resin 29 .
  • Japanese Patent Application Publication No. H07-211852 discloses a further example of a semiconductor device (designated by reference numeral ‘ 40 ’) in which as shown in FIGS. 24 and 25 , an opening 32 a is formed at the center portion of a die stage 32 of a lead frame 31 so as to reduce the overall joining area between the die stage 32 and a molded resin 39 .
  • the aforementioned semiconductor device 30 is designed to reduce the adhered area formed between the die stage 22 and the molded resin 29 so that the separated area appearing in the boundary between them can be reduced, whereby it may be difficult for the separated area to extend towards the boundary between the semiconductor chip and the molded resin, regardless of the impact caused by the separation.
  • the semiconductor device 30 is joined to the circuit board by use of non-lead solder having a high melting point, separation may be easily caused due to heating.
  • the peripheral portion of the die stage 32 extends outside of the peripheral portion of the semiconductor chip 38 , so that separation may occur in such an ‘extended’ peripheral portion to cause impact by which the separated area may be further extended towards the boundary between the semiconductor chip 38 and the molded resin 39 , whereby it may grow as a crack (or cracks) so as to unexpectedly break bonding wires 36 .
  • a lead frame of this invention has a die stage for mounting a semiconductor chip thereon and is enclosed in a molded resin such that the semiconductor chip is adhered to the upper surface of the die stage, thus producing a semiconductor device, wherein the outline of the die stage is shaped to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed on the respective sides of the die stage so as to reduce the overall area of the die stage.
  • the die stage has a rectangular shape (or a square shape), and the cutouts are formed inwardly in the peripheral area corresponding to the four sides of the die stage.
  • each of the cutouts has a semicircular shape whose length L2 is defined in a range from (L1 ⁇ 0.05) to (L1 ⁇ 0.20) where ‘L1’ denotes the length of each side of the die stage.
  • the overall area S2 of the die stage is defined in a range from (S1 ⁇ 0.10) to (S1 ⁇ 0.40) where ‘S1’ denotes the overall area of the semiconductor chip.
  • the joined area between the die stage and the semiconductor chip that are firmly joined together is surrounded by the molded resin introduced into the cutouts of the die stage; therefore, it is possible to establish a firmly joined state between the semiconductor chip and the molded resin inside of the cutouts of the die stage.
  • the aforementioned relationships defined between L1 and L2 and between S1 and S2 guarantee a high joining strength between the die stage and the semiconductor chip so as to prevent separation from occurring in the boundary between the semiconductor chip and the molded resin.
  • the aforementioned lead frame is joined with a circuit board by use of non-lead solder, which does not contain a toxic substance, thus contributing to the protection of the environment during manufacturing.
  • FIG. 1 is a cross sectional view showing the constitution of a semiconductor device having a lead frame in accordance with a first embodiment of the invention
  • FIG. 2 is an illustration diagrammatically showing the lead frame having a die stage of a prescribed shape, which is observed from the backside;
  • FIG. 3 is an illustration diagrammatically showing applied areas of a joining material on the die stage shown in FIG. 2 ;
  • FIG. 4 is a graph showing variations of S2/S1 ratio between the backside area (S2) of a die stage and the backside area (S1) of a semiconductor chip having 4 mm X 4 mm dimensions;
  • FIG. 5 is a graph showing variations of adhesive force established between the die stage and the semiconductor chip having 4 mm ⁇ 4 mm dimensions
  • FIG. 6 is a graph showing variations of the S2/S1 ratio between the backside area (S2) of a die stage and the backside area (S1) of a semiconductor chip having 7 mm ⁇ 7 mm dimensions;
  • FIG. 7 is a graph showing variations of the adhesive force established between the die stage and the semiconductor chip having 7 mm ⁇ 7 mm dimensions
  • FIG. 8 is a graph showing variations of the S2/S1 ratio between the backside area (S2) of a die stage and the backside area (S1) of a semiconductor chip having 10 mm ⁇ 10 mm dimensions;
  • FIG. 9 is a graph showing variations of the adhesive force established between the die stage and the semiconductor chip having 10 mm ⁇ 10 mm dimensions
  • FIG. 10 is a graph showing variations of the S2/S1 ratio between the backside area (S2) of a die stage and the backside area (S1) of a semiconductor chip having 12 mm ⁇ 12 mm dimensions;
  • FIG. 11 is a graph showing variations of the adhesive force established between the die stage and the semiconductor chip having 12 mm ⁇ 12 mm dimensions
  • FIG. 12A is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a second embodiment of the invention.
  • FIG. 12B is a cross sectional view taken along line A-A in FIG. 12A ;
  • FIG. 13A is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a third embodiment of the invention.
  • FIG. 13B is a cross sectional view take along line B-B in FIG. 13A ;
  • FIG. 14 is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a fourth embodiment of the invention.
  • FIG. 15A is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a fifth embodiment of the invention.
  • FIG. 15B is a cross sectional view taken along line C-C in FIG. 15A ;
  • FIG. 16A is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a sixth embodiment of the invention;
  • FIG. 16B is a cross sectional view taken along line D-D in FIG. 16A ;
  • FIG. 17 is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with a seventh embodiment of the invention.
  • FIG. 18A is a backside view diagrammatically showing a semiconductor chip and a die stage of a lead frame in accordance with an eighth embodiment of the invention.
  • FIG. 18B is a cross sectional view taken along line E-E in FIG. 18A ;
  • FIG. 19 is a cross sectional view showing the constitution of a conventionally-known semiconductor device.
  • FIG. 20 is a plan view simply showing the relationship between a semiconductor chip and a die stage in the semiconductor device shown in FIG. 19 ;
  • FIG. 21 is a plan view diagrammatically showing an example of the lead frame
  • FIG. 22 is a plan view diagrammatically showing a semiconductor chip that is mounted on the lead frame shown in FIG. 21 ;
  • FIG. 23 is a cross sectional view showing the constitution of a conventionally-known semiconductor device having the lead frame shown in FIG. 21 ;
  • FIG. 24 is a plan view diagrammatically showing an example of the lead frame
  • FIG. 25 is a perspective view showing the appearance of a conventionally-known semiconductor device having the lead frame shown in FIG. 24 ;
  • FIG. 26 shows a comparison between samples with respect to their dimensions and adhesive forces
  • FIG. 27 shows a comparison between samples with respect to their defects.
  • FIGS. 1 to 3 show a lead frame 1 and a semiconductor device 10 in accordance with a first embodiment of the invention.
  • the lead frame 1 is produced using a thin plate made of a prescribed metal such as Cu alloy and 42 alloy, which is subjected to etching and is then subjected to die pressing, so that it is formed in a prescribed shape.
  • the lead frame 1 comprises a die stage 2 in which a semiconductor chip 8 is mounted on the upper surface, a plurality of stays 4 for supporting the die stage 2 , and a plurality of leads 5 that are arranged outside of the die stage 2 and are electrically connected with electrodes of the semiconductor chip 8 .
  • the die stage 2 is formed in a prescribed shape to match the shape of the semiconductor chip 8 .
  • the die stage 2 as a whole is roughly formed in a rectangular shape to match the rectangular shape of the semiconductor chip 8 as shown in FIGS. 2 and 3 .
  • the overall area of the die stage 2 is reduced so as to be smaller than that of the semiconductor chip 8 (i.e., the backside area of the semiconductor chip 8 mounted on the die stage 2 ), wherein the outline shape of the die stage 2 is formed so as to be completely encompassed inside of the outline shape of the semiconductor chip 8 .
  • the peripheral portion of the semiconductor chip 8 having the prescribed area extends outside of the peripheral portion of the die stage 2 .
  • Semicircular cutouts 3 are respectively formed at the centers of the four sides of the die stage 2 , which is thus reduced in the overall area. Therefore, when the semiconductor chip 8 is mounted on the upper surface of the die stage 2 , prescribed parts of the backside of the semiconductor chip 8 matching the semicircular cutouts 3 of the die stage 2 are exposed towards the backside of the semiconductor chip 8 .
  • each of the semicircular cutouts 3 is cut inside of the die stage 2 by a prescribed length L2, which is set within a range defined by the following equation (1) (where L1 denotes the length of each side of the die stage 2 ).
  • L2 (L1 ⁇ 0.05) to (L1 ⁇ 0.20) (1)
  • the stays 4 are formed integrally together with the die stage 2 and are arranged in a radial manner with respect to the four corners of the die stage 2 , whereby the die stage 2 is reliably supported by the stays 4 .
  • each of the leads 5 is constituted by an inner lead 5 a , which is arranged inside of the semiconductor device 10 , and an outer lead 5 b , which is arranged outside of the semiconductor device 10 .
  • the inner leads 5 a of the leads 5 are electrically connected with electrodes of the semiconductor chip 8 via bonding wires 6
  • the outer leads 5 b are electrically joined with a circuit board (not shown) installed in an electronic device (not shown) via solder.
  • a die bonding step is firstly performed in such a way that an appropriate amount of a joining material 7 such as Ag paste and non-lead solder (e.g., Sn-Ag-Cu alloy) is applied onto the upper surface of the die stage 2 of the lead frame 1 , wherein the semiconductor chip 8 is mounted on the upper surface of the die stage 2 and pressed by a prescribed load while the joining material 7 is melted and then solidified, so that the semiconductor chip 8 is integrally joined on the upper surface of the die stage 2 .
  • a joining material 7 such as Ag paste and non-lead solder (e.g., Sn-Ag-Cu alloy)
  • the Ag paste and the like is applied to the upper surface of the die stage 2 at prescribed areas 7 A (encompassed by dotted circles in FIG. 3 ), which are located so as to avoid the cutouts 3 . Therefore, the cutouts 3 of the die stage 2 do not interfere with the application of the joining material 7 .
  • the electrodes of the semiconductor chip 8 are electrically connected with the inner leads 5 a of the leads 5 by way of the bonding wires 6 such as metal wires.
  • the lead frame 1 is placed in a cavity of a metal mold consisting of an upper mold and a lower mold, which is then filled with a thermosetting resin such as epoxy resin, which is injected into the cavity and is then hardened.
  • a thermosetting resin such as epoxy resin
  • the molded resin 9 flows into the cutouts 3 of the die stage 2 to join the backside of the semiconductor chip 8 , so that the molded resin 9 is partially formed inside of the cutouts 3 of the die stage 2 .
  • non-lead solder plating is performed on prescribed portions of the leads 5 , which project outside of the molded resin 9 , as necessary, so that rust is prevented from occurring on the leads 5 . This makes it easy to perform soldering work when the semiconductor device 10 is mounted on the circuit board.
  • the semiconductor device 10 by way of the aforementioned steps. Then, the semiconductor device 10 having the aforementioned constitution is temporarily mounted on the circuit board at the prescribed position, wherein non-lead solder is subjected to melting and solidification upon reflow soldering, and the outer leads 5 b of the leads 5 are electrically joined with the circuit board. Thus, it is possible to firmly mount the semiconductor device 10 on the circuit board at the prescribed position.
  • the semiconductor device 10 having the aforementioned lead frame 1 even when the semiconductor device 10 is heated upon reflow soldering so that separation may occur between the die stage 2 and the molded resin 9 , it is possible to avoid the occurrence of separation between the semiconductor chip 8 and the molded resin 9 as well as the occurrence of breaks of the bonding wires 6 .
  • the present embodiment is characterized in that the outline of the die stage 2 is shaped to be smaller than the outline of the semiconductor chip 8 so that the overall area of the die stage 2 is reduced so as to be smaller than that of the semiconductor chip 8 , whereby when the semiconductor chip 8 is mounted on the upper surface of the die stage 2 , the peripheral portion of the semiconductor chip 8 partially extends outside of the peripheral portion of the die stage 2 .
  • the separated area which may be easily formed in the peripheral portion of the die stage 2 when the semiconductor device 10 is mounted on the circuit board upon heating.
  • the semiconductor chip 8 is soldered to the die stage 2 ; hence, they can be firmly joined together. That is, the adhered areas formed between the semiconductor chip 8 and the molded resin 9 inside of the cutouts 3 of the die stage 2 are encompassed by the firmly joined areas between the die stage 2 and the semiconductor chip 8 ; hence, it is possible to establish a firmly adhered state between the semiconductor chip 8 and the molded resin 9 inside of the cutouts 3 of the die stage 2 .
  • the molded resin 9 itself can be engaged inside of the cutouts 3 of the die stage 2 ; hence, it is very difficult for both of the molded resin 9 and the die stage 2 to mutually move from each other in prescribed directions matching the four sides of the die stage 2 . Therefore, even though separation occurs between the die stage 2 and the molded resin 9 , it does not extend towards the boundary between the semiconductor chip 8 and the molded resin 9 , and it does not grow as cracks to unexpectedly break the bonding wires 6 .
  • the present embodiment introduces the relationship between the length L1 of each side of the rectangularly-shaped die stage 2 , and the length L2, by which each cutout 3 is formed inwardly into each side of the die stage 2 , as defined in the aforementioned equation (1), whereby it is possible to increase the joining strength so as to be higher with respect to the die stage 2 .
  • the present embodiment introduces the relationship between the backside area S1 of the semiconductor chip 8 and the backside area S2 of the die stage 2 as defined in the aforementioned equation (2), whereby it is possible to increase the joining strength so as to be higher with respect to the die stage 2 .
  • the length L2 of each semicircular cutout is set to (L1 ⁇ 0.20).
  • the graph of FIG. 4 shows a comparison between the aforementioned example of the semiconductor device, in which cutouts are formed on the respective sides of the die stage, and a comparative example of the semiconductor device, in which no cutout is formed in the die stage, in terms of the aforementioned parameter of S2/S1.
  • a so-called adhesive force (or adhesive factor) is introduced to assess the adhesive property of the semiconductor device, wherein the adhesive force established between the semiconductor chip and the molded resin is normally set to 1.00, while the adhesive force established between the die stage and the molded resin is decreased to 0.50 when adhesion is weakened.
  • the adhesive force can be described as follows:
  • FIG. 26 shows a comparison between “Sample A”, in which the semiconductor chip has a square shape whose one side length is set to 9.9 mm and the die stage has a square shape whose one side length is set to 9 mm, and “Sample B” in which the semiconductor chip has the same dimensions described above while the die stage has a square shape whose one side length is set to 4.2 mm, wherein both of Samples A and B do not provide cutouts in the die stages thereof.
  • the occurrence of separation may greatly depend upon the adhesive force of the molded resin; hence, when the adhesive force between the semiconductor chip and the molded resin is 1.00, it is assumed that the adhesive force between the die stage and the molded resin is 0.50. For this reason, it is presumed that the semiconductor chip joins the molded resin with an adhesive force of 1.00 in relation to the area (S1-S2), in which the backside area S2 of the die stage is subtracted from the backside area S1 of the semiconductor chip, while the die stage joins the molded resin with an adhesive force of 0.50 in relation to the backside area S2 of the die stage. Therefore, the prescribed adhesive forces as shown in the rightmost column of FIG. 26 can be defined with respect to Samples A and B respectively. Such definitions for adhesive forces can be used for the assessment of semiconductor devices.
  • the semiconductor chip 8 joins the molded resin 9 at an adhesive force of 1.00 in relation to the ‘exposed’ backside area of the semiconductor chip 8 , i.e., the aforementioned area (S1-S2), in which the backside area S2 of the die stage 2 excluding the cutouts 3 is subtracted from the backside area S1 of the semiconductor chip 8 , while the die stage 2 joins the molded resin 9 at an adhesive force of 0.50 in relation to the backside area S2 of the die stage 2 .
  • the adhesive force be 0.80 or more.
  • the range guaranteeing an adhesive force of 0.80 or more can be converted to the range of the aforementioned ratio S2/S1, which is about 40% or less.
  • the ratio S2/S1 be approximately 10% or more. That is, it is preferable that the ratio S2/S1 range from 10% to 40%, based on which the aforementioned equation (2) can be estimated.
  • a semiconductor chip having a square shape whose one side length is set to 4 mm is joined together with a die stage having a square shape whose one side length is set to 2 mm in which cutouts are formed on respective sides, wherein they are integrally enclosed in a molded resin so as to produce a semiconductor device, which is now placed under assessment as follows:
  • the semiconductor device is subjected to baking at a temperature of 125° C. for 24 hours, humidification of 30% at 85° C. for 168 hours, humifification of 70% at 30° C. for 120 hours, and heating during reflow soldering at a peak temperature of 265° C. for 10 seconds 2 times. In this case, no separation is found with respect to the die stage; thus, very good results can be obtained.
  • FIGS. 6, 8 , and 10 show variations of the aforementioned ratio S2/S1 in relation to variations of one side length of the die stage with respect to three types of square-shaped semiconductor chips having 7 mmX 7 mm dimensions, 10 mm X 10 mm dimensions, and 12 mm ⁇ 12 mm dimensions, respectively.
  • FIGS. 7, 9 , and 11 show variations of the adhesive force with respect to the three types of the square-shaped semiconductor chips, respectively.
  • FIGS. 12A and 12B show the lead frame 1 and the semiconductor device 10 in accordance with the second embodiment of the invention, wherein in addition to the foregoing cutouts 3 that are formed at the centers of the respective sides of the die stage 2 , secondary cutouts 3 A are formed so as to encompass the cutouts 3 inwardly of the die stage 2 whose backside is subjected to half etching.
  • Each of the secondary cutouts 3 A is opened with respect to the cutouts 3 and the backside of the die stage 2 , wherein in the foregoing molding step, the molded resin 9 flows into the secondary cutouts 3 A in addition to the cutouts 3 of the die stage 2 .
  • the second embodiment can offer the same effects as demonstrated by the first embodiment.
  • the overall adhered area is reduced in the same plane formed between the backside of the die stage 2 and the molded resin 9 so that the stress therein is dispersed; hence, it is possible to make it difficult for separation to occur between the die stage 2 and the molded resin 9 .
  • Such an effect can be obtained by making the backside of the die stage 2 roughly by use of a sand blaster and the like.
  • FIGS. 13A and 13B show the lead frame 1 and the semiconductor device 10 in accordance with the third embodiment of the invention, wherein the secondary cutouts 3 A are formed by performing half etching on the upper surface of the die stage 2 so as to encompass the semicircular cutouts 3 , which are formed at the centers of the respective sides of the die stage 2 .
  • the secondary cutouts 3 A are opened in the cutouts 3 on the upper surface of the die stage 2 , wherein in the foregoing molding step, the molded resin 9 is introduced into the secondary cutouts 3 A in addition to the cutouts 3 , so that the molded resin 9 partially formed inside of the secondary cutouts 3 is joined to the backside of the semiconductor chip 8 .
  • the third embodiment can demonstrate the same effects as offered in the first embodiment, wherein due to the formation of the secondary cutouts 3 A, it is possible to increase the overall contact area between the semiconductor chip 8 and the molded resin 9 .
  • the secondary cutouts 3 A are formed in the side of the upper surface of the die stage 2 ; hence, in the foregoing wire bonding step, it is possible to maintain the stable condition secured for the die stage 2 , which serves as the base for mounting the semiconductor chip 8 .
  • FIG. 14 shows the lead frame 1 and the semiconductor device 10 in accordance with the fourth embodiment of the invention, wherein the die stage 2 is provided with through holes 3 B, which penetrate through the corner portions of the die stage 2 , in addition to the semicircular cutouts 3 .
  • Each of the through holes 3 B is opened on both of the upper surface and backside of the die stage 2 , wherein in the foregoing molding step, the molded resin 9 is introduced into the insides of the through holes 3 B in addition to the cutouts 3 , so that the molded resin 9 partially formed inside of the through holes 3 B is joined with the backside of the semiconductor chip 8 .
  • the fourth embodiment can demonstrate the same effects as offered in the first embodiment, wherein it is possible to further increase the overall contact area formed between the semiconductor chip 8 and the molded resin 9 .
  • the through holes 3 B do not interfere with the respective sides of the die stage 2 , which form the peripheral portion of the die stage 2 ; hence, in the foregoing wire bonding step, it is possible to maintain the stable condition secured for the die stage 2 , which serves as the base for mounting the semiconductor chip 8 .
  • the fourth embodiment can be modified in such a way that the upper surface or backside of the die stage 2 is subjected to half etching at prescribed areas encompassing the through holes 3 B.
  • FIGS. 15A and 15B show the lead frame 1 and the semiconductor device 10 in accordance with the fifth embodiment of the invention, wherein third cutouts 3 C are formed by performing half etching on the backside of the die stage so as to provide communication between the ‘opposing’ cutouts 3 , which are formed at the centers of the respective sides of the die stage 2 .
  • the third cutouts 3 C are opened between the cutouts 3 in the backside of the die stage 2 , wherein in the foregoing molding step, the molded resin 9 is introduced into the third cutouts 3 C in addition to the cutouts 3 .
  • the fifth embodiment can demonstrate the same effects as offered in the first embodiment, and it can also demonstrate the same effects as offered in the second embodiment.
  • FIGS. 16A and 16B show the lead frame 1 and the semiconductor device 10 in accordance with the sixth embodiment of the invention, wherein the third cutouts 3 C are formed by performing half etching on the upper surface of the die stage 2 so as to provide communication between the ‘opposing’ cutouts 3 , which are formed at the centers of the respective sides of the die stage 2 .
  • the third cutouts 3 C are opened between the cutouts 3 in the upper surface of the die stage 2 , wherein in the foregoing molding step, the molded resin 9 is introduced into the third cutouts 3 C in addition to the cutouts 3 , so that the molded resin 9 partially formed in the third cutouts 3 C is joined with the backside of the semiconductor chip 8 .
  • the sixth embodiment can demonstrate the same effects as offered in the first embodiment, and it can also demonstrate the same effects as offered in the third embodiment.
  • FIG. 17 shows the lead frame 1 and the semiconductor device 10 in accordance with the seventh embodiment of the invention, wherein a plurality of semicircular cutouts 3 are formed on each of the four sides of the die stage 2 , so that it is possible to demonstrate the same effects as offered in the first embodiment.
  • FIGS. 18A and 18B show the lead frame 1 and the semiconductor device 10 in accordance with the eighth embodiment of the invention, wherein a plurality of semicircular cutouts 3 are formed on each of the four sides of the die stage 2 , and fourth cutouts 3 D are formed by performing half etching on the upper surface of the peripheral portion of the die stage 2 including the cutouts 3 .
  • the fourth cutouts 3 D are opened between the cutouts 3 in the upper surface of the die stage 2 at its corners, wherein in the foregoing molding step, the molded resin 9 is introduced into the fourth cutouts 3 D in addition to the cutouts 3 , so that the molded resin 9 partially formed in the fourth cutouts 3 D is joined with the backside of the semiconductor chip 8 .
  • the eighth embodiment can demonstrate the same effects as offered in the first embodiment, and it can also demonstrate the same effects as offered in the third embodiment.
  • the cutouts 3 of the die stage 2 are not necessarily limited to a semicircular shape, and can be changed to a triangular shape or rectangular shape, for example.
  • a semiconductor device including a lead frame according to this invention is designed such that the outline of a die stage is shaped to be smaller than the outline of a semiconductor chip, whereby it is possible to minimize the separated area that may be formed in the boundary between the die stage and molded resin due to heating when the semiconductor device is soldered to the circuit board. This can prevent the separated area formed in proximity to the die stage from extending to the boundary between the semiconductor chip and molded resin; hence, it is possible to prevent bonding wires from being unexpectedly broken due to the formation of cracks caused by the growth of the separation.
  • a plurality of cutouts are adequately formed in the peripheral portion of the die stage so that the molded resin formed inside of the cutouts can be firmly joined with the backside of the semiconductor chip. Therefore, even when separation occurs in the boundary between the die stage and molded resin, it does not extend towards the boundary between the semiconductor chip and molded resin; hence, it is possible to prevent the bonding wires from being unexpectedly broken due to the formation of cracks caused by the growth of the separation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Food Science & Technology (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US10/853,148 2003-05-28 2004-05-26 Lead frame and semiconductor device using the same Abandoned US20050006733A1 (en)

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JP2006351755A (ja) * 2005-06-15 2006-12-28 Renesas Technology Corp 半導体装置
JP5173654B2 (ja) * 2007-08-06 2013-04-03 セイコーインスツル株式会社 半導体装置
JP5797126B2 (ja) * 2012-02-06 2015-10-21 三菱電機株式会社 半導体装置
JP5954013B2 (ja) * 2012-07-18 2016-07-20 日亜化学工業株式会社 半導体素子実装部材及び半導体装置
CN108585799B (zh) * 2018-05-11 2021-05-11 广东工业大学 一种新型陶瓷3d打印成型方法
CN113169150B (zh) * 2021-03-10 2022-06-14 英诺赛科(苏州)半导体有限公司 Iii族氮基半导体封装结构及其制造方法
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CN2733595Y (zh) 2005-10-12
CN100385658C (zh) 2008-04-30
TW200504986A (en) 2005-02-01
US20080073764A1 (en) 2008-03-27
TWI265619B (en) 2006-11-01
JP2005012184A (ja) 2005-01-13
CN1574330A (zh) 2005-02-02
US7964942B2 (en) 2011-06-21
HK1069675A1 (en) 2005-05-27
KR100582613B1 (ko) 2006-05-23
KR20040103778A (ko) 2004-12-09

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