TWM627595U

TWM627595U - Voltage level conversion circuit exhibiting reduced power consumption

Info

Publication number: TWM627595U
Application number: TW110213179U
Authority: TW
Inventors: 余建政; 邱崑霖; 賴永瑄
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2021-11-09
Filing date: 2021-11-09
Publication date: 2022-06-01

Abstract

本創作提出一種降低功耗之電位轉換電路，其係由一栓鎖電路(1)、一輸出控制電路(2)以及一輸入電路(3)所組成，其中，該栓鎖電路(1)係用來保存差動輸入信號；該輸出控制電路(2)係用來控制該電位轉換電路的輸出信號之電位；而該輸入電路(3)係用來提供該電位轉換電路的差動輸入信號。 The present invention proposes a potential conversion circuit for reducing power consumption, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), wherein the latch circuit (1) is a used to store the differential input signal; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the differential input signal of the potential conversion circuit.

本創作所提出之降低功耗之電位轉換電路，不但能精確地將第一信號轉換為一第二信號，同時亦能有效地減少漏電流，進而降低功率消耗。 The potential conversion circuit for reducing power consumption proposed in this work can not only accurately convert the first signal into a second signal, but also effectively reduce leakage current, thereby reducing power consumption.

Description

降低功耗之電位轉換電路 Potential conversion circuit for reducing power consumption

本創作係有關一種降低功耗之電位轉換電路，尤指利用一栓鎖電路(1)、一輸出控制電路(2)以及一輸入電路(3)所組成，以求獲得精確電壓位準轉換且有效降低功率消耗之電子電路。 The present invention relates to a potential conversion circuit for reducing power consumption, especially composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), in order to obtain precise voltage level conversion and Electronic circuits that effectively reduce power consumption.

電位轉換電路係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換電路就負責將低電壓工作信號轉換成高電壓工作信號。 A potential conversion circuit is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential conversion circuit is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

第1圖係顯示一先前技藝(prior art)之一閂鎖型電位轉換電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換電路的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換電路中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 FIG. 1 shows a prior art latch-type potential conversion circuit, which uses a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1), a A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) ) to form a potential conversion circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the first signal (V(IN)) is also at the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, in the same During the time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential conversion circuit is in a stable state, the latch type There is no static current generated in the potential conversion circuit. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換電路在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成邏輯低位準時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為邏輯低位準，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional potential conversion circuit, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the output terminal The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention with each other, so the second signal (V(OUT)) is slower when it transitions to a logic low level. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a logic low level, The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS electrical The crystal ( MN1 ) and the second NMOS transistor ( MN2 ) are completely turned on or turned off, which will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND). Current increases power loss.

再者，閂鎖型的電位轉換電路的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換電路正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type potential conversion circuit is affected by the first high potential voltage (VDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type potential conversion circuit can operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電位轉換電路，該電位轉換電路藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換電路的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電位轉換電路的性能也不會有太大的改變。因此，鏡像型的電位轉換電路可以適用在各種輸出電壓電路。 FIG. 2 shows another prior art mirror-type potential conversion circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and to The drain of the first PMOS transistor (MP1) makes the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in the saturation region, and its The gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential conversion circuit is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the potential conversion The performance of the circuit will not change much either. Therefore, the mirror-type potential conversion circuit can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a voltage is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1). a quiescent current path.

有鑑於此，本創作之主要目的係提出一種降低功耗之電位轉換電路，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少漏電流，進而降低功率消耗。 In view of this, the main purpose of this creation is to provide a potential conversion circuit with reduced power consumption, which can not only accurately and quickly convert a first signal into a second signal, but also can effectively reduce leakage current, thereby reducing power consumption. .

由模擬結果證實，本創作所提出之降低功耗之電位轉換電路，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has the advantages of simple circuit structure and the advantages of miniaturization of the device. efficiency, while also effectively reducing power loss.

1:栓鎖電路 1: Latch circuit

2:輸出控制電路 2: Output control circuit

3:輸入電路 3: Input circuit

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

I1:第一反相器 I1: first inverter

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: the third NMOS transistor

MN4:第四NMOS電晶體 MN4: Fourth NMOS transistor

MN5:第五NMOS電晶體 MN5: Fifth NMOS transistor

MN6:第六NMOS電晶體 MN6: sixth NMOS transistor

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): Second signal

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

第1圖係顯示第一先前技藝中電位轉換電路之電路圖；第2圖係顯示第二先前技藝中電位轉換電路之電路圖；第3圖係顯示本創作較佳實施例之降低功耗之電位轉換電路之電路圖；第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖。 Figure 1 shows the circuit diagram of the potential conversion circuit in the first prior art; Figure 2 shows the circuit diagram of the potential conversion circuit in the second prior art; Figure 3 shows the potential conversion for reducing power consumption according to the preferred embodiment of the present invention Circuit diagram of the circuit; FIG. 4 is a timing diagram of transient analysis of the first signal and the second signal in the preferred embodiment of the present invention.

根據上述之目的，本創作提出一種降低功耗之電位轉換電路，如第3圖所示，其係由一栓鎖電路(1)、一輸出控制電路(2)以及一輸入電路(3)所組成，其中，該栓鎖電路(1)係用來保存差動輸入信號；該輸出控制電路(2)係用來控制該電位轉換電路的輸出信號之電位；而該輸入電路(3)係用來提供該電位轉換電路的差動輸入信號；該栓鎖電路(1)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)、一第五NMOS電晶體(MN5)以及一第六NMOS電晶體(MN6)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第一NMOS電晶體(MN1)的源極連接至該第三NMOS電晶體(MN3)的汲極，其閘極連接至該第四節點(N4)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至該第四NMOS電晶體(MN4)的汲極，其閘極連接至該第三節點(N3)，而其汲極則與該第四節點(N4)相連接；該第五NMOS電晶體(MN5)的源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；該第六NMOS電晶體(MN6)的源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接；該輸出控制電路(2)係由一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該輸入電路(3)係由一第三NMOS電晶體(MN3)、一第四NMOS電晶體(MN4)以及一第一反相器(I1)所組成，其中，該第三NMOS電晶體(MN3)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一NMOS電晶體(MN1)的源極相連接；該第四NMOS電晶體(MN4)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二NMOS電晶體(MN2)的源極相連接；該第一反相器(I1)耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該第一高電源供應電壓(VDDH)係用以提供該電位轉換電路所需之第一高電位電壓；而該第二高電源供應電壓(VDDL)係用以提供該電位轉換電路所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特；該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes a potential conversion circuit for reducing power consumption, as shown in FIG. 3, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3). composition, wherein, the latch circuit (1) is used to store the differential input signal; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used for to provide the differential input signal of the potential conversion circuit; the latch circuit (1) consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , a first NMOS transistor (MN1), a second NMOS transistor (MN2), a fifth NMOS transistor (MN5) and a sixth NMOS transistor (MN6), wherein the first PMOS transistor The source of the crystal (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the A second PMOS transistor (MP2) has its source connected to the first high power supply voltage (VDDH), its gate connected to the third node (N3), and its drain connected to the second node (N2) ) is connected; the source of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), its gate is connected to the fourth node (N4), and its drain is connected to The third node (N3) is connected; the source of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4), and the gate is connected to the third node (N3), The drain electrode is connected to the fourth node (N4); the source electrode of the fifth NMOS transistor (MN5) is connected to the third node (N3), and the gate electrode is connected to the second input end (INB). ), and its drain is connected to the first node (N1); the source of the sixth NMOS transistor (MN6) is connected to the fourth node (N4), and its gate is connected to the first input terminal (IN), and its drain is the same as the second section point (N2) is connected; the output control circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the third PMOS transistor (MP3) The source is connected to the first high power supply voltage (VDDH), the gate is connected to the first input terminal (IN), and the drain is connected to the first node (N1); the fourth PMOS power The source of the crystal (MP4) is connected to the first high power supply voltage (VDDH), the gate is connected to the second input terminal (INB), and the drain is connected to the second node (N2); The input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the third NMOS transistor (MN3) ) is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); the fourth NMOS The source electrode of the transistor (MN4) is connected to the ground (GND), the gate electrode is connected to the second input terminal (INB), and the drain electrode is connected to the source electrode of the second NMOS transistor (MN2); The first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing an inverse of the first signal (V(IN)). phase signal; the first high power supply voltage (VDDH) is used to provide the first high potential voltage required by the potential conversion circuit; and the second high power supply voltage (VDDL) is used to provide the potential conversion circuit The required second high potential voltage, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) is 1.8 volts, The second high power supply voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is Corresponding waveforms between 0 volts and 1.8 volts.

請再參閱第3圖，說明圖3之工作原理如下：現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，電位轉換電路的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第三NMOS電晶體(MN3)、該第六NMOS電晶體(MN6)以及該第三PMOS電晶體(MP3)的閘極，使得該第三NMOS電晶體(MN3)和該第六NMOS電晶體(MN6)都關閉(OFF)，而該第三PMOS電晶體(MP3)導通(ON)，此時該第一節點(N1)的電位被拉升至一接近第一高電位電壓(VDDH)之高電位；而該第一反相器(I1)傳送第二高電位電壓(VDDL)到該第四NMOS電晶體(MN4)、該第五NMOS電晶體(MN5)以及該第四PMOS電晶體(MP4)的閘極，使得該第四NMOS電晶體(MN4)和該第五NMOS電晶體(MN5)都導通(ON)，而該第四PMOS電晶體(MP4)關閉(OFF)，此時，由於該第三PMOS電晶體(MP3)和該第五NMOS電晶體(MN5)都導通(ON)，因此，該第三節點(N3)的電位會被拉升至一高電位，而該第三節點(N3)的高電位使得該第二PMOS電晶體(MP2)關閉、該第二NMOS電晶體(MN2)導通，此時，由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通，因此，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，再者，該第四節點(N4)的低電位傳送到該第一PMOS電晶體(MP1)和該第一NMOS電晶體(MN1)的閘極，使得該第一NMOS電晶體(MN1)關閉、該第一PMOS電晶體(MP1)導通，此時由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通，而該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都關閉，因此，該第四節點(N4)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過電位轉換電路轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to FIG. 3 again to explain the working principle of FIG. 3 as follows: Now consider the steady-state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic low level (0 volts): the first input terminal ( The logic low level on IN) is simultaneously transmitted to the input of the first inverter (I1), the third NMOS transistor (MN3), the sixth NMOS transistor (MN6) and the third PMOS transistor ( MP3) gate, so that both the third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are turned off (OFF), and the third PMOS transistor (MP3) is turned on (ON), at this time the The potential of the first node (N1) is pulled up to a high potential close to the first high potential voltage (VDDH); and the first inverter (I1) transmits the second high potential voltage (VDDL) to the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the gates of the fourth PMOS transistor (MP4) so that both the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are is turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). At this time, since the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are both turned on (ON), therefore , the potential of the third node (N3) will be pulled to a high potential, and the high potential of the third node (N3) will turn off the second PMOS transistor (MP2), the second NMOS transistor (MN2) ) is turned on, at this time, since both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are turned on, the potential of the fourth node (N4) will be pulled down to a logic low level ( 0 volts), and further, the low potential of the fourth node (N4) is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first NMOS transistor ( MN1) is turned off and the first PMOS transistor (MP1) is turned on. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off, therefore, the potential of the fourth node (N4) maintains a steady state value at a logic low level (0 volt). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a logic low level through a potential conversion circuit. The second signal of level (0 volt) is output from the output terminal (OUT).

再考慮第一信號(V(IN))為邏輯高位準(1.2伏特)時，電位轉換電路的穩態操作情形：第一輸入端(IN)上的邏輯高位準同時傳送到該第一反相器(I1)的輸入端、該第三NMOS電晶體(MN3)、該第六NMOS電晶體(MN6)以及該第三PMOS電晶體(MP3)的閘極，使得該第三NMOS電晶體(MN3)和該第六NMOS電晶體(MN6)都導通(ON)，而該第三PMOS電晶體(MP3)關閉(OFF)；而該第一反相器(I1)傳送一低位準(0伏特)到該第四NMOS電晶體(MN4)、該第五NMOS電晶體(MN5)以及該第四PMOS電晶體(MP4)的閘極，使得該第四NMOS電晶體(MN4)和該第五NMOS電晶體(MN5)都關閉(OFF)，而該第四PMOS電晶體(MP4)導通(ON)，此時，由於該第四PMOS電晶體(MP4)和該第六NMOS電晶體(MN6)都導通(ON)，而該第四NMOS電晶體(MN4)關閉(OFF)，因此，該第四節點(N4)的電位會被拉升至一邏輯高位準，再者，該第四節點(N4)的高電位傳送到該第一PMOS電晶體(MP1)和該第一NMOS電晶體(MN1)的閘極，使得該第一PMOS電晶體(MP1)關閉、該第一NMOS電晶體(MN1)導通，此時，由於該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都導通，因此，該第三節點(N3)的電位會被拉降至一邏輯低位準(0伏特)，再者，該第三節點(N3)的低電位傳送到該第二PMOS電晶體(MP2)和該第二NMOS電晶體(MN2)的閘極，使得該第二PMOS電晶體(MP2)導通、該第二NMOS電晶體(MN2)關閉，此時由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都關閉，而該第六NMOS電晶體(MN6)、該第二PMOS電晶體(MP2)以及該第四PMOS電晶體(MP4)都導通，因此，該第四節點(N4)的電位會維持在邏輯高位準的穩態值。質言之，第一信號(V(IN))為邏輯高位準(1.2伏特)時，經過電位轉換電路轉換成具高位準(VDDH)的第二信號，由輸出端(OUT)輸出。 Then consider the steady-state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic high level (1.2 volts): the logic high level on the first input terminal (IN) is simultaneously transmitted to the first inverter the input terminal of the device (I1), the third NMOS transistor (MN3), the sixth NMOS transistor (MN6) and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3 ) and the sixth NMOS transistor (MN6) are turned on (ON), and the third PMOS transistor (MP3) is turned off (OFF); and the first inverter (I1) transmits a low level (0 volts) to the gates of the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN4) The crystal (MN5) is turned off (OFF), and the fourth PMOS transistor (MP4) is turned on (ON). At this time, since the fourth PMOS transistor (MP4) and the sixth NMOS transistor (MN6) are both turned on (ON), and the fourth NMOS transistor (MN4) is turned off (OFF), therefore, the potential of the fourth node (N4) will be pulled to a logic high level, and furthermore, the fourth node (N4) The high potential is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first PMOS transistor (MP1) is turned off and the first NMOS transistor (MN1) is turned on. , at this time, since the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on, the potential of the third node (N3) will be pulled down to a logic low level (0 volts) ), furthermore, the low potential of the third node (N3) is transmitted to the gate of the second PMOS transistor (MP2) and the second NMOS transistor (MN2), so that the second PMOS transistor (MP2) turned on, the second NMOS transistor (MN2) is turned off. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, the sixth NMOS transistor (MN6), the Both the second PMOS transistor ( MP2 ) and the fourth PMOS transistor ( MP4 ) are turned on, so the potential of the fourth node ( N4 ) is maintained at a steady state value of a logic high level. Qualitatively speaking, first When the signal (V(IN)) is at a logic high level (1.2 volts), it is converted into a second signal with a high level (VDDH) through a potential conversion circuit, and is output from the output terminal (OUT).

綜上所述，第一信號(V(IN))為邏輯低位準(0伏特)時，第二信號(V(OUT))亦為邏輯低位準(0伏特)；而第一信號(V(IN))為第二高電位電壓(1.2伏特)時，第二信號(V(OUT))為第一高電位電壓(1.8伏特)。如此，電壓位準轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal (V( When IN)) is the second high potential voltage (1.2 volts), the second signal (V(OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

本創作所提出之降低功耗之電位轉換電路之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之降低功耗之電位轉換電路，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 Figure 4 shows the simulation results of Spice transient analysis of the potential conversion circuit for reducing power consumption proposed in this work. The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work not only still remains The first signal can be quickly and accurately converted into a second signal, and the power loss can be effectively reduced.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1:栓鎖電路 1: Latch circuit

2:輸出控制電路 2: Output control circuit

3:輸入電路 3: Input circuit

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

I1:第一反相器 I1: first inverter

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: the third NMOS transistor

MN4:第四NMOS電晶體 MN4: Fourth NMOS transistor

MN5:第五NMOS電晶體 MN5: Fifth NMOS transistor

MN6:第六NMOS電晶體 MN6: sixth NMOS transistor

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): Second signal

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

Claims

一種降低功耗之電位轉換電路，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極以及一第五NMOS電晶體(MN5)的汲極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極以及一第六NMOS電晶體(MN6)的汲極連接在一起；一第三節點(N3)，用以將該第五NMOS電晶體(MN5)的源極、一第一NMOS電晶體(MN1)的汲極、該第二PMOS電晶體(MP2)的閘極以及一第二NMOS電晶體(MN2)的閘極連接在一起；一第四節點(N4)，用以將該第六NMOS電晶體(MN6)的源極、一第二NMOS電晶體(MN2)的汲極、該第一PMOS電晶體(MP1)的閘極以及一第一NMOS電晶體(MN1)的閘極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)以及一第三NMOS電晶體(MN3)的閘極，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)以及一第四NMOS電晶體(MN4)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)、該第三PMOS電晶體(MP3)以及該第四PMOS電晶體(MP4)的源極，用以提供該降低功耗之電位轉換電路所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，用以提供該降低功耗之電位轉換電路所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一栓鎖電路(1)，耦接於該第一高電源供應電壓(VDDH)，用來保存差動輸入信號；一輸出控制電路(2)，耦接於該栓鎖電路(1)，用以控制該電位轉換電路的輸出信號之電位；以及一輸入電路(3)，耦接於該第一輸入端(IN)，用以提供差動輸入信號。 A potential conversion circuit for reducing power consumption for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for converting a The drain of the first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the drain of a fifth NMOS transistor (MN5) are connected together; a second node (N2) is connected with The drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the drain of a sixth NMOS transistor (MN6) are connected together; a third node (N3 ) for the source of the fifth NMOS transistor (MN5), the drain of a first NMOS transistor (MN1), the gate of the second PMOS transistor (MP2) and a second NMOS transistor The gates of (MN2) are connected together; a fourth node (N4) is used for the source of the sixth NMOS transistor (MN6), the drain of a second NMOS transistor (MN2), the first The gate of the PMOS transistor (MP1) and the gate of a first NMOS transistor (MN1) are connected together; a first input terminal (IN) is coupled to the third PMOS transistor (MP3) and a first The gates of the three NMOS transistors (MN3) are used to provide a first signal (V(IN)); a second input terminal (INB) is coupled to the fourth PMOS transistor (MP4) and a fourth The gate of the NMOS transistor (MN4) is used to provide an inversion signal of the first signal (V(IN)); an output terminal (OUT) is coupled to the fourth node (N4) and used to output the the second signal (V(OUT)); A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) Inverted signal; a first high power supply voltage (VDDH), coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the The source of the fourth PMOS transistor (MP4) is used to provide the first high potential voltage required by the potential conversion circuit for reducing power consumption; a second high power supply voltage (VDDL) is used to provide the power consumption reducing circuit The second high potential voltage required by the potential conversion circuit, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH); a latch circuit (1), coupled to The first high power supply voltage (VDDH) is used to store the differential input signal; an output control circuit (2) is coupled to the latch circuit (1) for controlling the output signal of the potential conversion circuit. electric potential; and an input circuit (3) coupled to the first input end (IN) for providing a differential input signal.

如申請專利範圍第1項所述的降低功耗之電位轉換電路，其中該栓鎖電路(1)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第一NMOS電晶體(MN1)，其源極連接至該第三NMOS電晶體(MN3)的汲極，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；一第二NMOS電晶體(MN2)，其源極連接至該第四NMOS電晶體(MN4)的汲極，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接；一第五NMOS電晶體(MN5)，其源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；以及一第六NMOS電晶體(MN6)，其源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接。 The potential conversion circuit for reducing power consumption as described in claim 1, wherein the latch circuit (1) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); A second PMOS transistor (MP2) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the third node (N3), and whose drain is connected to the second node ( N2) is connected; a first NMOS transistor (MN1), its source is connected to the drain of the third NMOS transistor (MN3), its gate is connected to the second node (N2), and its drain Then it is connected to the first node (N1); a second NMOS transistor (MN2), its source is connected to the drain of the fourth NMOS transistor (MN4), and its gate is connected to the first node ( N1), and its drain is connected to the second node (N2); a fifth NMOS transistor (MN5), its source is connected to the third node (N3), and its gate is connected to the second an input terminal (INB) whose drain is connected to the first node (N1); and a sixth NMOS transistor (MN6) whose source is connected to the fourth node (N4) and whose gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2).

如申請專利範圍第2項所述的降低功耗之電位轉換電路，其中該輸出控制電路(2)包括：一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 The potential conversion circuit for reducing power consumption as described in claim 2, wherein the output control circuit (2) comprises: a third PMOS transistor (MP3), the source of which is connected to the first high power supply voltage (VDDH), the gate of which is connected to the first input terminal (IN), and the drain of which is connected to the first node (N1); and A fourth PMOS transistor (MP4), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the second input terminal (INB), and whose drain is connected to the second node (N2) is connected.

如申請專利範圍第3項所述的降低功耗之電位轉換電路，其中該輸入電路(3)包括：一第三NMOS電晶體(MN3)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一NMOS電晶體(MN1)的源極相連接；一第四NMOS電晶體(MN4)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二NMOS電晶體(MN2)的源極相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The potential conversion circuit for reducing power consumption as described in claim 3, wherein the input circuit (3) comprises: a third NMOS transistor (MN3), the source of which is connected to the ground (GND), and the gate of which is connected to the ground (GND). connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), its source is connected to the ground (GND) ), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1), coupled to The first input terminal (IN) is used to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)).

如申請專利範圍第1項所述的降低功耗之電位轉換電路，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The potential conversion circuit for reducing power consumption as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL).

如申請專利範圍第5項所述的降低功耗之電位轉換電路，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The potential conversion circuit for reducing power consumption as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH).

如申請專利範圍第4項所述的降低功耗之電位轉換電路，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The potential conversion circuit for reducing power consumption as described in claim 4, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).