TWI637397B - 自動設時重置脈衝產生器及具有脈衝產生器的記憶體裝置 - Google Patents
自動設時重置脈衝產生器及具有脈衝產生器的記憶體裝置 Download PDFInfo
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Abstract
一種自動設時重置脈衝產生器,包含正反器、追蹤區塊和追蹤電路。正反器接收輸入訊號和回饋訊號,並輸出重置訊號。追蹤區塊具有串聯耦合的複製胞以複製在外部裝置的結構。追蹤區塊具有第一端和第二端。第一端和第二端位在追蹤區塊在相同位置或兩個不同位置處。追蹤電路單元接收重置訊號,並接收第一端和第二端,以分別對在第一端處的追蹤區塊進行放電,以及感測在第二端處由重置訊號觸發的電壓準位。當電壓準位小於或等於閾值時,作為回饋訊號的追蹤訊號被輸出到正反器。
Description
本發明大體上涉及一種記憶體裝置,具體來說,涉及一種自動設時重置脈衝產生器和具有自動設時重置脈衝產生器的記憶體裝置。
基本上,記憶體裝置包含記憶胞單元和週邊控制電路。週邊控制電路用以控制對記憶胞單元的記憶胞的存取。記憶胞單元可具有對不同結構的多種設計。然而,一串記憶胞在操作中需要進行放電或重置。
在記憶胞單元中,每一位元線上包含串聯耦合的多個記憶胞。位元線連接到用於選擇位元線的Y路徑電路。接著,多個放電和感測單元分別用於對位元線進行放電,以及感測位元線中的資料。
然而,在電阻、電容(RC)放電機制中,其所進行的放電處理對於記憶胞單元的存取操作上會消耗許多時間。因此,在加速存取時間的考量下,如何減少放電時間為一個值得考慮的課題。
本發明提出具有自動設時重置脈衝產生器的記憶體裝置,以便適當控制以停止位元線的放電處理。存取時間不會浪費在因恆定設置的放電時間所導致的充分完成放電處理的等待時間。
在一實施例中,本發明提供自動設時重置脈衝產生器,其包含正反器電路單元、追蹤區塊和追蹤電路單元。正反器電路單元接收輸入訊號和回饋訊號,並輸出重置訊號,其中重置訊號向外部輸出以對外部裝置進行重置。追蹤區塊具有串聯耦合的多個複製胞,並且複製在外部裝置中的結構,其中追蹤區塊具有第一端和第二端,其中第一端和第二端取自追蹤區塊在相同位置或兩個不同位置處。追蹤電路單元接收重置訊號,並接收第一端和第二端,以分別對在第一端處的追蹤區塊進行放電和感測在第二端處由重置訊號觸發的電壓準位,其中當作輸入到正反器電路的回饋訊號的追蹤訊號(TRACK_OUT signal)從第一邏輯狀態改變成第二邏輯狀態,以使得當在第二端處的電壓準位經比較而小於或等於所預定的閾值時,改變重置訊號的邏輯狀態。
在另一實施例中,關於上述的自動設時重置脈衝產生器,追蹤塊的複製胞是複製的記憶胞,以當作記憶體裝置中的複製位元線。
在另一實施例中,關於上述的自動設時重置脈衝產生器,延遲電路單元為緩衝器。
在另一實施例中,關於上述的自動設時重置脈衝產生器,追蹤電路單元包括用於對在第一端處的追蹤區塊進行放電的放電路徑和用於感測在第二端處的電壓準位的感測電路。
在另一實施例中,關於上述的自動設時重置脈衝產生器,第一端和第二端取自在追蹤區塊的中間區處的追蹤區塊的相同位置。
在另一實施例中,關於上述的自動設時重置脈衝產生器,第一端和第二端取自追蹤區塊的第一位置和第二位置,第一位置相對接近於追蹤區塊的第一末端,且第二位置相對接近於追蹤區塊的第二末端。
在另一實施例中,關於上述的自動設時重置脈衝產生器,第一位置為追蹤區塊的第一末端,且第二位置為追蹤區塊的第二末端。
在另一實施例中,本發明提供記憶體裝置,其包含記憶胞單元和自動設時重置脈衝產生器。記憶胞單元包含多個位元線、Y路徑電路以及多個放電和感測單元。位元線中的每一個包括串聯耦合的多個記憶胞;用於按照預期選擇位元線中的一個的Y路徑電路;以及多個放電和感測單元,它們分別對應於分別用於對位元線進行放電和感測位元線中的資料的位元線。自動設時重置脈衝產生器包含正反器電路單元、追蹤區塊和追蹤電路單元。正反器電路單元接收輸入訊號和回饋訊號,並輸出重置訊號,其中重置訊號向外部輸出以對記憶胞單元的位元線進行放電。追蹤區塊具有串聯耦合的多個複製胞,並在記憶胞單元中複製位元線中的一個的結構,其中追蹤區塊具有第一端和第二端,其中第一端和第二端取自追蹤區塊在相同位置或兩個不同位置處。追蹤電路單元接收重置訊號,並接收第一端和第二端,以分別對在第一端處的追蹤區塊進行放電和感測在第二端處由重置訊號觸發的電壓準位,其中當作輸入到正反器電路的回饋訊號的追蹤訊號從第一邏輯狀態改變成第二邏輯狀態,以使得當電壓準位經比較而小於或等於所預定的閾值時,重置訊號的邏輯狀態產生改變。
在另一實施例中,關於記憶體裝置,追蹤區塊的胞為根據位元線的記憶胞複製的記憶胞,以當作位元線在記憶胞單元中的複製位元線。
在另一實施例中,關於記憶體裝置,延遲電路單元為緩衝器。
在另一實施例中,關於記憶體裝置,追蹤電路單元包括用於對在第一端處的追蹤區塊進行放電的放電路徑和用於感測在第二端處的電壓準位的感測電路。
在另一實施例中,關於記憶體裝置,第一端和第二端取自在追蹤區塊的中間區處的追蹤區塊的相同位置。
在另一實施例中,關於記憶體裝置,第一端和第二端取自追蹤區塊的第一位置和第二位置,第一位置相對接近於追蹤區塊的第一末端,且第二位置相對接近於追蹤區塊的第二末端。
在另一實施例中,關於記憶體裝置,第一位置為追蹤區塊的第一末端,且第二位置為追蹤區塊的第二末端。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
現將詳細參考實施例配合圖式做說明。只要可能,相同的參考標號在圖式及描述中用以指代相同或相似部分。
記憶胞陣列基本上具有多個記憶胞。記憶胞串聯成為記憶胞串。所述記憶胞串也是待選擇的位元線的一部分。每一個記憶胞等效於RC(電阻、電容)電路單元,並且,記憶胞在操作中會累積一些電荷。在操作中,例如,具有記憶胞的位元線需要在讀取之前進行放電。然而,在操作中,放電時間並不總是相同的。通常來說,所設置長度恆定的時段需確保全部位元線在任何情況下都可完成放電。也就是說,實際上所述恆定的時段通常大於對位元線進行放電的實際需要。這會造成在存取操作上浪費時間。
本發明提出自動設時重置脈衝產生器,其可裝備在記憶體裝置中,以便及時停止放電處理而不浪費時間。提供若干實施例以描述本發明,並不用以限制本發明的範疇。
圖1為根據本發明的實施例的示意性地說明自動設時重置脈衝產生器的電路圖的圖式。參看圖1,一般來說,自動設時重置脈衝產生器110包含正反器電路單元100、延遲電路單元102、追蹤區塊104和追蹤電路單元106。自動設時重置脈衝產生器110大體上不限於用在可控制位元線的放電處理的記憶體裝置中。在另一方面,追蹤區塊104可為需要進行放電的總體電路的多個電路串中的一個的複製區塊。總體電路可為記憶體裝置或具有類似的待放電的記憶胞串的任何裝置。稍後如圖3中所示,以下實施例以記憶體裝置為例。
正反器電路單元100接收輸入訊號(例如讀取啟動訊號READ),以及接收回饋訊號(例如追蹤訊號TRACK_OUT)。正反器電路單元100還具有輸出重置訊號(例如重置訊號RESET)的一端。重置訊號RESET輸出至外部裝置以使外部裝置進行重置。如圖3中所示,在實施例中,外部裝置為記憶胞單元90。延遲電路單元延遲重置訊號RESET以具有重置追蹤訊號RETRACK。追蹤區塊104具有串聯耦合的多個複製胞,並用以複製外部裝置中的結構。追蹤區塊104具有第一端112和第二端114,其中第一端112和第二端114位於追蹤區塊104上的相同位置或兩個不同位置處。
在實施例中,第一端112和第二端114位於追蹤區塊104的中間區處的相同位置,在圖4中有更詳細的描述。
在圖1的實施例中,第一端112和第二端114位於追蹤區塊104的第一位置和第二位置。第一位置相對第二位置更接近於追蹤區塊104的第一末端,且第二位置相對第一位置更接近於追蹤區塊104的第二末端。再者,在實施例中,第一位置可為追蹤區塊的第一末端,且第二位置則可為追蹤區塊的第二末端。
圖1中使追蹤區塊104具有的兩種位置的設置方式具有至少一個原因。對於具有多個胞的串列,如果追蹤區塊104在第一末端(即如圖1中所示的追蹤區塊104的下部末端處)進行放電,那麼可預期的,在第二末端(即如圖1中所示的頂部末端)處的開始的胞將會是最後一個結束放電處理的胞。在第二端114處的電壓準位將確保可完成放電處理。
在隨後的動作中,追蹤電路單元106接收第一端112和第二端114,以對在第一端112處的追蹤區塊104進行放電,並感測在第二端114處的電壓準位。作為回饋訊號的追蹤訊號TRACK_OUT從追蹤電路單元106輸出到正反器電路單元100。追蹤訊號TRACK_OUT被觸發到邏輯高狀態,以禁能重置訊號RESET,其中,重置訊號RESET被發送到放電和感測單元96(見圖3)。隨後,重置訊號RESET被改變成邏輯低狀態,以及時停止放電處理。
圖1中的延遲電路單元102,例如緩衝器,根據訊號RESET訊號設置預設延遲,以確保外部裝置充分開始放電處理。
在另一方面,自動設時重置脈衝產生器110可被視為兩個部分,其中一個部分為追蹤區塊104,另一部分為重置控制電路120。重置控制電路120包含正反器電路單元100、延遲電路單元102和追蹤電路單元106。
圖2為根據本發明的實施例的示意性地說明追蹤電路單元的電路圖的圖式。為更詳細地描述追蹤電路單元106,請參看圖2。在實施例中,追蹤電路單元106包含放電電路106a和感測電路106b。放電電路106a提供放電路徑,並且在實施例中,放電電路106a包含電晶體開關。所述電晶體開關受重置追蹤訊號RETRACK的控制以引發在第一端112處的追蹤區塊104的放電處理。在實施例中,感測電路106b包含感測放大器,用以感測在第二端114處的電壓準位,並在電壓準位小於或等於閾值時,感測電路106b輸出追蹤訊號TRACK_OUT。追蹤訊號TRACK_OUT為被提供到如圖1所示的正反器電路單元100的回饋訊號。
在實施例中,自動設時重置脈衝產生器110可應用於記憶體裝置。圖3為根據本發明的實施例的示意性地說明記憶體裝置的電路圖的圖式。參看圖3,記憶體裝置包含記憶胞單元90和自動設時重置脈衝產生器110。
記憶胞單元90包含多個位元線92、Y路徑電路94和多個放電和感測單元96。每一位元線92包含串聯耦合的多個記憶胞CELL。Y路徑電路94與位元線92耦合,並選擇所需的位元線92的其中之一。放電和感測單元96分別對應於位元線92,並分別對位元線92進行放電以及感測位元線中的資料。在實施例中,如通常在本領域中所知而不需詳細描述的,放電和感測單元96包含放電電路96a和感測電路96b。放電電路96a可由重置訊號RESET控制以執行放電處理。感測電路96b可由感測啟動訊號ENSA控制以執行感測處理。在低功率操作的實施例中,感測啟動訊號ENSA依據重置訊號RESET的下降邊緣觸發,並且感測啟動訊號ENSA的邏輯狀態將從低改變成高。感測啟動訊號ENSA可在一時段之後被禁能或由讀取啟動訊號READ的上升邊緣來被禁能。並且感測啟動訊號ENSA的邏輯狀態將從高改變成低。在高速操作的實施例中,感測啟動訊號ENSA始終保持為高。
與記憶胞單元90配置的自動設時重置脈衝產生器110包含等效於位元線92、Y路徑電路94以及放電和感測單元96的複製電路,並且,自動設時重置脈衝產生器110進一步包含控制機構。因此,同樣還參看圖1,自動設時重置脈衝產生器110可被視為兩個部分,其中一個部分為追蹤區塊104,另一部分為重置控制電路120。重置控制電路120包含正反器電路單元100、延遲電路單元102和追蹤電路單元106。在具有記憶胞單元90的自動設時重置脈衝產生器110的應用的實施例中,正反器電路單元100接收輸入訊號(例如讀取啟動訊號READ和回饋訊號TRACK_OUT),並輸出重置訊號RESET。重置訊號RESET向外部輸出,以通過與先前段落中描述的相同的機構對記憶胞單元90的位元線92進行放電。延遲電路單元102延遲重置訊號RESET以使重置訊號RESET具有重置追蹤訊號RETRACK。
另外,追蹤區塊104具有串聯耦合的多個複製胞116a,並在記憶胞單元中複製位元線92中其中之一的結構。另外,在實施例中,Y路徑電路94也可被追蹤區塊104中的Y路徑電路118所複製。追蹤區塊104具有第一端112和第二端114,其中第一端112和第二端114位於追蹤區塊104的相同位置或兩個不同位置處。詳細地說,第一端112和第二端114位於複製位元線116的相同位置或兩個不同位置處。在圖3的實施例中,第一端112和第二端114位於追蹤區塊104的兩個不同位置122和124處,所述位置122和124對應於如圖1中所繪示的第一端112和第二端114處的兩個位置。
重置控制電路120的追蹤電路單元106接收第一端112和第二端114,以分別對在第一端112處的追蹤區塊104或複製位元線116進行放電(細節上來說,在第一端112進行放電),以及感測在第二端114處的電壓準位。作為回饋訊號的追蹤訊號TRACK_OUT被輸出到正反器電路單元100。當第二端114的電壓準位小於或等於閾值時,追蹤訊號TRACK_OUT被觸發到邏輯高狀態以禁能重置訊號RESET,所述重置訊號RESET被發送到放電和感測單元96。隨後,將重置訊號RESET改變成邏輯低狀態以及時停止放電處理。
在實施例中,複製位元線116的胞的字元線端126還可連接到對應的記憶胞單元90的胞的字元線端WL,以具有更好的複製條件。然而,在又另一實施例中,為了避免對記憶胞單元90中的感測速度產生影響,屬於記憶胞單元90的字元線端WL可以不連接到複製位元線116。在此情形下,複製位元線116的胞的字元線端126可以連接到恆定電壓,或是也可以連接到所述胞的另一端。
關於追蹤區塊104的第一端112和第二端114,提供另一實施例。圖4為根據本發明的實施例的示意性地說明自動設時重置脈衝產生器的電路圖的圖式。除了第一端112和第二端114的位置之外,圖4中的自動設時重置脈衝產生器110的實施例與圖1中繪示的自動設時重置脈衝產生器110相類似。在此實施例中,第一端112和第二端114位在追蹤區塊的中間區處的,即圖3中的複製位元線116的追蹤區塊104的相同位置。在此情形下,位元線還可從第一端112進行放電。然而,第二端114不連接到整個追蹤區塊中預期最晚時間進行放電的胞。無論如何,這種差異可使得對位元線的放電動作的停止時間點稍微早於如圖1中透過第二端114連接到末端胞的狀態。即使以此方式,本發明的概念對於及時停止放電處理仍是有效。
圖5為根據本發明的實施例的示意性地說明用於自動設時重置脈衝產生器的訊號的時序圖。參看圖5,繪示了用於讀取啟動訊號READ、重置訊號RESET、重置追蹤訊號RETRACK、感測和追蹤訊號TRACK_OUT的時序。讀取啟動訊號READ為來自系統的用以存取記憶體的讀取啟動訊號。重置訊號RESET將被發送到放電和感測單元96,以及時控制(開始或停止)放電處理。重置追蹤訊號RETRACK由延遲電路單元102根據訊號RESET延遲一預設時間來產生,用以確保記憶胞單元90(外部裝置)充分的啟動放電處理。感測訊號為在追蹤區塊104的第二端114處的電壓準位。當感測訊號的電壓準位下降到等於或小於閾值時,輸出追蹤訊號TRACK_OUT。追蹤訊號TRACK_OUT被回饋回到正反器電路單元100,以禁能重置訊號RESET,從而停止記憶胞單元90中的放電處理。
在高速操作的實施例中,追蹤電路單元106的感測電路106b始終開啟。在低功率操作的實施例中,一旦讀取啟動訊號READ變成高準位Hi,感測電路106b就會被開啟,並且在追蹤訊號TRACK_OUT從Hi變成低準位Lo之後,感測電路106b就被關閉。
圖6為根據本發明的實施例的示意性地說明用於在操作中的自動設時重置脈衝產生器的方法的圖式。參看圖6,根據本發明的另一方面,操作自動設時重置脈衝產生器110以控制放電時間的方法可包含若干步驟。在步驟S100中,讀取啟動訊號READ啟動讀取處理。在步驟S102中,開啟所選擇的位元線92的Y路徑電路以及複製位元線116的Y路徑電路118。在步驟S104中,對主陣列的所選擇的位元線和複製位元線進行重置以開始放電。在步驟S106中,檢測在第二端114處的複製位元線的電壓準位。在步驟S108中,禁能重置訊號RESET,使所選擇的位元線停止放電,並且接著開始感測資料。
本發明已提出自動設時重置脈衝產生器110以通過追蹤區塊複製實際位元線。因此,檢測追蹤區塊的電壓準位可確定停止對位元線進行放電的時間,以便及時開始感測位元線的資料。本發明可確保放電處理的完成,並及時開始感測處理。可有效避免由於重置時間的恆定設置導致的等待時間。可加速對記憶體的存取時間。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
90:記憶胞單元 92:位元線 94:Y路徑電路 96:放電和感測單元 96a:放電電路 96b:感測電路 100:正反器電路單元 102:延遲電路單元 104:追蹤區塊 106:追蹤電路單元 106a:放電電路 106b:感測電路 110:自動設時重置脈衝產生器 112:第一端 114:第二端 116:複製位元線 116a:複製胞 116b:複製胞 118:Y路徑電路 120:重置控制電路 122:位置 124:位置 126:字元線端 WL:字元線端 READ:讀取啟動訊號 RESET:重置訊號 TRACK_OUT:追蹤訊號 RETRACK:重置追蹤訊號 ENSA:感測啟動訊號 S100、S102、S104、S106、S108:步驟
圖1為根據本發明的實施例的示意性地說明自動設時重置脈衝產生器的電路圖的圖式。 圖2為根據本發明的實施例的示意性地說明追蹤電路單元的電路圖的圖式。 圖3為根據本發明的實施例的示意性地說明記憶體裝置的電路圖的圖式。 圖4為根據本發明的實施例的示意性地說明自動設時重置脈衝產生器的電路圖的圖式。 圖5為根據本發明的實施例的示意性地說明用於自動設時重置脈衝產生器的訊號的時序圖的圖式。 圖6為根據本發明的實施例的示意性地說明用於在操作中的自動設時重置脈衝產生器的方法的圖式。
Claims (16)
- 一種自動設時重置脈衝產生器,包括: 正反器電路單元,接收輸入訊號和回饋訊號,並輸出重置訊號,其中所述重置訊號向外部輸出以對外部裝置進行重置; 追蹤區塊,具有串聯耦合的多個複製胞,並且複製在所述外部裝置中的結構,其中所述追蹤區塊具有第一端和第二端,其中所述第一端和所述第二端取自所述追蹤區塊在相同位置或兩個不同位置處;以及 追蹤電路單元,接收所述重置訊號,並接收所述第一端和所述第二端,以分別對在所述第一端處的所述追蹤區塊進行放電和感測,在所述第二端處由所述重置訊號觸發的電壓準位,其中當作所述回饋訊號的追蹤訊號被輸出到所述正反器電路單元, 其中當作所述回饋訊號輸入到所述正反器電路的所述追蹤訊號從第一邏輯狀態改變成第二邏輯狀態,以使得當在所述第二端處的所述電壓準位經比較而小於或等於所預定的閾值時,改變所述重置訊號的邏輯狀態。
- 如申請專利範圍第1項所述的自動設時重置脈衝產生器,其中所述追蹤區塊的所述胞是複製的記憶胞,以當作在記憶體裝置中的複製位元線。
- 如申請專利範圍第1項所述的自動設時重置脈衝產生器,進一步包括用於在所述重置訊號進入所述追蹤電路單元中之前延遲所述重置訊號的延遲電路單元。
- 如申請專利範圍第3項所述的自動設時重置脈衝產生器,其中所述延遲電路單元為緩衝器。
- 如申請專利範圍第1項所述的自動設時重置脈衝產生器,其中所述追蹤電路單元包括用於對在所述第一端處的所述追蹤區塊進行放電的放電路徑和用於感測在所述第二端處的所述電壓準位的感測電路。
- 如申請專利範圍第1項所述的自動設時重置脈衝產生器,其中所述第一端和所述第二端取自在所述追蹤區塊的中間區處的所述追蹤區塊的所述相同位置。
- 如申請專利範圍第1項所述的自動設時重置脈衝產生器,其中所述第一端和所述第二端取自所述追蹤區塊的第一位置和第二位置,所述第一位置相對接近於所述追蹤區塊的第一末端,且所述第二位置相對接近於所述追蹤區塊的第二末端。
- 如申請專利範圍第7項所述的自動設時重置脈衝產生器,其中所述第一位置為所述追蹤區塊的所述第一末端,且所述第二位置為所述追蹤區塊的所述第二末端。
- 一種記憶體裝置,包括: 記憶胞單元,包括: 多個位元線,每一位元線包括串聯耦合的多個記憶胞; Y路徑電路,其用於按照預期選擇所述位元線中的一個;以及 多個放電和感測單元,分別對應於分別用於對所述位元線進行放電和感測所述位元線中的資料的位元線;以及 自動設時重置脈衝產生器,包括: 正反器電路單元,接收輸入訊號和回饋訊號,並輸出重置訊號,其中所述重置訊號向外部輸出以用於對所述記憶胞單元的所述位元線進行放電的重置; 追蹤區塊,其具有串聯耦合的多個複製胞,並在所述記憶胞單元中複製所述位元線中的一個的結構,其中所述追蹤區塊具有第一端和第二端,其中所述第一端和所述第二端取自所述追蹤區塊在相同位置或兩個不同位置處;以及 追蹤電路單元,其接收所述重置訊號,並接收所述第一端和所述第二端,以分別對在所述第一端處的所述追蹤區塊進行放電和感測在所述第二端處由所述重置訊號觸發的電壓準位, 其中當作所述回饋訊號輸入到所述正反器電路的所述追蹤訊號從第一邏輯狀態改變成第二邏輯狀態,以使得當在所述第二端處的所述電壓準位經比較而小於或等於所預定的閾值時,改變所述重置訊號的邏輯狀態。
- 如申請專利範圍第9項所述的記憶體裝置,其中所述追蹤區塊的所述胞是根據所述位元線的所述記憶胞複製的記憶胞,以當作所述位元線在所述記憶胞單元中的複製位元線。
- 如申請專利範圍第9項所述的記憶體裝置,其中所述自動設時重置脈衝產生器進一步包括用於在所述重置訊號進入所述追蹤電路單元中之前延遲所述重置訊號的延遲電路單元。
- 如申請專利範圍第11項所述的記憶體裝置,其中所述延遲電路單元為緩衝器。
- 如申請專利範圍第9項所述的記憶體裝置,其中所述追蹤電路單元包括用於對在所述第一端處的所述追蹤區塊進行放電的放電路徑和用於感測在所述第二端處的所述電壓準位的感測電路。
- 如申請專利範圍第9項所述的記憶體裝置,其中所述第一端和所述第二端取自在所述追蹤區塊的中間區處的所述追蹤區塊的所述相同位置。
- 如申請專利範圍第9項所述的記憶體裝置,其中所述第一端和所述第二端取自所述追蹤區塊的第一位置和第二位置,所述第一位置相對接近於所述追蹤區塊的第一末端,且所述第二位置相對接近於所述追蹤區塊的第二末端。
- 如申請專利範圍第15項所述的記憶體裝置,其中所述第一位置為所述追蹤區塊的所述第一末端,且所述第二位置為所述追蹤區塊的所述第二末端。
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