TWI594427B - 半導體裝置結構及相關製程 - Google Patents

半導體裝置結構及相關製程 Download PDF

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TWI594427B
TWI594427B TW098104762A TW98104762A TWI594427B TW I594427 B TWI594427 B TW I594427B TW 098104762 A TW098104762 A TW 098104762A TW 98104762 A TW98104762 A TW 98104762A TW I594427 B TWI594427 B TW I594427B
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gate
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semiconductor device
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鄭峻
莫哈曼Ｎ 達沃奇
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馬克斯半導體股份有限公司
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Description

半導體裝置結構及相關製程
本發明係關於場效電晶體及方法，且更特定而言係關於具有一凹陷式場板(RFP)之高可靠性功率絕緣閘極場效電晶體(MOSFET)及相關技術。
本申請案主張2008年2月14日申請之序號為61/065,759號之美國臨時申請案之優先權，該申請案之全文以引用方式併入本文中。
功率MOSFET作為開關裝置而廣泛用於諸多電子應用中。為最小化傳導功率損失，可期望MOSFET具有低特定導通電阻，該特定導通電阻被定義為導通電阻面積乘積(Ron *A)，其中Ron 係MOSFET處於一導通(ON)狀態中時之一MOSFET電阻，其中A係MOSFET之面積。渠溝MOSFET提供低特定導通電阻，特定而言在10-100電壓範圍內。隨著單元密度增加，諸如一閘極至源極電容Cgs、一閘極至汲極電容Cgd及/或一汲極至源極電容Cds之任何相關聯電容亦增加。在諸如行動產品中之同步降壓dc-dc轉換器等諸多開關應用中，具有30V崩潰電壓之MOSFET通常以接近1MHz之較高速度運作。因此，可期望最小化由此等電容引起之開關或動態功率損失。此等電容之量值與閘極電荷Qg、閘極-汲極電荷Qgd及輸出電荷Qoss成正比。此外，對於在第三象限中運作之一裝置(亦即，當一汲極-本體接面變成正向偏壓時)，少數電荷在其正向傳導期間儲存於該裝置中。此所儲存電荷在自傳導切換至非傳導中引起一延遲。為克服此延遲，可期望一具有快速反向恢復之本體二極體。然而，一快速恢復本體二極體通常引起高電磁干擾(EMI)。此意味著在二極體恢復期間，負向波形(ta )與正向波形(tb )之間的比率對於一避免EMI問題之軟恢復而言必須小於1。
由於開關速度要求隨著新應用而增加至1MHz及更大，因此先前技術狀態之功率MOSFET愈加不能以令人滿意之效率以此等高速度運作。可期望一除具有一低特定導通電阻(Ron*A)之外亦具有低電荷Qg、Qgd、Qoss及Qrr之功率MOS電晶體。
存在兩種用以改良功率MOSFET之開關效能之常見技術。第一種技術係具有厚底部氧化物之渠溝閘極MOSFET，如圖1中所示(美國專利第6,849,898號)。第二種技術係***式多晶閘極MOSFET結構，其中第一多晶閘極電短接至源電極(美國專利第5,998,833、6,683,346號)，如圖2中所圖解闡釋。
最近，如圖3中所示，Darwish之美國專利申請案第2008/0073707 A1號揭示一種具有凹陷式場板(RFP)結構之功率MOSFET，該凹陷式場板(RFP)結構實現了一用於進一步減少閘極-源極電容及閘極-汲極電容、且因此總閘極電荷(Qg)及"米勒"電荷(Qgd)之極短通道區(~0.25微米)。另外，該RFP結構由於為電流及由該RFP引發之漂移區之增強耗乏提供一額外路徑而改良本體二極體反向恢復速度。
本申請案揭示對具有凹陷式場板(RFP)及類似結構之功率絕緣閘極場效電晶體之改良。發明者已認識到可藉由將一補償植入執行至RFP渠溝中來改良RFP型功率MOSFET之效能。此補償植入有助於在關斷(OFF)狀態中使耗乏邊界成形，且因此有助於避免擊穿。因此，亦可於漂移或散佈區中將一局域增強添加至通道與汲極之間之摻雜。此提供一增效組合，其中可在不使崩潰電壓降級之情形下改良導通電阻。
所揭示之創新在各種實施例中提供至少以下優點中之一或多者。然而，並非所有此等優點均係由所揭示之創新中之每一者產生，且此優點列表不限定各種所請求之發明。
‧經改良(減少)之導通電阻；
‧經改良(減少)之崩潰；
‧RFP渠溝底部處任一介電層上減少之電應力；
‧較高之可靠性及較長之運作壽命；及/或
‧在漂移區中增加局域摻雜濃度之增加之能力。
本文將特別參考當前較佳之實施例(藉助實例而非限定方式)闡述本申請案之眾多創新性教示內容。本申請案闡述數項實施例，且不應將以下陳述視作大體限定申請專利範圍。
為圖解闡釋之簡明及清晰起見，圖式圖解闡釋一般構造方式，且可省略眾所習知之特徵及技術之闡述及細節以避免不必要地混淆本發明。另外，圖式中之元件不必按比例來繪製，可放大某些區域或元件以有助於改良對本發明實施例之理解。
在說明書及申請專利範圍中，術語"第一"、"第二"、"第三"、"第四"等(若存在)可用於在類似元件之間加以區分而未必用於闡述一特定之相繼或時間次序。應理解，如此使用之術語可互換。此外，術語"包括"、"包含"、"具有"及其任何變化意欲涵蓋非排他性包含，以使一包括一元件列表之製程、方法、物件、設備或組成不必侷限於彼等元件，但可包含未明確列出或此製程、方法、物件、設備或組成所固有之其他元件。
本發明預期且意欲將該設計應用於n型及p型MOSFET兩者；出於清晰之原因，基於n通道MOSFET結構給出實例，但熟習此項技術者將知曉修改該設計以製造一類似之p通道裝置之變化。
本申請案揭示對具有凹陷式場板(RFP)及類似結構之功率絕緣閘極場效電晶體之改良。發明者已認識到可藉由將一補償植入執行至RFP渠溝中來改良RFP型功率MOSFET之效能。此補償植入有助於在關斷狀態中使耗乏邊界成形，且因此有助於避免擊穿。因此，亦可在漂移或散佈區中將一局域增強添加至通道與汲極之間之摻雜。此提供一增效組合，其中可在不使崩潰電壓降級之情形下改良導通電阻。
在一個樣本實施例中，含有RFP之MOSFET具有一埋置式深補償帶，該深補償帶浮動於RFP渠溝下方之N本體區中。該深補償帶在施加一高汲極-源極電壓時減少跨越該RFP與N-磊晶層之間的介電層之電壓。
在一個樣本實施例中，含有RFP之MOSFET具有：一埋置式深補償帶，其浮動於RFP渠溝下方之N本體區中；及一在N磊晶層中之漂移或散佈區中對通道與汲極之間的摻雜之局域增強。
在一項實施例中，含有RFP之MOSFET亦在與RFP渠溝壁接觸之P本體中具有一深P+區，該深P+區自該P本體延伸至N磊晶層中。
在一項實施例中，RFP渠溝下方之深補償帶延伸至且連接至源電極。
在一項實施例中，RFP渠溝下方之深補償帶延伸至與RFP渠溝側壁接觸之P本體區。
在一項實施例中，深補償帶係一極輕摻雜之p區；而在另一實施例中，深補償帶係一極輕摻雜之n區。
現在參考圖4(a)，一半導體裝置結構100包括一閘極102，該閘極定位於一第一渠溝104(本文中亦闡述為一閘極渠溝104)中。含有閘極102之第一渠溝104可係半導體裝置結構100內諸多閘極渠溝中之一者。半導體裝置結構100係以電容方式被耦合以控制自一具有一第一傳導性類型之源極區106穿過與第一渠溝104毗鄰之半導體材料108之垂直傳導。
如圖4(a)中所示，閘極102具有一閘電極，該閘電極包括具有一約等於閘極渠溝104之一寬度之寬度之傳導閘極材料。應瞭解，儘管該閘電極可具有一約等於閘極渠溝104之寬度之寬度，但另一選擇為可使用一更寬之閘極渠溝及一更小之閘電極來接觸該閘電極，從而允許該閘極渠溝與閘極導體絕緣。
半導體裝置結構100亦包含凹陷式場板110，該等凹陷式場板經定位而接近且以電容方式耦合至半導體材料108。凹陷式場板110定位於相應之第二渠溝112(本文中亦闡述為RFP渠溝112)中。該等渠溝(亦即，相應之第二渠溝112及該等閘極渠溝)中之每一者皆具有渠溝壁，該等渠溝壁塗佈有諸如二氧化矽(SiO2 )之一絕緣材料。RFP渠溝112含有一絕緣材料，該絕緣材料具有一較佳超過半導體裝置結構100之崩潰電壓之崩潰電壓。閘極渠溝104較佳含有一直至p本體汲極接面之絕緣材料，從而最小化該閘電極(連接至閘極102)與汲極或漂移區之任一重疊。
在一項實施例中，該閘極渠溝含有諸如二氧化矽之厚底部絕緣介電材料。在另一實施例中，RFP渠溝及/或閘極渠溝104內之絕緣材料具有一階梯式厚度。提供一階梯式厚度可有助於使通道成形且可有助於控制"熱"電子效應。
傳導材料(例如n型摻雜多晶矽)形成一藉由絕緣材料而與閘極渠溝104電分離之閘電極。可矽化該傳導材料以減小其電阻。傳導材料亦填充RFP渠溝112，藉由絕緣材料而與閘極渠溝104電分離且在RFP渠溝上面延伸以形成複數個RFP電極。儘管該RFP電極比閘電極深且係獨立地受到偏壓或連接至一源電極(亦即，源極106)，但該等渠溝中之每一者可具有大致相等之深度或在深度上可係不同且可藉由以相同處理步驟被蝕刻而自對準，且一源極區(包含源電極)可延伸於閘極106與RFP渠溝112之間。
在一項實施例中，對n-磊晶漂移區進行均勻地摻雜。在另一實施例中，不對n-磊晶漂移區進行均勻地摻雜。具體而言，摻雜經分級以在一與下伏基板118之介面處具有一較高且朝向表面降低之摻雜濃度。對汲極漂移區進行非均勻摻雜允許通道之較大成形且允許控制"熱"電子注入。
可將源極區摻雜為n+。閘極渠溝104及RFP渠溝可具有一減少導通電阻之薄絕緣材料層或一提供增加反向偏壓崩潰電壓之較大電隔離之厚絕緣材料層。在所繪示之實施例中，RFP電極具有一均勻深度。在另一實施例中，該等RFP電極中之至少一者向上延伸且接觸源極106。
有利地，半導體裝置結構100亦包含p型或n型之深補償帶114，該等深補償帶至少部分地位於相應之RFP渠溝112下方。深補償帶114可係RFP渠溝下方之N-漂移區中之p型摻雜劑濃度區(如圖4a中所示)或輕摻雜n型摻雜劑濃度區之浮動島。圖式顯示此補償帶114之邊界，彷彿已對其進行完全逆摻雜，但熟習此項技術者將理解，可使用(舉例而言)一單個摻雜劑種類之濃度輪廓類似地構想一經補償但未經逆摻雜帶之邊界。
深補償帶114亦在施加一高汲極-源極電壓時降低跨越RFP與N-磊晶層之間的介電層之電壓。
如圖4(b)中所示，裝置100亦含有一與RFP渠溝112之側壁接觸之深p本體區116。在116a處具有邊界之深p本體區116可與源電極連接且亦可與深補償帶114連接。可藉由深補償植入及其在不添加新遮罩之情形下之相關退火來形成邊緣終止中之深P-N接面。因此，所揭示之結構可提供一較可靠之邊緣終止。
另一選擇為，如圖4(c)中所示，深補償帶114可垂直延伸且與p本體區合併。
圖5中所顯示之兩維電壓模擬展現：在相同之偏壓條件下，圖3中所示之習用結構裝置跨越RFP與N-磊晶層之間的底部介電層具有約19V，而圖4(a)-(c)之一實施例由於來自深補償帶114之保護而跨越RFP與N-磊晶層之間的底部介電層僅顯示7V。
由於RFP與汲極之間的底部介電層上之電應力顯著減少，因此圖4(a)-(c)之裝置結構將提供一較高之可靠性及較長之運作壽命。另外，深補償帶114增強N-磊晶層之橫向及垂直耗乏，此在不使該裝置崩潰電壓降級之情形下提供用於該磊晶層中較高之局域摻雜濃度之空間。
磊晶層中局域摻雜濃度之增加進一步減小漂移區之導通電阻。藉由適當地調整N-磊晶層中P及N區之摻雜濃度，可在不減小崩潰電壓之情形下降低裝置之總導通電阻。此外，局域摻雜增強之N層亦降低該裝置之本體二極體之少數載流子注入效率且改動本體二極體反向恢復期間之電場分佈。因此，改良了該本體二極體之反向恢復，從而產生一具有較低反向恢復電荷及軟恢復特徵之裝置。
由於摻雜增強僅出現於作用區中，因此經改良之裝置邊緣接面終止區之終止效率將不會發生降級。
凹陷式場板110可定位於與閘極渠溝104分離之多個相應渠溝112中。因此，半導體裝置100可係(舉例而言)一n通道MOSFET，該MOSFET具有一凹陷式場板(RFP)渠溝112及一形成於生長在一重摻雜N+基板上方之一N-型磊晶層上之閘極渠溝104。
在其中汲極118相對於一源極-本體電極(亦即，源極106)受到負偏壓且其中擴散電流導致少數載流子注入及一高反向恢復電荷Qrr之第三象限運作中，複數個RFP電極形成除由一習用結構中之閘電極提供之路徑外之自汲極至源極之多數載流子通道電流路徑。RFP電極與閘電極之組合效應係減少之少數載流子擴散電流及減少之恢復電荷Qrr兩者。因此，在第三象限運作中，RFP電極充當一額外閘極，而一添加之閘極-汲極電容Cgd無任一損失。
在反向偏壓運作中，RFP亦減少一通道區中之任一電場。因此，在無擊穿崩潰之實質風險之情形下可能有更短之通道長度，從而進一步允許Ron*A及Qg之減少。當一汲極-源極電壓VDS在一關斷狀態中增加時，閘極渠溝104、RFP渠溝112與汲極區之間的電容性耦合進一步以一更高速率耗乏汲極漂移區。低Cgd及其快速下降速率與增加之汲極-源極電壓VDS組合提供一更低之閘極-汲極電荷。
半導體裝置結構100可具有一準垂直或橫向組態。確保半導體裝置結構100具有一準垂直或橫向組態可有助於使通道成形且可減少熱電子效應。
可使用閘極導體及RFP導體之各種變化。Darwish之美國申請案第2008/0073707 A1號中已顯示各種組合，該申請案之全文以引用方式併入本文中。多晶矽可用作傳導材料。閘極導體及RFP導體之結構性設計中之實例性變化包含***式多晶組態及單個多晶組態(圖21-25)、厚底部氧化物及階梯狀底部氧化物及各種形式之組合。
參考圖26，前述實施例中之每一者可以一單個組態、一多條紋組態、一蜂巢式佈局組態或前述組態之一組合來實施。此外，可反轉極性及傳導性類型。
參考圖27，前述實施例RFP中之每一者亦可以一其中RFP渠溝及導體於裝置之源極-本體-汲極層中形成行之一中斷方式來實施。在此中斷方案中，可提供較多之N++表面積，從而減小N++電阻且降低總導通電阻。
圖6-18中詳述一用於製造所闡述之實施例之製作製程。在圖6中，以N++基板201開始，使N-磊晶層203生長，隨後形成一薄層之氧化矽層205。基板201可已摻雜有磷或砷。舉例而言，氧化物層205之較佳厚度可係200-300A。在圖7中，應用渠溝遮罩207以形成用於渠溝蝕刻之硬遮罩且蝕刻該氧化物層。
然後，實施一標準矽蝕刻步驟以根據該遮罩形成複數個渠溝209。在圖8中，可對整個裝置執行毯覆磷離子211(舉例而言，P31 )植入以局域地增加N-磊晶層之摻雜濃度。該植入較佳以0度傾斜來達成。圍繞邊緣終止區域或閘極匯流排區域(圖中未顯示)之渠溝遮罩防止磷摻雜劑進入此等區域中。因此，僅裝置之作用區接受摻雜增強植入。
在植入之後，在一含氧氣氛中使用一高溫製程使該磷摻雜劑退火及擴散。因此，N-磊晶層內側形成一摻雜增強N層213，如圖9中所示。然後，可首先使用一犧牲氧化來氧化渠溝壁。在移除犧牲氧化物層之後，使一墊氧化物沿渠溝側壁再生長。在圖10中，該等渠溝填充有高密度氧化物217。氧化物217可包含二氧化矽或其他類型之沈積氧化物，例如LTO或TEOS或高密度電漿(HDP)氧化物。然後，如圖11中所示，使用一干式電漿蝕刻或CMP技術將該氧化物變薄以平坦化氧化物表面219。
在圖12中，在於渠溝222上方留有開口之狀況下已應用作用遮罩223之後，進一步向下蝕刻該氧化物至渠溝中以形成渠溝底部氧化物層(BOX)221。然後，在圖13中，使用該BOX遮罩來保護作用閘極渠溝225及邊緣終止區域(未顯示)。實施氧化物移除步驟以完全蝕刻掉RFP渠溝內之BOX。在移除該BOX遮罩之前，透過RFP渠溝底部231將硼-11離子229植入至N/N-磊晶層中，從而形成圖14中所示之P層或隔離帶237。
在一項實施例中，為實施圖4(c)中所示之結構，使用一傾斜角度植入沿RFP側壁引入硼。在移除BOX光阻劑233之後，採用一可選高溫退火來使硼擴散，從而在N-磊晶區內側形成P層或隔離帶237。然後，在圖14中，使閘極氧化物235沿渠溝側壁生長。
圖15至圖17中所示之剩餘製程步驟與美國專利申請案第2008/0073707號中之圖14-17中所闡釋之步驟類似，該申請案以引用方式併入本文中。圖18中顯示最終裝置結構。有必要指出，藉由適當地選擇與P+植入之植入能量組合之RFP多晶凹陷深度，可使P+區比P本體深，如圖19A中所示。端視P屏蔽區(或隔離帶)之摻雜濃度，P屏蔽帶可係圖19C中所示之一"π"區260(一極輕摻雜P區)或圖19B中所示之一"v"區250(一極輕摻雜n區)。需要一較深P+區以改良裝置堅固性且將埋置式P區連接至源電極。另外，如圖20中所示，亦可使N++源極區完全凹陷，以便可消除N++源極光遮罩步驟。
此外，亦可使用***式多晶閘極裝置結構來實施本發明中所提議之技術。圖21至圖23中簡單展示實施方案中之一者。該製程包含在該等渠溝中沈積一第一多晶層、多晶回蝕及氧化物移除、閘極氧化、第二多晶層沈積以及CMP及/或多晶回蝕。使用圖21-23中所示之***式閘極雙多晶組態來替換圖18中所示之作用渠溝閘極及RFP渠溝中之單多晶層。在此情形中，RFP渠溝中之底部多晶層及上部多晶層兩者皆電短接至源極金屬。另外，圖23中之裝置之RFP區中之***式多晶層可直接由圖24A及圖25A所展示之單RFP多晶層來替換。端視P屏蔽區(或隔離帶)之摻雜濃度，在極輕濃度下，該P屏蔽帶可係一"Π"區(一極輕摻雜P區)或一"v"區(一極輕摻雜n區)，如圖24B、24C、25B、及25C中所示。
圖28係一繪示用於製造根據本發明一項實施例之一MOSFET之一製作製程之流程圖。該製作製程包含使一N-磊晶層生長302在一N+基板上。該製作製程亦包含局域地增加304該N-磊晶層內之摻雜濃度。局域地增加304該N-磊晶層內之摻雜濃度包含毯覆植入磷。可以一零度之傾斜角度或可以某一其他傾斜角度來毯覆植入磷。局域地增加304該N-磊晶層內之摻雜濃度亦包含阻止磷摻雜劑進入一邊緣終止區域及/或一閘極匯流排區域(包含將氧化物留在一邊緣終止區域或一閘極匯流排區域處)。
用於製造一MOSFET之製作製程亦包含在該N-磊晶層內側形成306一摻雜增強N層，包含在氧氣氛中使用一高溫熱製程使該磷摻雜劑退火及散佈。用於製造一MOSFET之製作製程亦包含使渠溝之渠溝表面平滑308且降低在矽渠溝蝕刻期間所引發之渠溝表面之粗糙度，包含氧化渠溝側壁、移除310犧牲氧化物層及使墊氧化物沿渠溝側壁再生長312。
用於製造一MOSFET之製作製程亦包含用高密度氧化物填充314該渠溝、平坦化氧化物表面316(包含回蝕氧化物)、形成一底部氧化物層(BOX)(包含使用一作用遮罩進一步向下蝕刻至渠溝中)及使用一BOX遮罩保護318一作用閘極渠溝及一邊緣終止。用於製造一MOSFET之製作製程亦包含透過一凹陷式場板渠溝底部將硼(B11)植入320至一N-磊晶層中(包含以一傾斜角度沿凹陷式場板側壁引入硼)、完全蝕刻掉322一凹陷式場板渠溝內側之BOX(包含移除氧化物)、視需要驅使324硼以將一P層形成至該N-磊晶層中(包含在一高溫下退火)及使一閘極氧化物沿一渠溝側壁生長324。
對於一樣本40V實施例，較佳參數如下。然而，必須理解，將針對不同運作電壓來縮放此等參數，且當然其亦可適於與諸多其他製程一起使用。在此樣本實施例中，渠溝係0.3微米寬、約1.0微米深，且係以一微米之間距來佈局。(單元間距係兩微米，此乃因存在兩種類型之渠溝。)在此樣本實施例中，起始材料係0.35 ohm-cm n-on-n+epi，約5.5微米厚。舉例而言，以3E12/cm2 (亦即，3×1012 cm-2 )用磷來執行一毯覆n-增強植入。然後蝕刻該等渠溝。在一犧牲氧化及渠溝填充(較佳使用一沈積氧化物加上氧化)之後，較佳執行一回蝕以將該等渠溝清除至約其一半深度。然後圖案化光阻劑以曝露RFP渠溝而非閘極渠溝，且自該等RFP渠溝移除氧化物堵塞物。然後執行一P型植入以形成P隔離區；在此實例中，係兩種硼植入物之一組合，一種為在30keV下以2.5E12/cm2 之硼植入物加上另一種為在120keV下以2E12之硼植入物。此將在該等RFP渠溝下面產生一約0.7微米深度之經逆摻雜或經補償隔離區114。然後，剩餘之製程步驟以傳統方式繼續，其中形成閘極、本體、源極、觸點等。
如以上所提及，將閘極連接至汲極之局域地增強之n摻雜在以上闡述之各種實施例中減小導通電阻。然而，由所添加之隔離區提供之經改良之關斷狀態行為使得此增強之n摻雜成為可能。
在替代實施例中，該隔離區之深度可係(舉例而言)自0.25微米至2.5微米，且針對不同於40V之運作電壓而相應地加以縮放。類似地，隔離植入在替代實施例中可使用在20-320keV下之自2E12cm-2 至1E13之一劑量，或者甚至更高或更低之劑量及/或能量，且允許縮放。
應瞭解，前述內容僅係對本發明之某些具體圖解闡釋性及實例性實施例之一闡述，且不應認為係對歸屬於本發明範疇內之全部實施例之闡述。
根據各種實施例，提供有：一種半導體裝置結構，其包括：一閘極，其定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過與該渠溝毗鄰之半導體材料之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；及一第二傳導性類型之擴散物，其至少部分地位於該等相應之第二渠溝下方。
根據各種實施例，提供有：一種半導體裝置結構，其包括：一半導體層；一閘極，其在該半導體層內定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過該層中接近該渠溝之第二傳導性類型部分之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；一第二傳導性類型之擴散組分，其至少部分地位於該等相應之第二渠溝下方；藉此該等擴散組分減少在關斷狀態中該層之該第二傳導性類型部分之耗乏。
根據各種實施例，提供有：一種半導體裝置結構，其包括：一半導體層；一閘極，其在該半導體層內定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過該層中接近該渠溝之第二傳導性類型部分之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；一第二傳導性類型之一第一額外擴散組分，其至少部分地位於該等相應之第二渠溝下方；及該第一傳導性類型之一第二額外擴散組分，其至少部分地位於該層之該等第二傳導性類型部分內；藉此該第一額外擴散組分減少在關斷狀態中該層之該等第二傳導性類型部分之耗乏；且藉此該第二額外擴散組分減少該裝置在導通狀態中之導通電阻。
根據各種實施例，提供有：一種經改良之RFP電晶體結構，其具有：(a)低總導通電阻，(b)降低之(本體二極體之)少數載流子注入效率(c)經改良之(本體二極體之)反向恢復，(c)較低之反向恢復電荷，(d)軟恢復特性，(e)由於可靠之邊緣終止，不減小崩潰電壓或使裝置邊緣接面終止區之終止效率降級，該經改良之結構包括：一RFP電晶體結構，其包含由一或多個凹陷式場板渠溝鄰接之至少一個或多個閘極渠溝；及該等凹陷式場板渠溝下方之相應深補償帶。
根據各種實施例，提供有：一種運作一半導體裝置結構之方法，其包括：使用定位於一第一渠溝中以提供至少導通及關斷狀態之一閘電極來控制第一與第二源/汲電極之間穿過半導體材料中之一通道位置之傳導；及使用以下兩者來避免該通道位置之擊穿：一或多個凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料，該等凹陷式場板定位於相應之第二渠溝中；及一第二傳導性類型之一或多個擴散組分，其至少部分地位於該等相應之第二渠溝下方；藉此該等擴散組分減在少關斷狀態中之耗乏散佈。
根據各種實施例，提供有：一種用於製造一MOSFET之製作製程，其以任一次序包括以下動作：a)提供一n型半導體層；b)在該層中形成一p型本體；c)在該層中形成一由該本體隔離之n型源極；d)在該層中形成一絕緣閘極渠溝及在該閘極渠溝中形成一閘電極；該閘電極以電容方式耦合至該本體之至少一部分；e)在該層中形成一第二絕緣渠溝、在該渠溝下面提供一額外受體摻雜劑劑量且在該第二渠溝中形成一凹陷式場板電極；及f)在該本體之該部分中提供一額外施體摻雜劑原子劑量，藉此減小導通電阻。
根據各種實施例，提供有：經改良之高可靠性功率RFP結構以及製作及運作製程。該結構包含在RFP渠溝下方之複數個局域化摻雜劑集中帶，該複數個局域化摻雜劑集中帶浮動或延伸且與MOSFET之本體層合併或透過垂直摻雜區之一區與源極層連接。此局域摻雜劑帶降低該裝置之本體二極體之少數載流子注入效率且改動本體二極體反向恢復期間之電場分佈。
修改及變化
如熟習此項技術者將認識到，可在一極大應用範圍中修改且變動本申請案中所闡述之創新性概念，且因此，申請專利之標的物之範疇不受所給出之具體實例性教示內容中之任一者之限定。本發明意欲涵蓋歸屬於隨附申請專利範圍之精神及寬廣範疇內之所有此等替代方案、修改及變化。
可以各種佈局製作該裝置，包含"條紋"及"蜂巢式"佈局。可垂直地、准垂直地以及橫向地組態源極、本體及汲極區之層。可對磊晶漂移區進行均勻地或非均勻地摻雜。儘管以上所闡述之實施例包含一生長於一基板上之磊晶層，但在某些應用中可省略該磊晶層。可針對各種應用來組合及再組合不同實施例之各種特徵。
舉例而言，既不必在垂直方向上亦不必在橫向方向上對溝道與汲極之間的區進行均勻地摻雜。由所揭示之創新在漂移或散佈區摻雜方面提供之改良可與各種各樣的其他裝置改良及特徵組合。
舉另一例而言，RFP及閘極渠溝不必具有相同寬度。
該設計可應用於IGBT或其他包含雙極傳導之裝置。可用摻雜劑來修改該閘極渠溝之底部；該設計亦可在源極結構處及在汲極結構處變化；且可使用替代本體結構；可首先製作接觸渠溝，然後切割閘極渠溝並構造源極及汲極結構。
當然，矽中之n型摻雜劑可係磷、銻或砷或此等材料之組合。適當之施體摻雜劑可用於其他半導體材料中。
由於可將所揭示之製程縮放為其他運作電壓，因此預計對尺寸及摻雜劑之可預測縮放允許相同增效。舉例而言，在一200V實施例中，發明者預期渠溝深度將係稍深(舉例而言，1.5至2.5微米)，且補償植入能量及劑量將係大約相同。當然，磊晶層摻雜將係明顯地減少，且磊晶層厚度更大，熟習此項技術者將易於理解。n增強摻雜(較佳自終止對其加以阻斷)在驅入之後可具有一分佈，該分佈到達補償植入之上邊界，但較佳未到達補償植入之下邊界。
以下申請案可含有額外資訊及替代修改：2008年4月29日申請之代理檔案第MXP-14P號、序列號第61/125,892號；2008年6月2日申請且標題為"Edge Termination for Devices Containing Permanent Charge"之代理檔案第MXP-15P號、序列號第61/058,069號；2008年6月11日申請且標題為"MOSFET Switch"之代理檔案第MXP-16P號、序列號第61/060,488號；2008年6月20日申請且標題為"MOSFET Switch"之代理檔案第MXP-17P號、序列號第61/074,162號；2008年6月30日申請且標題為"Trench-Gate Power Device"之代理檔案第MXP-18P號、序列號第61/076,767號；2008年7月15日申請且標題為"A MOSFET Switch"之代理檔案第MXP-19P號、序列號第61/080,702號；2008年7月30日申請且標題為"Lateral Devices Containing Permanent Charge"之代理檔案第MXP-20P號、序列號第61/084,639號；2008年7月30日申請且標題為"Silicon on Insulator Devices Containing Permanent Charge"之代理檔案第MXP-21P號、序列號第61/084,642號；2008年2月11日申請且標題為"Use of Permanent Charge in Trench Sidewalls to Fabricate Un-Gated Current Sources,Gate Current Sources,and Schottky Diodes"之代理檔案第MXP-22P號、序列號第61/027,699號；2008年2月14日申請且標題為"Trench MOSFET Structure and Fabrication Technique that Uses Implantation Through the Trench Sidewall to Form the Active Body Region and the Source Region"之代理檔案第MXP-23P號、序列號第61/028,790號；2008年2月14日申請且標題為"Techniques for Introducing and Adjusting the Dopant Distribution in a Trench MOSFET to Obtain Improved Device Characteristics"之代理檔案第MXP-24P號、序列號第61/028,783號；2008年8月25日申請且標題為"Devices Containing Permanent Charge"之代理檔案第MXP-25P號、序列號第61/091,442號；2008年12月1日申請且標題為"An Improved Power MOSFET and Its Edge Termination"之代理檔案第MXP-27P號、序列號第61/118,664號；及2008年12月16日申請且標題為"A Power MOSFET Transistor"之代理檔案第MXP-28P號、序列號第61/122,794號。
本申請案中之闡述不應理解為暗指任一特定元件、步驟或功能係一必須包含於申請專利範圍範疇中之必要元件：申請專利之標的物之範疇僅由所允許之申請專利範圍界定。此外，此等申請專利範圍並非意欲援引35USC部分112之第六段，除非確確字"用於…之構件"後跟一分詞。
所申請之申請專利範圍意欲盡可能地全面，且不意欲讓與、貢獻或放棄標的物。
100．．．半導體裝置結構
102．．．閘極
104．．．第一渠溝(閘極渠溝)
106．．．源極
108．．．半導體材料
110．．．凹陷式場板
112．．．第二渠溝(RFP渠溝)
114．．．深補償帶(隔離區)
118．．．汲極
116．．．深P本體部位
201．．．基板
203．．．N-磊晶層
205．．．氧化物層
207．．．渠溝遮罩
209．．．渠溝
211．．．磷離子
213．．．摻雜增強N層
217．．．氧化物
219．．．氧化物表面
221．．．底部氧化物層(BOX)
222．．．渠溝
223．．．作用遮罩
225．．．作用閘極渠溝
229．．．硼-11離子
231．．．RFP渠溝底部
233．．．BOX光阻劑
235．．．閘極氧化物
237．．．P層或隔離帶
250．．．"v"區
260．．．"π"區
圖1係帶有一具有一厚底部氧化物結構之渠溝閘極之一先前技術MOSFET之一剖視圖。
圖2係具有一***式多晶閘極結構之一先前技術MOSFET之一剖視圖。
圖3係具有與閘極渠溝平行之RFP之一先前技術MOSFET之一剖視圖。
圖4(a)係具有一浮動深補償帶之一含有RFP之MOSFET結構之一剖視圖。
圖4(b)係具有一延伸至且連接至源電極之深補償帶之一含有RFP之MOSFET結構之一剖視圖。
圖4(c)係具有一延伸至P本體區之深補償帶之一含有RFP之MOSFET結構之一剖視圖。
圖5顯示先前RFP-MOSFET結構與一含有一深補償帶之MOSFET之間的一兩維電壓模擬比較。
圖6至圖18顯示用於製造圖4(a)中所繪示之樣本結構之一樣本製程中之連續步驟。
圖19A係具有一深補償帶及一延伸超出P-N接面且至N漂移區中之P+植入區之一含有RFP之MOSFET結構之一剖視圖。
圖19B係具有一深補償帶(其係一輕摻雜p區)及一延伸超出P-N接面且至N漂移區中之P+植入區之一含有RFP之MOSFET結構之一剖視圖。
圖19C係具有一深補償帶(其係一輕摻雜n區)及一延伸超出P-N接面且至N漂移區中之P+植入區之一含有RFP之MOSFET結構之一剖視圖。
圖20係具有一深補償帶及一延伸超出P-N接面且至N漂移區及完全凹陷下去之N++源極區中之P+植入區之一含有RFP之MOSFET結構之一剖視圖。
圖21至圖23顯示一用於製作以在RFP渠溝中具有***式多晶層結構之***式多晶閘極結構來實施之圖4(a)結構之一實施例之製程。
圖24A、圖24B、圖24C、圖25A、圖25B及圖25C顯示具有一深補償帶(圖24B及圖25B中之輕摻雜p區以及圖24C及圖25C中之輕摻雜n區)、以在RFP渠溝中具有一單個多晶層結構之***式多晶閘極結構來實施之含有RFP之MOSFET結構之剖視圖。
圖26顯示圖4(a)之一實施例之一俯視圖，其中RFP區在水平方向上係一連續條帶。
圖27顯示圖4(a)之一實施例之一俯視圖，其中RFP區在水平方向上被分為數個行。
圖28顯示用於一樣本製作製程之一示意性流程圖。
100．．．半導體裝置結構
102．．．閘極
104．．．第一渠溝(閘極渠溝)
106．．．源極
108．．．半導體材料
110．．．凹陷式場板
112．．．第二渠溝(RFP渠溝)
114．．．深補償帶(隔離區)
118．．．汲極

Claims (33)

  1. 一種半導體裝置結構，其包括：一閘極，其定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過與該渠溝毗鄰之半導體材料之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；及一第二傳導性類型之若干擴散物，其至少部分地位於該等相應之第二渠溝下方。
  2. 如請求項1之半導體裝置結構，其中該裝置進一步包含自一源極層延伸至該等擴散物中之至少一者之第二傳導性類型之一摻雜劑濃度區層。
  3. 如請求項1之半導體裝置結構，其中該等擴散物中之至少一者垂直延伸且與第二傳導性類型之一本體層合併。
  4. 如請求項1之半導體裝置結構，其中該裝置進一步包含自一源極層延伸至該等擴散物中之至少一者之第二傳導性類型之一摻雜劑濃度區層，且該等擴散物中之至少一者垂直延伸且與第二傳導性類型之一本體層合併。
  5. 如請求項1之半導體裝置結構，其中該閘極具有一***式多晶組態。
  6. 如請求項1之半導體裝置結構，其中該等凹陷式場板中之至少一者具有一***式多晶組態。
  7. 如請求項1之半導體裝置結構，其中該閘極及該等凹陷式場板中之至少一者兩者皆具有一***式多晶組態。
  8. 如請求項1之半導體裝置結構，其中該第一傳導性類型係n型。
  9. 如請求項1之半導體裝置結構，其中該閘極以電容方式被耦合以控制至該第一傳導性類型之一汲極擴散物之垂直傳導。
  10. 一種半導體裝置結構，其包括：一半導體層；一閘極，其在該半導體層內定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過該層中接近該渠溝之第二傳導性類型部分之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；一第二傳導性類型之若干擴散組分，其至少部分地位於該等相應之第二渠溝下方；藉此該等擴散組分減少在關斷狀態中該層之該第二傳導性類型部分之耗乏。
  11. 如請求項10之半導體裝置結構，其中該閘極具有一***式多晶組態。
  12. 如請求項10之半導體裝置結構，其中該等凹陷式場板中之至少一者具有一***式多晶組態。
  13. 如請求項10之半導體裝置結構，其中該閘極及該等凹陷式場板中之至少一者兩者皆具有一***式多晶組態。
  14. 如請求項10之半導體裝置結構，其中該等擴散組分具有一足夠高之濃度以對該半導體層進行局域逆摻雜且藉此在該第二渠溝下面產生一第二傳導性類型區。
  15. 如請求項10之半導體裝置結構，其中該半導體層係一磊晶層。
  16. 一種半導體裝置結構，其包括：一半導體層；一閘極，其在該半導體層內定位於一第一渠溝中，且以電容方式被耦合以控制自一第一傳導性類型源極穿過該層中接近該渠溝之第二傳導性類型部分之垂直傳導；若干凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中；一第二傳導性類型之一第一額外擴散組分，其至少部分地位於該等相應之第二渠溝下方；及該第一傳導性類型之一第二額外擴散組分，其至少部分地位於該層之該等第二傳導性類型部分內；藉此該第一額外擴散組分減少在關斷狀態中該層之該等第二傳導性類型部分之耗乏；且藉此該第二額外擴散組分減少該裝置在導通狀態中之導通電阻。
  17. 如請求項16之半導體裝置結構，其中該閘極具有一***式多晶組態。
  18. 如請求項16之半導體裝置結構，其中該等凹陷式場板中之至少一者具有一***式多晶組態。
  19. 如請求項16之半導體裝置結構，其中該閘極及該等凹陷式場板中之至少一者兩者皆具有一***式多晶組態。
  20. 如請求項16之半導體裝置結構，其中該等擴散組分具有一足夠高之濃度以對該半導體層進行局域逆摻雜且藉此在該第二渠溝下方產生一第二傳導性類型區。
  21. 如請求項16之半導體裝置結構，其中該半導體層係一磊晶層。
  22. 一種經改良之凹陷式場板(RFP)電晶體結構，其具有：(a)低總導通電阻，(b)降低之(本體二極體之)少數載流子注入效率，(c)經改良之(本體二極體之)反向恢復，(c)較低之反向恢復電荷，(d)軟恢復特性，(e)由於可靠之邊緣終止，不減小崩潰電壓或使裝置邊緣接面終止區之終止效率降級，該經改良之結構包括：一RFP電晶體結構，其包含由一或多個凹陷式場板渠溝鄰接之至少一個或多個閘極渠溝；及若干相應之深補償帶，其位於該等凹陷式場板渠溝下方。
  23. 如請求項16之經改良之RFP電晶體結構，其中該凹陷式場板區下方之埋置式隔離帶係浮動的。
  24. 如請求項16之經改良之RFP電晶體結構，其中該凹陷式場板區下方之該埋置式隔離帶係由一深P區連接至源電極。
  25. 如請求項16之經改良之RFP電晶體結構，其中該凹陷式場板區下方之該埋置式隔離帶垂直延伸且與P本體區合併。
  26. 一種用於運作一半導體裝置結構之方法，其包括：使用一定位於一第一渠溝中以提供至少導通及關斷狀態之閘電極來控制第一與第二源/汲電極之間穿過半導體材料中之一通道位置之傳導；及使用以下兩者來避免對該通道位置之擊穿一或多個凹陷式場板，其經定位而接近且以電容方式耦合至該半導體材料；該等凹陷式場板定位於相應之第二渠溝中，及一第二傳導性類型之一或多個擴散組分，其至少部分地位於該等相應之第二渠溝下方；藉此該等擴散組分減少在該關斷狀態中之耗乏散佈。
  27. 如請求項26之方法，其中該裝置進一步包含自一源極層延伸至該等擴散組分中之至少一個位置之一第二傳導性類型之摻雜劑濃度區層。
  28. 如請求項26之方法，其中該閘極具有一***式多晶組態。
  29. 如請求項26之方法，其中該等凹陷式場板中之至少一者具有一***式多晶組態。
  30. 如請求項26之方法，其中該閘極及該等凹陷式場板中之至少一者兩者皆具有一***式多晶組態。
  31. 如請求項26之方法，其中該第一傳導性類型係n型。
  32. 如請求項26之方法，其中該閘極以電容方式被耦合以控制至該第一傳導性類型之一汲極擴散物之垂直傳導。
  33. 一種用於製造一MOSFET之製作製程，其以任一次序包括以下動作：a)提供一n型半導體層；b)在該層中形成一p型本體；c)在該層中形成一由該本體隔離之n型源極；d)在該層中形成一絕緣閘極渠溝且在該閘極渠溝中形成一閘電極；該閘電極以電容方式耦合至該本體之至少一部分；e)在該層中形成一第二絕緣渠溝、在該渠溝下面提供一額外受體摻雜劑劑量且在該第二渠溝中形成一凹陷式場板電極；及f)在該本體之該部分中提供一額外施體摻雜劑原子劑量，藉此減小導通電阻。
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