CN113690303A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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CN113690303A
CN113690303A CN202010418849.6A CN202010418849A CN113690303A CN 113690303 A CN113690303 A CN 113690303A CN 202010418849 A CN202010418849 A CN 202010418849A CN 113690303 A CN113690303 A CN 113690303A
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region
trench
groove
electrode
conductive structure
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肖魁
方冬
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China Resources Microelectronics Chongqing Ltd
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China Resources Microelectronics Chongqing Ltd
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Priority to PCT/CN2020/140321 priority patent/WO2021232807A1/zh
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Abstract

本申请涉及一种半导体器件及其制备方法，器件包括：漂移区和形成于漂移区上表层的体区；形成于体区上表层第一掺杂区；第一沟槽，自体区内延伸至漂移区内，第二沟槽，贯穿第一掺杂区、体区并延伸至漂移区内，第一沟槽的侧壁和第二沟槽的侧壁均形成有氧化层，第一沟槽内填充有第一导电结构，第二沟槽填充有第二导电结构；第一扩展区，包围第一沟槽的底部；栅极与第二导电结构接触；第一电极延伸至第一沟槽顶部并与第一掺杂区、体区和第一沟槽接触；第二电极与半导体衬底接触。漂移区、第一掺杂区、具有第一导电类型，体区、第一扩展区具有第二导电类型。通过第一沟槽和扩展区的作用，可增强漂移区的耗尽，提高器件耐压。

Description

半导体器件及其制备方法
技术领域
本申请涉及半导体领域，尤其涉及一种半导体器件及其制备方法。
背景技术
在MOS(Metal Oxide Semiconductor，金属氧化物半导体)管中以及具有MOS管结构的其他半导体器件中，由于器件导通时会存在一定的导通电阻，导通电阻越大，器件功耗越大，因此，需要尽量减小导通电阻。目前，通常采用沟槽栅结构，通过形成沟槽栅结构，使导通沟道由横向变成纵向，大大提高了导通沟道的密度，降低导通电阻。然而，在沟槽栅结构的基础上，若想进一步降低导通电阻，需提高漂移区的掺杂浓度，而提高掺杂浓度又会减弱器件的耐压能力，因此，受耐压能力的限制，使得进一步降低器件的导通电阻变得困难。
发明内容
基于此，有必要针对目前半导体器件难以进一步降低导通电阻的技术问题，提出一种新的半导体器件及其制备方法。
一种半导体器件，包括：
漂移区，具有第一导电类型，形成于半导体衬底上；
体区，具有第二导电类型，形成于所述漂移区的上表层；
第一掺杂区，具有第一导电类型，形成于所述体区的上表层；
第一沟槽和第二沟槽，所述第一沟槽自所述体区内部延伸至所述漂移区内，所述第二沟槽贯穿所述第一掺杂区、所述体区并延伸至所述漂移区内，所述第一沟槽的侧壁和所述第二沟槽的侧壁均形成有氧化层，且所述第一沟槽内填充有第一导电结构，所述第二沟槽填充有第二导电结构；
第一扩展区，具有第二导电类型，形成于所述第一沟槽下方的漂移区内并包围所述第一沟槽的底部；
栅极，与所述第二导电结构接触；
第一电极，延伸至所述第一沟槽顶部并与所述第一掺杂区、所述体区和所述第一沟槽接触；
第二电极，与所述半导体衬底接触。
在其中一个实施例中，所述第一沟槽的底部深度大于所述第二沟槽的底部深度。
在其中一个实施例中，所述第一沟槽底部未形成有所述氧化层，所述第一扩展区与所述第一导电结构接触。
在其中一个实施例中，所述第一沟槽的内壁均形成有所述氧化层，所述第一扩展区与所述第一导电结构隔离。
在其中一个实施例中，所述第一导电结构与所述第一电极接触。
在其中一个实施例中，所述第一沟槽内还形成有位于所述第一导电结构顶部的隔离层，所述第一导电结构通过所述隔离层与所述第一电极隔离。
在其中一个实施例中，还包括：
重掺杂区，具有第二导电类型，形成于所述体区内并与所述第二沟槽间隔设置，且所述重掺杂区的掺杂浓度高于所述体区的掺杂浓度，所述第一沟槽贯穿所述重掺杂区并延伸至所述漂移区内，所述第一电极的底部未被所述第一沟槽覆盖的部分被所述重掺杂区包围。
在其中一个实施例中，所述半导体器件为VDMOS场效应管，所述第一掺杂区为源区，所述半导体衬底具有第一导电类型，所述第一电极为源极，所述第二电极为漏极。
在其中一个实施例中，所述半导体器件为IGBT器件，所述第一掺杂区为发射区，所述半导体衬底具有第二导电类型，所述半导体衬底与所述漂移区之间还形成有缓冲区，所述缓冲区具有第一导电类型，所述第一电极为发射极，所述第二电极为集电极。
一种半导体器件制备方法，包括：
在半导体衬底上形成漂移区，所述漂移区具有第一导电类型；
在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层；
通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区；
向所述第一沟槽内填充第一导电结构；
在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构；
对所述漂移区的上表层进行第二导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的第一掺杂区；
削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成与所述第二导电结构接触的栅极，形成与所述半导体衬底接触的第二电极。
上述半导体器件及其制备方法，在元胞区开设第二沟槽且在第二沟槽内形成第二导电结构和氧化层，其中，第二导电结构与栅极连接，从而构成沟槽栅结构，通过该沟槽栅结构形成纵向导通沟道，提高导通沟道的密度，降低导通电阻。
同时，在元胞区还开设第一沟槽，一方面，第一沟槽内形成有第一导电结构和氧化层，第一导电结构能够从第一电极获取一定的电势，与氧化层形成内场板，调节漂移区电场，增强漂移区的耗尽。另一方面，在元胞区域还形成有第一扩展区包围沟槽底部，且第一扩展区的导电类型与漂移区的导电类型相反，第一扩展区也可以增强漂移区的耗尽。在本申请中，通过在传统沟槽栅结构的基础上，形成内场板和第一扩展区，在内场板和第一扩展区的共同作用下，增大漂移区的耗尽，提高漂移区的击穿电压。因此，在具有同等击穿电压的条件下，本申请中半导体器件的漂移区可以提高掺杂浓度，从而降低导通电阻，即，在具有同等击穿电压的条件下，本申请中的半导体器件具有更低的导通电阻。
附图说明
图1为第一实施例中半导体器件的剖面图；
图2为第二实施例中半导体器件的剖面图；
图3为第三实施例中半导体器件的剖面图；
图4为第四实施例中半导体器件的剖面图；
图5为一实施例中半导体器件制备方法的步骤流程图；
图6a～6h为一实施例中半导体器件制备方法相关步骤对应的结构剖视图。
标号说明
100漂移区；110体区；111第一掺杂区；112重掺杂区；121第一沟槽；122第二沟槽；131氧化层；131a隔离氧化层；131b栅氧层；141第一导电结构；142第二导电结构；150第一扩展区；160隔离层；200介质层；310第一电极；320第二电极；410半导体衬底。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示，半导体器件包括漂移区100，漂移区100形成于半导体衬底410的正面，漂移区100具体可以是半导体衬底410通过外延生长而成。漂移区100上表层形成有体区110，体区110上表层形成第一掺杂区111。第一掺杂区111与第一电极310连接，半导体衬底410与第二电极320连接，第一电极310和第二电极320通过体区110和漂移区100形成电流通路。
半导体器件内还具有第一沟槽121和第二沟槽122，其中，第一沟槽121自体区110内延伸至漂移区100内，即第一沟槽121的顶端和底端分别在体区110内和漂移区100内；第二沟槽122贯穿源区111、体区110并延伸至漂移区100内。第一沟槽121的侧壁和第二沟槽122的侧壁均形成有氧化层131，其中，第一沟槽121内形成的氧化层为隔离氧化层131a，第二沟槽122内形成的氧化层为栅氧层131b。同时，第一沟槽121内还填充有第一导电结构141，第二沟槽122内还填充有第二导电结构142。进一步的，栅极(图中未示出)与第二导电结构142接触；第一电极310延伸至第一沟槽121的顶部并分别与第一掺杂区111、体区110和第一沟槽接触，使第一掺杂区111、体区110和第一沟槽121内的第一导电结构141均能获取第一电极310的电位。具体的，第一导电结构141和第二导电结构142可为多晶硅。
漂移区100内还形成有第一扩展区150，第一扩展区150位于第一沟槽121的下方并包围第一沟槽121的底部。
其中，漂移区100、第一掺杂区111具有第一导电类型，体区110、第一扩展区150具有第二导电类型。具体的，第一导电类型为P型，第二导电类型为N型，或，第一导电类型为N型，第二导电类型为P型。
上述半导体器件，第二沟槽122内的第二导电结构142和栅氧层131b形成沟槽栅结构并与与栅极(图中未示出)连接，通过沟槽栅结构在体区110内形成纵向导电沟道。进一步的，在第二沟槽122内，可仅填入第二导电结构142，形成如图1所示的普通沟槽栅结构。
同时，一方面，第一沟槽121内的第一导电结构141能够从第一电极310处获取电势，使得第一沟槽121内的第一导电结构141和隔离氧化层131a构成内场板，以调节漂移区110的电场，增强漂移区110的耗尽。另一方面，第一沟槽121底部的第一扩展区150与漂移区110的导电类型相反，也能进一步增强漂移区110的耗尽。在本申请中，通过增加内场板和第一扩展区，能够有效提高器件耐压，因此，在具有同等击穿电压的条件下，本申请中半导体器件的漂移区可以提高掺杂浓度，从而降低导通电阻。且，传统的沟槽栅结构中，击穿位置为沟槽栅与漂移区的交界面，在本申请中，由于在漂移区100内设置有第一沟槽121和包围第一沟槽121底部的第一扩展区150，使得击穿位置从沟槽栅处转移至第一扩展区150与漂移区100的交界面，从而使击穿更加稳定。
在一实施例中，也可在第二沟槽122底部的漂移区100内形成包围第二沟槽122的第二扩展区，第二扩展区与第一扩展区的性质及作用相同，可进一步增强漂移区的耗尽。
在一实施例中，第一沟槽121和第二沟槽122的底部深度不同，具体的，第一沟槽121的底部深度大于第二沟槽122的底部深度，这样漂移区100的三维耗尽最优。
在一实施例中，上述半导体器件还包括有重掺杂区112，重掺杂区112形成于体区110内并与第二沟槽122间隔设置，重掺杂区112具有第二导电类型，即重掺杂区112与体区110的导电类型相同，但重掺杂区112的掺杂浓度高于体区110的掺杂浓度。此时，第一沟槽121依次贯穿重掺杂区112、体区110并延伸至漂移区100内，第一电极310的底部一部分与第一沟槽121接触并被第一沟槽121覆盖，另一部分则并被重掺杂区112包围，以降低第一电极310与体区110的接触电阻。需要说明的是，此处的第一电极310包括位于图示顶层的金属层以及自金属层延伸至第一沟槽121处的第一引出结构。
在一实施例中，在第一掺杂区111和第二沟槽122上覆盖有介质层200，第一电极310的第一引出结构贯穿介质层200、第一掺杂区111并延伸至第一沟槽121顶部与第一沟槽121接触。
具体的，在一实施例中，第一沟槽121底部未形成有氧化层，使得第一扩展区150与第一导电结构141直接接触。在另一实施例中，第一沟槽121的内壁均形成有氧化层131，使得第一扩展区150与第一导电结构141隔离。
具体的，在一实施例中，第一电极310延伸至第一沟槽121顶部并与第一沟槽121接触，第一导电结构141填满第一沟槽121并直接与第一电极310接触以获取电势。在另一实施例中，第一导电结构141未填满第一沟槽121，第一导电结构顶部还设有隔离层，第一导电结构141通过隔离层与第一电极310隔离，且，隔离层的厚度需满足第一导电结构141能从第一电极310处获取感应电势。
为详细介绍本申请中的半导体结构，以下以四个实施例进一步说明。
第一实施例：
图1是第一实施例中半导体器件的结构示意图。
继续参见图1，第一电极310延伸至第一沟槽121顶部并与第一沟槽121内的第一导电结构141直接接触，使得第一导电结构141直接获取第一电极310的电势，第一导电结构141和氧化层131相当于内场板，调节漂移区100的电场，增强漂移区100的耗尽。
具体的，在第一沟槽内121内，氧化层131仅形成于第一沟槽121的侧壁，即第一沟槽121的侧壁形成有氧化层131，但第一沟槽121的底部未形成氧化层，第一扩展区150与第一沟槽121内的第一导电结构141接触，第一导电结构141从第一电极310处获取电势后，第一扩展区150也可通过第一导电结构141获取电势，增强第一扩展区150对漂移区100的耗尽。
在本实施例中，第一导电结构141与第一电极310直接接触、第一扩展区150与第一导电结构141直接接触，使得第一扩展区150和第一导电结构141均均有较强的电势，可以提高对漂移区100的耗尽。
第二实施例：
图2是第二实施例中半导体器件的结构示意图。
第二实施例与第一实施例的区别仅在于，第二实施例中氧化层131的覆盖区域不同。在本实施例中，第一沟槽121的内壁上均形成有氧化层131，即第一沟槽121的侧壁和底部均形成有氧化层131，第一扩展区150与第一导电结构141隔离，由此切断第一电极310、第一导电结构141和第一扩展区150的漏电通道，减小漏电。
第三实施例：
图3是第三实施例中半导体器件的结构示意图。
第三实施例与第一实施例的区别仅在于，第三实施例中第一导电结构141与第一电极310之间还形成有隔离层160，第一导电结构141通过隔离层160与第一电极310隔离，且隔离层160的厚度需满足第一导电结构141可从第一电极310处获取感应电势。具体的，隔离层160可为氧化硅。
在本实施例中，第一电极310与第一导电结构141之间设有隔离层160，利用隔离层160切断第一电极310、第一导电结构141和第一扩展区150的漏电通道，减小漏电。同时，第一导电结构141可以获取第一电极310的感应电势，因此，在本实施例中，第一导电结构141和第一扩展区150具有一定的感应电势，可增强漂移区100的耗尽。
第四实施例：
图4是第四实施例中半导体器件的结构示意图。
第四实施例与第一实施例的区别仅在于，第四实施例中第一沟槽121内的第一导电结构141与第一电极310之间设有隔离层160，且第一沟槽121内壁均形成有氧化层131，使第一扩展区150与第一导电结构141隔离。
在本实施例中，第一电极310通过隔离结构160与第一导电结构141隔离，且第一导电结构141通过氧化层131与第一扩展区150隔离，进一步切断第一电极310、第一导电结构141和氧化层131的漏电通道，避免漏电，此时，第一导电结构141可获取第一电极310的感应电势，而第一扩展区150无电势。
在一具体的实施例中，上述半导体器件可为VDMOS(Vertical Double diffusionMetal Oxide Semiconductor，垂直型双扩散金属氧化物半导体)场效应管。其中，第一掺杂区111为源区，半导体衬底410具有第一导电类型。第一电极310为源极，第二电极320为漏极。
在另一具体的实施例中，上述半导体器件也可为IGBT((Insulated Gate BipolarTransistor，绝缘栅双极型晶体管)。其中，第一掺杂区111为发射区，半导体衬底410具有第二导电类型，半导体衬底410与漂移区100之间还形成有缓冲区，缓冲区具有第一导电类型。第一电极310为发射极，第二电极320为集电极。
本申请还涉及一种半导体器件的制备方法，如图5所示，该制备方法包括以下步骤：
步骤S510：在半导体衬底上形成漂移区，所述漂移区具有第一导电类型。
如图6a所示，提供半导体衬底410，半导体衬底上410形成有漂移区100。
步骤S520：在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层。
如图6b所示，在漂移区100上开设第一沟槽121，第一沟槽121的内壁形成氧化层131。具体的，可通过热氧化工艺在第一沟槽121的内壁形成氧化层131。
步骤S530：通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区。
如图6c所示，通过第一沟槽121向漂移区100注入第二导电类型掺杂离子，形成与第一沟槽121底部接触的第一扩展区150。
步骤S540：向所述第一沟槽内填充第一导电结构。
如图6e所示，向第一沟槽121内填充第一导电结构141。具体的，第一导电结构141可为多晶硅。
在一实施例中，在步骤S530和步骤S540之间，还包括：
刻蚀所述第一沟槽底部的氧化层，暴露出所述第一扩展区。
如图6d所示，通过干法刻蚀第一沟槽121底部的氧化层131，形成暴露出第一扩展区150的开口。此时，在步骤S540中，填充第一导电结构141后，第一导电结构141与第一扩展区150接触。
步骤S550：在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构。
如图6f所示，继续在漂移区100上开设第二沟槽122，第一沟槽121和第二沟槽122相互隔离。在第二沟槽122的内壁形成氧化层131，并在第二沟槽122内填充第二导电结构142。此时，第一沟槽121内形成的氧化层为隔离氧化层131a，第二沟槽122内形成的氧化层为栅氧层131b。具体的，第二导电结构142可为多晶硅。
步骤S560：对所述漂移区的上表层进行第二导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成于所述第一沟槽和所述第二沟槽接触的第一掺杂区。
如图6g所示，在形成第一沟槽121和第二沟槽122之后，继续形成体区和第一掺杂区。具体的，对漂移区100的上表层进行第二导电类型掺杂，形成与第一沟槽121和第二沟槽122接触的体区110。继续对体区110的上表层进行第一导电类型掺杂，形成与第一沟槽121和第二沟槽122接触的第一掺杂区111。
在一实施例中，形成体区110的工艺具体为高温推阱工艺，其中，高温推阱的温度和时间可根据体区的掺杂深度和掺杂浓度调节，具体的，高温推阱的温度范围可控制在900℃～1200℃之间，高温推阱的时间范围可控制在10min～180min之间。在上述高温推阱形成体区110的同时，第一扩展区150的掺杂离子向外扩散，使得第一扩展区150向外扩展，从而增大第一扩展区150的体积。
步骤S570：削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成于所述第二导电结构接触的栅极，形成与所述半导体衬底接触的第二电极。
如图6h所示，削减第一沟槽内的第一导电结构141和氧化层131的高度，使第一沟槽121及其内部填充结构整体顶面高度下降至体区内，并在第一沟槽121的上方贯穿第一掺杂区111并延伸至体区110已与第一沟槽接触的第一引出结构，因此，第一引出结构还与第一掺杂区111和体区110接触。第一引出结构的顶部与第一金属层连接，第一引出结构与第一金属层共同作为第一电极310。具体的，第一引出结构在图6h截面中的宽度大于第一沟槽121的宽度，且第一引出结构覆盖第一沟槽121。
同时，还形成与第二导电结构142接触的栅极。
当上述半导体器件为VDMOS场效应管时，第一掺杂区111为源区，半导体衬底410具有第一导电类型。当上述半导体器件为IGBT时，第一掺杂区111为发射区，半导体衬底410具有第二导电类型，半导体衬底410与漂移区100之间还形成有第一导电类型缓冲区。
以上实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种半导体器件，其特征在于，包括：
漂移区，具有第一导电类型，形成于半导体衬底上；
体区，具有第二导电类型，形成于所述漂移区的上表层；
第一掺杂区，具有第一导电类型，形成于所述体区的上表层；
第一沟槽和第二沟槽，所述第一沟槽自所述体区内部延伸至所述漂移区内，所述第二沟槽贯穿所述第一掺杂区、所述体区并延伸至所述漂移区内，所述第一沟槽的侧壁和所述第二沟槽的侧壁均形成有氧化层，且所述第一沟槽内填充有第一导电结构，所述第二沟槽填充有第二导电结构；
第一扩展区，具有第二导电类型，形成于所述第一沟槽下方的漂移区内并包围所述第一沟槽的底部；
栅极，与所述第二导电结构接触；
第一电极，延伸至所述第一沟槽顶部并与所述第一掺杂区、所述体区和所述第一沟槽接触；
第二电极，与所述半导体衬底接触。
2.如权利要求1所述的半导体器件，其特征在于，所述第一沟槽的底部深度大于所述第二沟槽的底部深度。
3.如权利要求1所述的半导体器件，其特征在于，所述第一沟槽底部未形成有所述氧化层，所述第一扩展区与所述第一导电结构接触。
4.如权利要求1所述的半导体器件，其特征在于，所述第一沟槽的内壁均形成有所述氧化层，所述第一扩展区与所述第一导电结构隔离。
5.如权利要求1至4任一项所述的半导体器件，其特征在于，所述第一导电结构与所述第一电极接触。
6.如权利要求1至4任一项所述的半导体器件，其特征在于，所述第一沟槽内还形成有位于所述第一导电结构顶部的隔离层，所述第一导电结构通过所述隔离层与所述第一电极隔离。
7.如权利要求1所述的半导体器件，其特征在于，还包括：
重掺杂区，具有第二导电类型，形成于所述体区内并与所述第二沟槽间隔设置，且所述重掺杂区的掺杂浓度高于所述体区的掺杂浓度，所述第一沟槽自所述重掺杂区内部延伸至所述漂移区内，所述第一电极的底部未被所述第一沟槽覆盖的部分被所述重掺杂区包围。
8.如权利要求1所述的半导体器件，其特征在于，所述半导体器件为VDMOS场效应管，所述第一掺杂区为源区，所述半导体衬底具有第一导电类型，所述第一电极为源极，所述第二电极为漏极。
9.如权利要求1所述的半导体器件，其特征在于，所述半导体器件为IGBT器件，所述第一掺杂区为发射区，所述半导体衬底具有第二导电类型，所述半导体衬底与所述漂移区之间还形成有缓冲区，所述缓冲区具有第一导电类型，所述第一电极为发射极，所述第二电极为集电极。
10.一种半导体器件制备方法，其特征在于，包括：
在半导体衬底上形成漂移区，所述漂移区具有第一导电类型；
在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层；
通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区；
向所述第一沟槽内填充第一导电结构；
在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构；
对所述漂移区的上表层进行第二导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的第一掺杂区；
削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成与所述第二导电结构接触的栅极，形成与所述半导体衬底接触的第二电极。
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