TWI582930B - 積體電路裝置及封裝組件 - Google Patents

積體電路裝置及封裝組件 Download PDF

Info

Publication number
TWI582930B
TWI582930B TW099125728A TW99125728A TWI582930B TW I582930 B TWI582930 B TW I582930B TW 099125728 A TW099125728 A TW 099125728A TW 99125728 A TW99125728 A TW 99125728A TW I582930 B TWI582930 B TW I582930B
Authority
TW
Taiwan
Prior art keywords
layer
bump
copper
bottom metal
metal layer
Prior art date
Application number
TW099125728A
Other languages
English (en)
Other versions
TW201133744A (en
Inventor
黃見翎
吳逸文
王俊傑
劉重希
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201133744A publication Critical patent/TW201133744A/zh
Application granted granted Critical
Publication of TWI582930B publication Critical patent/TWI582930B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03901—Methods of manufacturing bonding areas involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H01L2224/11614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11827—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13561—On the entire surface of the core, i.e. integral coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13609—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/1369—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81413—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81416—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20641—Length ranges larger or equal to 100 microns less than 200 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20642—Length ranges larger or equal to 200 microns less than 300 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

積體電路裝置及封裝組件
本發明係關於積體電路製作，且特別是關於積體電路裝置內所應用之凸塊結構(bump structure)。
當今之積體電路係由如電晶體或電容之數百萬個裝置所形成。此些裝置之間起初為相分隔的，然而之後將相互地經過內部連結而形成功能性電路。內連結構通常包括如金屬導線(連接線)之橫向內連情形與如介層物(via)與接觸物(contact)等之垂直內連情形。此些內連情形逐漸地決定了當今積體電路之表現與密度的極限。於內連結構之頂部上，形成有銲墊(bond pad)並露出各晶片之表面。可透過銲墊以形成連結晶片與基板或另一晶片之電性連接情形。銲墊可用於打線接合(wire bonding)或覆晶接合(flip-chip bonding)等接合情形。
覆晶封裝技術利用了凸塊(bump)以建立介於一晶片之輸出/輸入銲墊(I/O pads)與基板或封裝物之導線架之間的電性連接關係。結構上而言，凸塊實際上包括了凸塊其本身與位於凸塊與輸出/輸入銲墊之間的所謂之凸塊底金屬層(under bump metallurgy，UBM)。凸塊底金屬層通常包括一黏著層、一阻障層與一濕潤層，並按照上述順序而設置於輸出/輸入銲墊之上。基於凸塊其本身之使用材料，則可細分為銲錫凸塊(solder bumps)、金凸塊(gold bumps)、銅柱凸塊(copper pillar bump)以及採用混合材料之凸塊。近年來已發展出了銅柱凸塊技術。於取代錫球凸塊的使用情形中，電子元件係藉由一銅柱凸塊而連結於一基板，如此可於最小之凸塊橋接可能情形下以達成了更細之間距，進而降低了電路之負載電容(capacitance load)，並使得電子元件可於更高頻率下操作。
銅柱凸塊覆晶組件(Cu pillar bump flip-chip assembly)具有下述優點：(1)較佳熱/電性表現、(2)高電流承載能力、(3)對於電致變遷之較佳阻抗能力，因而具有較長的凸塊壽命、(4)可最小化模塑孔洞(molding voids)，即於銅柱凸塊之間可形成有較為一致之空隙。此外，藉由使用銅柱而達成銲錫分佈的控制便可應用較為便宜之基板與消除無鉛淚珠設計。然而，銅於製造過程中具有氧化之傾向。經氧化之銅柱將導致了電子構件與基板之間的不良附著情形。如此之不良附著情形可基於高漏電流情形而導致了嚴重的可靠性問題。經氧化之銅柱亦可導致了沿著底膠與銅柱間介面之底膠破裂情形。此些破裂可能遷移至下方的低介電常數介電層或至用於連結銅柱與基板間之凸塊處。因此，便需要一側壁保護層以避免銅的氧化，但是用於製造銅柱側壁物之習知方法受到高製造成本與介面剝落等問題的困擾。目前，係採用浸潤式錫製程以於銅柱側壁上形成一錫層，然而上述技術仍存在有關於製造成本、錫與底膠間之附著情形等問題，以及於側壁上之銲錫的濕潤問題，上述問題為新世代晶片中用於精密間距封裝技術的一大挑戰。
有鑑於此，本發明提供了一種積體電路裝置及封裝組件，以解決上述問題。
依據一實施例，本發明提供了一種積體電路裝置，包括：一半導體基板；一第一凸塊底金屬層，形成於該半導體基板之上；一第二凸塊底金屬層，形成於該第一凸塊底金屬層之上，具有一側面；一導電柱，形成於該第二凸塊底金屬層之上，具有一側面與一頂面；以及一保護結構，形成於該導電柱之該側面與該第二凸塊底金屬層之該側面之上；其中該保護結構係由一非金屬材料所形成，而該導電柱係由一含銅層所形成。
依據另一實施例，本發明提供了一種積體電路裝置，包括：一半導體基板；一凸塊結構，形成於該半導體基板之上；以及一非金屬之保護結構，覆蓋至少該凸塊結構之側壁之一部；其中該凸塊結構包括形成於該半導體基板之上之一凸塊底金屬層以及形成於該凸塊底金屬層之上之一銅柱。
依據又一實施例，本發明提供了一種封裝組件，包括：一第一基板；一凸塊結構，形成於該第一基板之上，其中該凸塊結構包括形成於該第一基板之上之一凸塊底金屬層以及形成於該凸塊底金屬層之上之一銅柱；一非金屬之保護結構，覆蓋至少該凸塊結構之側壁之一部；一第二基板；以及一接合銲錫層，形成於該第二基板與該凸塊結構之間。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
本發明提供了數個適用於銅柱凸塊技術之側壁保護製程之實施例，側壁保護製程中係於銅柱凸塊之側壁上形成包括至少如一介電材料層、一聚合物材料層或上述材料膜層之組合等多個非金屬材料膜層其中之一之保護結構。於下文中所採用之”銅柱凸塊(Cu pillar bump)”係指一凸塊結構包括由銅或銅合金所形成之一導電柱(一柱子或一支撐座)。銅柱凸塊可直接應用於覆晶組件之一半導體晶片之導電接墊或一重分佈層之上或應用於其他之相似應用中。
於下文中藉由對應之圖式以詳細解說本發明之範例與實施例。可能的話，於圖式與描述中採用了相同之標號以代表相同或類似之構件。於圖式中，基於清楚與方便之目的，實施例之形狀或厚度可誇大顯示。再者，圖式中各元件之部分將分別描述說明，值得注意的是，圖中未特別繪示或描述之元件可能具有不同之形態。另外，當一膜層係為位於另一膜層之上或位於一基板之上時，此膜層可能直接地位於其他膜層之上或基板之上，或者是其間從在有中間之膜層。於下文中關於”某一實施例”或”一實施例”內之參考內容表示了相關於包括至少一實施例之此實施例之一特定構件、結構或特性。因此，於不同處之”於某一實施例中”或”於一實施例中”等描述並非相關於相同之實施例。再者，於一或多個實施例中之此些特定構件、結構或特徵可依照特定形態而結合。可以理解的是下述圖式中並非依照實際比例繪製，而此些圖式僅用於配合解說之用。
在此，第1A-1F圖為一系列剖面圖，顯示了於一實施例中之一銅柱凸塊製程內的一半導體裝置之一部的製作。
請參照第1A圖，於一半導體積體電路製作中採用一半導體基板10以用於凸塊製作，而積體電路可形成於半導體基板10之內及/或其上。此半導體基板係定義為包括半導體材料之任何結構，例如是包括塊狀矽、半導體晶圓、絕緣層上覆矽基板或一矽鍺基板，但並不以上述實施情形為限。亦可採用如包括III族、IV族、與V族元素之其他半導體材料。半導體基板10可更包括如淺溝槽隔離(STI)構件或局部矽氧化(LOCOS)構件之數個隔離構件(未顯示)。此些隔離構件可定義與分隔多個微電子元件(未顯示)。可形成於半導體基板10上之此些微電子元件的範例包括電晶體(例如金氧半導體電晶體(MOS)、互補型金氧半導體電晶體(CMOS)、雙極電晶體(BJT))、高壓電晶體、高頻電晶體、p通道及/或n通道場效應電晶體(PFETs或NFETs等)、電阻、二極體、電容、電感、熔絲及其他適當之元件。可施行包括沈積、蝕刻、佈值、微影、回火及其他適當製程之多個製程以形成上述多種微電子元件。此些微電子元件係經過內部連結以形成如邏輯裝置、記憶體裝置(如靜態隨機存取記憶體，SRAM)、射頻(RF)裝置、輸入/輸出裝置、晶片上系統裝置、上述裝置之結合及其他適當形態之裝置之一積體電路裝置。
半導體基板10可更包括位於積體電路之上的層間介電層與金屬化結構。位於金屬化結構內之層間介電層包括低介電常數介電材料、未摻雜矽玻璃(USG)、氮化矽、氮氧化矽或其他常用之材料。低介電材料之介電常數(k值)可少於約3.9或少於約2.8。金屬化結構內之金屬導線可由銅或銅合金所形成。金屬化膜層的形成細節為熟悉此技藝者可以理解的。一銲墊區域(未顯示)係為形成於最頂層之層間介電層內之一頂金屬化膜層，其為導電通道的一部且具有經過如化學機械研磨之一平坦化程序處理之一露出表面，如果需要的話。用於銲墊區域之適當材料可包括如銅、鋁、鋁銅、銅合金或其他之導電材料，但並以上述材料限制其實施情形。銲墊區域係用於連結位於各別晶片內之積體電路至外部構件之一接合程序。
半導體基板10更包括形成於銲墊區域之上並露出銲墊區域之一部之一保護層(未顯示)，以使得後續銅柱凸塊製程得以施行。此保護層係由擇自如未摻雜矽玻璃(USG)、氮化矽、氮氧化矽、氧化矽、及上述材料之組合之一非有機材料(non-organic material)。或者，保護層可由一聚合物層所形成，例如環氧樹脂、聚亞醯胺、苯環丁烯(BCB)、聚苯噁唑(PBO)及相似物，雖然其亦可使用其他之相對柔軟、更為有機之介電材料。
請參照第1圖，接著於基板10之上形成包括一第一凸塊底金屬層14與一第二凸塊底金屬層16之一凸塊底金屬層12。舉例來說，凸塊底金屬層12係形成於銲墊區域之露出部之上並延伸至保護層之一部上。第一凸塊底金屬層14，其亦稱為擴散阻障層或一黏著層，其係由鈦、鉭、氮化鈦、氮化鉭或相似物所形成，並可藉由如物理氣相沈積或濺鍍法等方法所形成。第一凸塊底金屬層14沈積至介於約500-2000埃之一厚度，例如為約1000埃之一厚度。形成於第一凸塊底金屬層14上之第二凸塊底金屬層16係為銅晶種層，其可藉由物理氣相沈積或濺鍍法等方式形成。第二凸塊底金屬層16可由包括銀、鉻、鎳、錫、金及其組合之銅合金所形成。第二凸塊底金屬層16沈積至約介於500-10000埃之一厚度，例如為約5000埃之厚度。於一實施例中，凸塊底金屬層12包括由鈦所形成之一第一凸塊底金屬層14以及由銅所形成之一第二凸塊底金屬層16。
接著，於凸塊底金屬層12之上形成一罩幕層18，並經過圖案化以於其內形成並露出凸塊底金屬層12之一部之一開口19，以用於銅柱凸塊的形成。罩幕層18可為一乾膜層或一阻劑膜層。開口19接著部份或完全地為具有錫濕潤性之一導電材料所填入。於一實施例中，於開口19內形成一銅層20以接觸下方之凸塊底金屬層12。於本發明中，”銅層”之描述係泛指大體包括純元素銅、包含不可避免之雜質之銅層及包括如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯之微量元素之銅合金之一膜層。其形成方法可包括濺鍍、印刷、電鍍、無電電鍍或常用之化學氣相沈積方法。舉例來說，可施行電化學電鍍以形成銅層20。於一實施例中，銅層20之厚度可大於25微米，於下文中銅層20亦可稱呼為具有一頂面20a與一側面20b之一銅柱20。於另一實例例中，銅層之厚度則大於40微米。舉例來說，銅層之厚度約為40-50微米，或約為40-70微米，雖然其厚度可能更厚或更薄。
請參照第1B圖，接著移除罩幕層18，以露出銅柱20之頂面20a與側面20b以及銅柱20以外之第二凸塊底金屬層16之一部。當罩幕層18為乾膜層時，可採用鹼性溶液以移除之。而當罩幕層18為阻劑膜層所形成時，則可採用丙酮、N-甲基砒喀烷酮(NMP)、二甲基亞砜(DMSO)、乙氧基乙醇(aminoethoxy ethanol)或相似物以移除之。接著如第1C圖所示，第二凸塊底金屬層16之露出部份經過蝕刻後以露出其下方位於銅凸塊20以外之第一凸塊底金屬層14之一部14a。於一實施例中，移除第二凸塊底金屬層16之步驟係為一乾蝕刻或一濕蝕刻。舉例來說，可使用採用氨基酸之一等向性濕蝕刻(通常稱之為快速蝕刻由於其處理時間較短)。因此，於銅柱20之下方，經圖案化之第二凸塊底金屬層16”便具有側面16b。此外，位於銅柱20之外，則露出了第一凸塊底金屬層14之一部14a。
請參照第1D圖，藉由如一坦覆地沈積之程序以形成一保護層22於如第1C圖所示結構之上。較精確的說，係沈積一保護層22以覆蓋銅柱20之底面20a與側面20b、經圖案化之第二凸塊底金屬層16”之側面16b以及第一凸塊底金屬層14之露出部14a。保護層22係為一非金屬材料層，例如為一介電材料層、一聚合物層，或上述膜層之組合。保護層22可為單一材料層或一多重膜層結構。保護層22之厚度約為500-1000埃。於一實施例中，保護層22係為由氮化矽、氧化矽、氮氧化矽、碳化矽、氧化矽與氮化矽之交錯膜層或上述材料之結合之所形成之一介電材料層，其可藉由下述之多個沈積技術中之任一方法所形成，包括熱氧化法、低壓化學氣相沈積(LPCVD)、大氣化學氣相沈積法(APCVD)或電漿加強型化學氣相沈積(PECVD)。於一實施例中，保護層22係為一聚合物材料層且由一聚合物所形成，例如環氧樹脂、聚亞醯胺、苯環丁烯(BCB)、聚苯噁唑(PBO)及相似物，雖然其亦可使用其他之相對柔軟、更為有機之介電材料。聚合物材料層係為柔軟的，因此具有降低位於基板之各別部份之本身應力的功能。此外，聚合物層可輕易地形成約為數十微米之一厚度。
接著，請參照第1E圖，經過蝕刻保護層22之數個部份後，留下沿著側面20b與16b與露出部14a之部份，藉以形成一側壁間隔物22a，其亦稱為一側壁保護結構22a，其中覆蓋銅柱20之頂面20a之保護層22於此步驟中被蝕刻移除。隨著微影與罩幕製程與乾蝕刻製程的演進，如反應性離子蝕刻與其他電漿蝕刻製程可完成了側壁間隔物22a的製作。
接著採用所形成之結構22a作為罩幕以蝕刻第一凸塊底金屬層14並露出下方之基板10。可使用如採用Cl2/BCl3作為蝕刻劑之標準反應離子蝕刻製程之一乾蝕刻製程，以形成一第一凸塊底金屬層14。因此，上述乾蝕刻製程圖案化了露出部14a之為側壁間隔物22a所覆蓋之一周圍表面14a”並露出了側面14b。由於周圍表面14a延伸至經圖案化之第二凸塊底金屬層16”之側面16b之外，故經圖案化之第一凸塊底金屬層14”之區域可大於經圖案化之第二凸塊底金屬層16”之區域。
所形成之凸塊結構24包括了銅柱20、位於銅柱20下方之經圖案化之第二凸塊底金屬層16”、位於經圖案化之第二凸塊底金屬層16”下方之經圖案化之第一凸塊底金屬層14”以及覆蓋側面20b與16b與周圍表面14a之側壁保護結構22a。半導體基板10接著經過切割後，利用錫球或銅凸塊而安裝於封裝基板或另一晶片上之一銲墊上而封裝至一封裝基板上或另一晶片之上。
第1F圖為一剖面圖，顯示了一實施例之一覆晶組件的剖面情形。如第1E圖所示結構經上下顛倒後使之底部黏著至另一基板100。基板100可為一封裝基板、電路板(如一印刷電路板)或其他之適當基板。凸塊結構24接觸了基板100之多個導電黏著點，例如為位於接觸銲墊及/或導電線路上之一接合銲錫層102，進而形成耦接了兩個基板10與100之一接合結構104。接合銲錫層102可為一共熔銲錫材料，其包括錫、鉛、銀、銅、鎳、鉍或其組合之合金。示範性之耦合製程包括一助熔劑應用、晶片擺置、融化錫球接點之迴銲與助熔劑殘留物的潔淨化。積體電路基板10、接合結構104與另一基板100可稱之為一封裝組件200，或於本實施例中稱之為一覆晶封裝組件。
本發明提供了一側壁保護結構，其由位於銅柱側壁上之一非金屬材料以保護銅柱側壁免於氧化並增加了銅柱側壁與一後續形成的底膠材料間的附著情形。相較於習知之浸入錫(immersion Sn)方法及接著採用之回火程序，此非金屬之側壁保護結構可調整基板之應力，並避免了於迴銲製程中沿著凸塊底金屬層之周圍之銅柱的銲錫濕潤情形。因此其適用於精細間距凸塊技術。
第2A-2D圖為一系列剖面圖，顯示了依據另一實施例之一銅柱凸塊製程內的一半導體裝置之一部的製作，其中將省略相同或相似如第1A-1F圖所示部份之描述。
請參照第2A圖，於位於銅柱20下方之經圖案化之第二凸塊底金屬層16”形成之後，於所形成結構之上形成一阻障層30。於一實施例中，阻障層30覆蓋了銅柱20之底面20a與側面20b以及經圖案化之第二凸塊底金屬層16”之側面16b。於其他實施例中，阻障層30覆蓋了至少銅柱20之頂面20、銅柱20之側面20b與經圖案化之第二凸塊底金屬層16”之側面之一。阻障層30係作為一擴散阻障層之用，以避免位於銅柱20內之銅擴散進入如銲錫之接合材料內，接合材料係用於接合半導體基板10與外部構件。阻障層30亦可稱為一保護層、一抗氧化層或一氧化阻擋層，以防止銅柱20之頂面20a與側面20b免於後續製程中的氧化。阻障層30可藉由選擇性之熱化學氣相沈積法而形成穿透空乏表面。阻障層30係為包括表列於週期表內之III族元素、IV族元素、V族元素或其組合之一含銅材料。於一實施例中，含銅材料層可包括如硼、鍺、矽、碳、氮、磷或其組合，但並不以上述材料為限。於部份實施例中，含銅材料層為一CuGeN膜層、一CuGe膜層、一CuSi膜層、一CuSiN膜層、一CuSiGeN膜層、一CuN膜層、一CuP膜層、一CuC膜層、一CuB膜層或上述膜層之組合，其可藉由採用含硼、鍺、矽、碳、氮、磷或其組合之氣體(例如B2H6、CH4、SiH4、GeH4、NH3、PH3)之一選擇性化學氣相沈積所形成。以形成一CuGeN膜層之一範例為例，於一GeH4之化學氣相沈積後施行一去氧化處理步驟(NH3處理)。一阻障層30可成為一擴散阻障層，以防止銅於後續接合程序中進入銲錫內，以使得IMC的形成可受到控制並變得較為薄化與均勻。阻障層30之厚度為薄的，由於其形成方式類似於於擴散製程。於一實施例中，阻障層30之厚度少於或等於約10奈米。
請參照第2B圖，接著形成保護層22於阻障層30與第一凸塊底金屬層14之露出部之上，例如是藉由一坦覆沈積所形成。保護層22係為非金屬之一材料層，例如一介電材料層、一聚合物材料層或上述膜層之組合。保護層22可為單一材料層或一多重膜層結構。於一實施例中，保護層22係為一聚合物材料層且由一聚合物所形成，例如環氧樹脂、聚亞醯胺、苯環丁烯(BCB)、聚苯噁唑(PBO)及相似物
接著，請參照第2C圖，蝕刻保護層22之特定部，以留下沿著側面20b與16b之部分並形成一側壁間隔物22a，亦可稱之為側壁保護結構22a，其中覆蓋銅柱20之頂面之保護層22於本步驟中被移除。於此步驟中，阻障層30仍殘留於銅柱20之頂面20a之上。接著採用所形成之結構22a作為罩幕而蝕刻第一凸塊底金屬層14，以露出下方之半導體基板10。所形成之凸塊結構32包括了銅柱20、位於銅柱20下方之經圖案化之第二凸塊底金屬層16”、位於經圖案化之第二凸塊底金屬層16”下方且具有延伸至側面16b以外之周圍表面14a之經圖案化之第一凸塊底金屬層14”、覆蓋側面20b與16b以及周圍表面14a之側壁保護結構22a，以及覆蓋了側壁保護結構22a與銅柱20之頂面20a之阻障層30。
請參照第2D圖，半導體基板10經上下顛倒後使之底部黏著至另一基板100。凸塊結構32接觸了基板100之多個導電黏著點，例如為位於接觸銲墊及/或導電線路上之一接合銲錫層102，進而形成耦接了兩個基板10與100之一接合結構104。接合銲錫層102可為一共熔銲錫材料，其包括錫、鉛、銀、銅、鎳、鉍或其組合之合金。積體電路基板10、接合結構104與另一基板100可稱之為一封裝組件200，或於本實施例中稱之為一覆晶封裝組件。
本發明提供了包括銅與鍺之一阻障層，其形成於一側壁保護結構與銅柱側壁之間，其可更避免銅柱側壁免於受到氧化並改進介於銅柱側壁與一後續形成之底膠材料間之的附著情形。如此避免了於迴銲製程中沿著凸塊底金屬層之周圍之銅柱的銲錫濕潤情形。此阻障層不至於對於片電阻值(Rs)造成太大影響。
第3A-3F圖為一系列剖面圖，顯示了依據另一實施例之一銅柱凸塊製程內的一半導體裝置之一部的製作，其中將省略相同或相似如第1A-1F圖所示部份之描述。
請參照第3A圖，於罩幕層18之開口19內形成銅層20之後，形成一上蓋層40於銅層20之頂面20a之上。上蓋層40可作為一阻障層，以防止銅柱內之銅免於擴散進入如銲錫合金之接合材料內，接合材料係用於接合基板10與外部構件。銅擴散的防止增加了封裝物的可靠度與接合強度。上蓋層40可包括鎳、錫、錫-鉛(SnPb)、金、銀、鈀、銦、鎳鈀金(NiPdAu)、鎳金(NiAu)、其他相似材料或合金並可藉由電鍍方法而形成。上蓋材料40具有約為1-10微米之一厚度。於部份實施例中，上蓋層40係為包括了一第一金屬膜層42與一第二金屬膜層44之一多重膜層結構。第一金屬膜層42可包括鎳、金、鈀、鎳基合金、金基合金、或鈀基合金。第二金屬膜層44可包括鎳、金、鈀、鎳基合金、金基合金、或鈀基合金。於一實施例中，第一金屬膜層42為一鎳層、而第二金屬膜層44可為一金層。第一金屬膜層42與第二金屬膜層44分別具有約為1-5微米之一厚度。
請參照第3B圖，接著移除罩幕層18，並露出上蓋層40之頂面40a與側面40b。如第3C圖所示，接著蝕刻第二凸塊底金屬層16之露出部，以露出下方位於銅柱20之外之第一凸塊底金屬層14。接著，如第3D圖所示，於得到結構之上形成保護層22，以覆蓋上蓋層40、銅柱20之側面20b、經圖案化之第二凸塊底金屬層16”之側面16b與第一凸塊底金屬層14之露出部。於施行微影與罩幕技術與乾蝕刻製程之後，以形成一側壁保護結構22a。因而露出了上蓋層40之頂面。接著採用所形成之結構22a作為罩幕層以蝕刻第一凸塊底金屬層14，進而露出下方之基板10。
如第3E圖，所形成之凸塊結構46包括了銅柱20、位於銅柱20之頂面20a上之上蓋層40、位於銅柱20之下方經圖案化之第二凸塊底金屬層16”、位於圖案化之第二凸塊底金屬層16”下方且具有延伸至第二凸塊底金屬層16”之側面16b以外之周圍表面14a之經圖案化之第一凸塊底金屬層14”、以及覆蓋側面40b、20b與16b與周圍表面14a”之側面保護結構22a。半導體基板10接著經過切割後，利用錫球或銅凸塊而安裝於封裝基板或另一晶片上之一銲墊上而封裝至一封裝基板上或另一晶片之上。
請參照第3F圖，半導體基板10經上下顛倒後使之底部黏著至另一基板100。凸塊結構46接觸了基板100之多個導電黏著點，例如為位於接觸銲墊及/或導電線路上之一接合銲錫層102，進而形成耦接了兩個基板10與100之一接合結構104。積體電路基板10、接合結構104與另一基板100可稱之為一封裝組件200，或於本實施例中稱之為一覆晶封裝組件。
第4A-4G圖為一系列剖面圖，顯示了依據另一實施例之一銅柱凸塊製程內的一半導體裝置之一部的製作，其中將省略相同或相似如第3A-3F圖所示部份之描述。
請參照第4A圖，於罩幕層18之開口19內形成銅層20之後，形成上蓋層40於銅層20之頂面20a之上，並接著形成一銲錫層50於上蓋層40之頂面40a之上。銲錫50可由Sn、SnAg、Sn-Pb、SnAgCu(具有少於0.3%重量百分比之Cu)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等材料，並藉由如電鍍程序所形成。於一實施例中，銲錫層50係為一無鉛銲錫層。對於一無鉛銲錫系統而言，銲錫層係為SnAg，其具有可控制低於3.0重量百分比之Ag含量。舉例來說，無鉛銲錫層為具有金含量控制至約為2.5重量百分比之SnAg層。
如第4B圖所示，接著移除罩幕層18，並露出銲錫層50之頂面50a與側面50b。上蓋層40之側面40b亦於此步驟中露出。如第4C圖所示，接著蝕刻第二凸塊底金屬層16之露出部，以露出下方之銅柱20以外之第一凸塊底金屬層14。接著，如第4D圖所示，形成保護層22於得到之結構上，以覆蓋銲錫層50、上蓋層40、銅柱20的側面20b、經圖案化之第二凸塊底金屬層16”之側面16b以及第一凸塊底金屬層14之露出部。於施行微影與罩幕技術及乾蝕刻製程之後，形成了如第4E圖所示側壁保護結構22a。因而露出銲錫層50之頂面50a。第一凸塊底金屬層14接著蝕刻採用所形成之結構22作為罩幕，露出下方基板10。
請參照第4F圖，針對銲錫層50施行一迴銲(reflowing)程序以形成經迴銲之銲錫層50”於上蓋層40之上。如此形成了一凸塊結構52，其包括了銅柱20、位於銅柱20上之上蓋層40、位於上蓋層40上之經迴銲之銲錫層50”、位於銅柱20之下之經圖案化之第二凸塊底金屬層16”、位於經圖案化之第二凸塊底金屬層16”且具有延伸至第二凸塊底金屬層16”之側面16b以外之周圍表面14a”之經圖案化之第一凸塊底金屬層14”、以及覆蓋了側面40b、20b、16b與周圍表面14a”之側壁保護結構22a。半導體基板10接著經過切割後，利用錫球或銅凸塊而安裝於封裝基板或另一晶片上之一銲墊上而封裝至一封裝基板上或另一晶片之上。
請參照第4G圖，半導體基板10經上下顛倒後使之底部黏著至另一基板100。凸塊結構52接觸了基板100之多個導電黏著點，例如為位於接觸銲墊及/或導電線路上之一接合銲錫層102，進而形成耦接了兩個基板10與100之一接合結構104。積體電路基板10、接合結構104與另一基板100可稱之為一封裝組件200，或於本實施例中稱之為一覆晶封裝組件。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．半導體基板
12．．．凸塊底金屬層
14．．．第一凸塊底金屬層
14a．．．第一凸塊底金屬層之一部
14”．．．經圖案化之第一凸塊底金屬層
14a”．．．周圍表面
16．．．第二凸塊底金屬層
16”．．．經圖案化之第二凸塊底金屬層
16b．．．圖案化之第二凸塊底金屬層之側面
18．．．罩幕層
19．．．開口
20．．．銅層/銅柱
20a．．．銅層/銅柱之頂面
20b．．．銅層/銅柱之側面
22．．．保護層
22a．．．側壁間隔物/側壁保護結構
24．．．凸塊結構
30．．．阻障層
32．．．凸塊結構
40．．．上蓋層
40a．．．上蓋層之頂面
40b．．．上蓋層之側面
42．．．第一金屬膜層
44．．．第二金屬膜層
46．．．凸塊結構
50．．．銲錫層
50a．．．銲錫層之頂面
50b．．．銲錫層之側面
52．．．凸塊結構
100．．．基板
102．．．接合銲錫層
104．．．接合結構
200．．．封裝組件
第1A-1F圖為一系列剖面圖，顯示了依據本發明一實施例之銅柱凸塊製程中之不同階段內之一半導體裝置之一部；
第2A-2D圖為一系列剖面圖，顯示了依據本發明另一實施例之銅柱凸塊製程中之不同階段內之一半導體裝置之一部；
第3A-3F圖為一系列剖面圖，顯示了依據本發明又一實施例之銅柱凸塊製程中之不同階段內之一半導體裝置之一部；以及
第4A-4G圖為一系列剖面圖，顯示了依據本發明另一實施例之之銅柱凸塊製程中之不同階段內之一半導體裝置之一部。
14”．．．經圖案化之第一凸塊底金屬層
14a”．．．周圍表面
16”．．．經圖案化之第二凸塊底金屬層
20．．．銅層/銅柱
22a．．．側壁間隔物/側壁保護結構
24．．．凸塊結構

Claims (10)

  1. 一種積體電路裝置，包括：一半導體基板；一第一凸塊底金屬層，形成於該半導體基板之上；一第二凸塊底金屬層，形成於該第一凸塊底金屬層之上，具有一側面；一導電柱，形成於該第二凸塊底金屬層之上，具有一側面與一頂面；以及一保護結構，形成於該導電柱之該側面與該第二凸塊底金屬層之該側面之上；其中該保護結構係由一非金屬材料所形成，而該導電柱係由一含銅層所形成。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該保護結構包括一介電層、一聚合物層、一氮化矽層、一聚亞醯胺層或上述膜層之組合。
  3. 如申請專利範圍第1項所述之積體電路裝置，其中該第一凸塊底金屬層包括未為該第二凸塊底金屬層所覆蓋之一周圍表面，其中該保護結構係形成於該第一凸塊底金屬層之該周圍表面之上。
  4. 如申請專利範圍第1項所述之積體電路裝置，更包括一阻障層形成於該導電柱與該保護結構之間，其中該阻障層係為包括鍺之一含銅材料層，其中該阻障層係形成於該導電柱之該頂面之上。
  5. 如申請專利範圍第1項所述之積體電路裝置，更包括一上蓋層，位於該導電柱之該頂面之上，其中該上蓋層包括位於該導電柱之上之一鎳層與位於該鎳層上之一金層，其中該保護結構覆蓋了至少該上蓋層之該側面的一部。
  6. 如申請專利範圍第1項所述之積體電路裝置，其中該第一凸塊底金屬膜層包括鈦，而該第二凸塊底金屬層包括銅。
  7. 一種積體電路裝置，包括：一半導體基板；一凸塊結構，形成於該半導體基板之上；以及一非金屬之保護結構，覆蓋至少該凸塊結構之側壁之一部；其中該凸塊結構包括形成於該半導體基板之上之一凸塊底金屬層以及形成於該凸塊底金屬層之上之一銅柱。
  8. 如申請專利範圍第7項所述之積體電路裝置，其中該非金屬之保護結構包括一氮化矽層、一聚合物層或上述膜層之組合。
  9. 如申請專利範圍第7項所述之積體電路裝置，更包括一阻障層，形成於該凸塊結構與該非金屬之保護結構之間，其中該阻障層包括銅與鍺。
  10. 一種封裝組件，包括：一第一基板；一凸塊結構，形成於該第一基板之上，其中該凸塊結構包括形成於該第一基板之上之一凸塊底金屬層以及形成於該凸塊底金屬層之上之一銅柱；一非金屬之保護結構，覆蓋至少該凸塊結構之側壁之一部，其中該非金屬之保護結構包括一氮化矽層、一聚合物層或上述膜層之組合；一第二基板；以及一接合銲錫層，形成於該第二基板與該凸塊結構之間。
TW099125728A 2010-03-24 2010-08-03 積體電路裝置及封裝組件 TWI582930B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/730,411 US8841766B2 (en) 2009-07-30 2010-03-24 Cu pillar bump with non-metal sidewall protection structure

Publications (2)

Publication Number Publication Date
TW201133744A TW201133744A (en) 2011-10-01
TWI582930B true TWI582930B (zh) 2017-05-11

Family

ID=44655434

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099125728A TWI582930B (zh) 2010-03-24 2010-08-03 積體電路裝置及封裝組件

Country Status (3)

Country Link
US (3) US8841766B2 (zh)
CN (2) CN105390473B (zh)
TW (1) TWI582930B (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8232193B2 (en) 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
JP5281122B2 (ja) * 2011-06-16 2013-09-04 株式会社フジクラ 接合方法、及び、製造方法
KR101310256B1 (ko) * 2011-06-28 2013-09-23 삼성전기주식회사 인쇄회로기판의 무전해 표면처리 도금층 및 이의 제조방법
KR20130007124A (ko) * 2011-06-29 2013-01-18 삼성전자주식회사 유기 보호막을 갖는 조인트 구조
US9484259B2 (en) * 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US8604867B2 (en) * 2011-11-28 2013-12-10 Qualcomm Incorporated Energy harvesting in integrated circuit packages
US8698308B2 (en) 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
CN103258809A (zh) * 2012-02-15 2013-08-21 稳懋半导体股份有限公司 三五族化合物半导体组件的铜金属连接线
US9159687B2 (en) 2012-07-31 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump for ball grid array
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
KR102060831B1 (ko) * 2013-02-27 2019-12-30 삼성전자주식회사 플립 칩 패키징 방법, 그리고 상기 플립 칩 패키징 방법에 적용되는 플럭스 헤드 및 그 제조 방법
CN104022090B (zh) * 2013-02-28 2018-01-23 日月光半导体制造股份有限公司 半导体接合结构及方法，以及半导体芯片
CN103915357B (zh) * 2014-04-16 2016-09-21 华进半导体封装先导技术研发中心有限公司 一种超细间距微凸点的制备方法
US9355980B2 (en) 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US9613921B2 (en) * 2013-10-18 2017-04-04 Globalfoundries Inc. Structure to prevent solder extrusion
US9735123B2 (en) * 2014-03-13 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and manufacturing method
US9779969B2 (en) * 2014-03-13 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method
US10083924B2 (en) * 2014-11-13 2018-09-25 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
JP6425532B2 (ja) 2014-12-17 2018-11-21 ルネサスエレクトロニクス株式会社 半導体装置
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US20170179058A1 (en) * 2015-12-16 2017-06-22 Lite-On Semiconductor Corporation Bump structure having first portion of copper and second portion of pure tin covering the first portion, and interconnect structure using the same
US9960137B1 (en) * 2016-11-01 2018-05-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for forming the same
US10593638B2 (en) * 2017-03-29 2020-03-17 Xilinx, Inc. Methods of interconnect for high density 2.5D and 3D integration
US10276528B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device and manufacturing method thereof
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
US10763234B2 (en) * 2018-10-16 2020-09-01 Advanced Semicomductor Engineering, Inc. Semiconductor device structure having semiconductor die bonded to redistribution layer via electrical pad with barrier layer
US10784222B2 (en) * 2018-10-31 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-bump sidewall protection
US11257752B2 (en) * 2018-12-13 2022-02-22 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor structure and method for fabricating the same
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
CN110164775B (zh) * 2019-06-04 2024-04-09 无锡中微高科电子有限公司 高功率mos芯片与控制芯片组合封装结构与封装方法
CN110504174A (zh) * 2019-07-25 2019-11-26 南通通富微电子有限公司 封装结构的形成方法
CN111128755B (zh) * 2019-12-30 2022-07-22 颀中科技（苏州）有限公司 封装结构及其成型方法
US11616007B2 (en) * 2020-10-08 2023-03-28 Advanced Semiconductor Engineering, Inc. Electronic package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094842A1 (en) * 1999-05-10 2004-05-20 Jimarez Miguel A. Flip chip C4 extension structure and process
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
TW200744142A (en) * 2006-05-22 2007-12-01 Taiwan Semiconductor Mfg Co Ltd Semiconductor device including electrically conductive bump and method of manufacturing the same
US20070284706A1 (en) * 2002-02-11 2007-12-13 Gabe Cherian No-wick(tm) 2 interconnections

Family Cites Families (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6701136A (zh) * 1967-01-25 1968-07-26
FI61588C (fi) * 1980-08-01 1982-08-10 Lohja Ab Oy Foerfarande foer utfoerande av elektriskt ledande genomfoeringar i tunnfilmer
US4720740A (en) * 1985-11-26 1988-01-19 Clements James R Electronic device including uniaxial conductive adhesive and method of making same
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4811082A (en) * 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
JP3022565B2 (ja) * 1988-09-13 2000-03-21 株式会社日立製作所 半導体装置
JPH02253628A (ja) * 1989-03-28 1990-10-12 Nec Corp 半導体装置の製造方法
US4990462A (en) * 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
JPH05211239A (ja) * 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
JP3078646B2 (ja) 1992-05-29 2000-08-21 株式会社東芝 インジウムバンプの製造方法
JP3057130B2 (ja) * 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
DE4314907C1 (de) * 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) * 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JP3296400B2 (ja) 1995-02-01 2002-06-24 東芝マイクロエレクトロニクス株式会社 半導体装置、その製造方法およびＣｕ製リード
US6464895B2 (en) 1995-03-24 2002-10-15 Rhodia Chimie Reagent and process which are useful for grafting a substituted difluoromethyl group onto a compound containing at least one electrophilic function
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6232563B1 (en) 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
JPH10132612A (ja) 1996-10-28 1998-05-22 Mitsutoyo Corp 光学式変位検出装置
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
KR100377033B1 (ko) * 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ｉｃ 및 그 제조방법
US5757881A (en) * 1997-01-06 1998-05-26 Siemens Business Communication Systems, Inc. Redundant field-defining arrays for a radiation system
JPH10330724A (ja) * 1997-05-30 1998-12-15 Hitachi Chem Co Ltd 耐熱接着剤、耐熱接着剤層付き半導体チップ、耐熱接着剤層付きリードフレーム、耐熱接着剤層付きフィルム及び半導体装置
US6037822A (en) * 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3654485B2 (ja) 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6291891B1 (en) * 1998-01-13 2001-09-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6015749A (en) * 1998-05-04 2000-01-18 Taiwan Semiconductor Manufacturing Company Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure
US6213376B1 (en) * 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
JP2000094181A (ja) 1998-09-24 2000-04-04 Sony Corp はんだ合金組成物
US6130162A (en) * 1999-01-04 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of preparing passivated copper line and device manufactured thereby
US6271059B1 (en) * 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6229216B1 (en) * 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
JP4131595B2 (ja) 1999-02-05 2008-08-13 三洋電機株式会社 半導体装置の製造方法
JP3667184B2 (ja) * 1999-02-26 2005-07-06 住友ベークライト株式会社 半導体装置
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6243272B1 (en) * 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
KR100313706B1 (ko) * 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6339029B1 (en) * 2000-01-19 2002-01-15 Taiwan Semiconductor Manufacturing Company Method to form copper interconnects
US6387793B1 (en) 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
US6592019B2 (en) * 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002050647A (ja) * 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
TW464927B (en) * 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
US6355501B1 (en) * 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6869831B2 (en) 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
EP1472730A4 (en) * 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6975016B2 (en) * 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US6805974B2 (en) * 2002-02-15 2004-10-19 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
DE10392377T5 (de) * 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
US6897532B1 (en) * 2002-04-15 2005-05-24 Cypress Semiconductor Corp. Magnetic tunneling junction configuration and a method for making the same
JP4034107B2 (ja) * 2002-04-17 2008-01-16 株式会社ルネサステクノロジ 半導体装置
CN1679154A (zh) * 2002-05-16 2005-10-05 新加坡国立大学 晶片级无电镀铜法和凸块制备方法,以及用于半导体晶片和微芯片的渡液
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
US20050012211A1 (en) * 2002-05-29 2005-01-20 Moriss Kung Under-bump metallugical structure
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) * 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7012333B2 (en) * 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same
US7271497B2 (en) 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) * 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) * 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US7078796B2 (en) * 2003-07-01 2006-07-18 Freescale Semiconductor, Inc. Corrosion-resistant copper bond pad and integrated device
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
WO2005008767A2 (en) 2003-07-16 2005-01-27 Koninklijke Philips Electronics N.V. Metal bump with an insulation for the side walls and method of fabricating a chip with such a metal bump
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
JP3794403B2 (ja) 2003-10-09 2006-07-05 セイコーエプソン株式会社 半導体装置
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP3981089B2 (ja) * 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
US7309904B2 (en) * 2004-03-24 2007-12-18 Yamaha Corporation Semiconductor device, magnetic sensor, and magnetic sensor unit
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) * 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) * 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060043603A1 (en) * 2004-08-31 2006-03-02 Lsi Logic Corporation Low temperature PB-free processing for semiconductor devices
US7262495B2 (en) * 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
TWI242867B (en) * 2004-11-03 2005-11-01 Advanced Semiconductor Eng The fabrication method of the wafer and the structure thereof
US7323406B2 (en) 2005-01-27 2008-01-29 Chartered Semiconductor Manufacturing Ltd. Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
US7348210B2 (en) * 2005-04-27 2008-03-25 International Business Machines Corporation Post bump passivation for soft error protection
US7391112B2 (en) 2005-06-01 2008-06-24 Intel Corporation Capping copper bumps
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) * 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7402515B2 (en) * 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US7224067B2 (en) * 2005-09-15 2007-05-29 Intel Corporation Intermetallic solder with low melting point
US7566650B2 (en) 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) * 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
JP4755486B2 (ja) 2005-11-17 2011-08-24 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
KR101424824B1 (ko) 2005-11-18 2014-08-01 레플리서러스 그룹 에스에이에스 다중 층 구조 형성 방법
TWI298204B (en) * 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) * 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
JP4768491B2 (ja) * 2006-03-30 2011-09-07 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US20070287279A1 (en) 2006-06-08 2007-12-13 Daubenspeck Timothy H Methods of forming solder connections and structure thereof
KR100762354B1 (ko) 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
US7700475B1 (en) * 2006-10-05 2010-04-20 Marvell International Ltd. Pillar structure on bump pad
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
TW200836275A (en) * 2007-02-16 2008-09-01 Chipmos Technologies Inc Packaging conductive structure and method for manufacturing the same
FR2914490B1 (fr) * 2007-03-26 2009-05-29 Commissariat Energie Atomique Procede de soudure de deux elements entre eux au moyen d'un materiau de brasure.
US7973418B2 (en) * 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US7576435B2 (en) * 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
TW200915511A (en) * 2007-06-15 2009-04-01 Rohm Co Ltd Semiconductor device
US7838424B2 (en) 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US8669658B2 (en) 2007-07-24 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Crosstalk-free WLCSP structure for high frequency application
SG149807A1 (en) * 2007-07-30 2009-02-27 Stats Chippac Ltd Semiconductor device and method of providing common voltage bus and wire bondable redistribution
US7759792B2 (en) * 2007-08-15 2010-07-20 Infineon Technologies Ag Integrated circuit including parylene material layer
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP4431606B2 (ja) 2007-10-05 2010-03-17 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造
JP2009094378A (ja) 2007-10-11 2009-04-30 Panasonic Corp 半導体装置及びその製造方法
US7713861B2 (en) 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들
US8039964B2 (en) 2008-02-27 2011-10-18 International Business Machines Corporation Fluorine depleted adhesion layer for metal interconnect structure
US7648899B1 (en) 2008-02-28 2010-01-19 Novellus Systems, Inc. Interfacial layers for electromigration resistance improvement in damascene interconnects
US20090233436A1 (en) * 2008-03-12 2009-09-17 Stats Chippac, Ltd. Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
CN101582386B (zh) * 2008-05-14 2011-08-03 俞宛伶 在半导体元件形成金属凸块与密封的方法
JP5801989B2 (ja) * 2008-08-20 2015-10-28 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
US7928534B2 (en) * 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8227926B2 (en) * 2009-10-23 2012-07-24 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US9082762B2 (en) * 2009-12-28 2015-07-14 International Business Machines Corporation Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
JP2012089772A (ja) * 2010-10-22 2012-05-10 Elpida Memory Inc 半導体装置の製造方法
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US9318429B2 (en) * 2014-03-31 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated structure in wafer level package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094842A1 (en) * 1999-05-10 2004-05-20 Jimarez Miguel A. Flip chip C4 extension structure and process
US20070284706A1 (en) * 2002-02-11 2007-12-13 Gabe Cherian No-wick(tm) 2 interconnections
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
TW200744142A (en) * 2006-05-22 2007-12-01 Taiwan Semiconductor Mfg Co Ltd Semiconductor device including electrically conductive bump and method of manufacturing the same

Also Published As

Publication number Publication date
US8841766B2 (en) 2014-09-23
US20110233761A1 (en) 2011-09-29
US11257714B2 (en) 2022-02-22
CN105390473B (zh) 2018-12-14
US9136167B2 (en) 2015-09-15
US20150325546A1 (en) 2015-11-12
CN102201375A (zh) 2011-09-28
TW201133744A (en) 2011-10-01
CN105390473A (zh) 2016-03-09
US20140363970A1 (en) 2014-12-11

Similar Documents

Publication Publication Date Title
TWI582930B (zh) 積體電路裝置及封裝組件
US9685372B2 (en) Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap
US9287171B2 (en) Method of making a conductive pillar bump with non-metal sidewall protection structure
US9627339B2 (en) Method of forming an integrated circuit device including a pillar capped by barrier layer
US10163837B2 (en) Cu pillar bump with L-shaped non-metal sidewall protection structure
US9711477B2 (en) Dummy flip chip bumps for reducing stress
TWI459523B (zh) 封裝裝置、積體電路元件及其製作方法
TWI411080B (zh) 半導體元件、封裝結構、及半導體元件的形成方法
KR101208758B1 (ko) 구리 필라 범프를 형성하는 메카니즘
TWI419279B (zh) 積體電路元件
TWI459524B (zh) 半導體裝置及其製造方法
TWI419285B (zh) 基板上的凸塊結構與其形成方法
US7176117B2 (en) Method for mounting passive components on wafer
US20190273054A1 (en) Substrate structure and method for fabricating the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees