TWI459523B - 封裝裝置、積體電路元件及其製作方法 - Google Patents

封裝裝置、積體電路元件及其製作方法 Download PDF

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Publication number
TWI459523B
TWI459523B TW100120497A TW100120497A TWI459523B TW I459523 B TWI459523 B TW I459523B TW 100120497 A TW100120497 A TW 100120497A TW 100120497 A TW100120497 A TW 100120497A TW I459523 B TWI459523 B TW I459523B
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Taiwan
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layer
metal
bump
solder
pillar
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TW100120497A
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English (en)
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TW201222752A (en
Inventor
Chien Ling Hwang
Zheng-Yi Lim
Chung Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201222752A publication Critical patent/TW201222752A/zh
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Description

封裝裝置、積體電路元件及其製作方法
本發明有關於積體電路製程，且特別是有關於積體電路元件中的銅柱凸塊結構。
覆晶封裝技術係利用凸塊電性連接晶片的輸入/輸出(Input/Output，I/O)接墊與封裝基板或導線架。在結構上，凸塊結構包含凸塊本身以及所謂的凸塊下金屬(under bump metallurgy，UBM)層，其中凸塊下金屬層位於凸塊與輸入/輸出接墊之間。凸塊下金屬層通常包括在輸入/輸出接墊上依序配置的一黏著層、一阻障層以及一潤濕層(wetting layer)。依據凸塊所使用的材料，可將凸塊分為焊料凸塊、金凸塊、銅柱凸塊、以及混合金屬凸塊。目前，銅內連線凸塊技術已被提出。電子元件以銅柱取代焊料凸塊連接至一基板。相較於焊料凸塊技術，銅柱凸塊技術可達到較小的間距(pitch)，且凸塊橋接(bridging)的可能性最低，並可減少電路的電容負載，且允許電子元件以較高的頻率運作。此方式仍需要焊料合金來覆蓋凸塊結構以及連接電子元件。
銅柱凸塊覆晶裝置具有下列優點：(1)較佳的熱/電性能，(2)較高的電流載流量(carrying capacity)，(3)電遷移的阻抗能力較佳，從而延長凸塊的使用壽命，(4)使封膠的孔洞最小化-使銅柱凸塊之間的間隔更加一致。再者，藉由使用銅柱控制的散錫能力(solder spreading)可不需使用無鉛的淚珠設計(lead-free teardrop design)因而可降低基板的製作成本。目前的製程是使用一具有開口的光阻層，並在光阻層的開口中形成一銅柱，該銅柱蓋有一金屬層蓋。然而，金屬層蓋的形成經常導致在光阻剝除製程之前及/或之後產生缺陷。另外，在製程中鋼容易被氧化。氧化的銅柱會導致電子元件與基板之間的黏著性變差。黏著性變差可能會導致高漏電流而有嚴重的可靠度問題。銅柱氧化亦可能會導致底膠沿著底膠與銅柱的界面裂開。裂縫可能會延伸至下方的低介電常數介電層或是延伸至用以接合銅柱與基板的焊料。
因此，需要側壁保護層以避免銅氧化，然而，習知的銅柱側壁製程的製程花費高且易有界面剝離(interface delamination)的問題。目前係利用浸錫製程將一錫層形成在銅柱側壁上，但仍有一些需要考慮的因素，如製作成本、浸錫層的厚度限制、錫與底膠之間的黏著性、以及焊料與側壁的的潤濕性的問題、焊料的過冷效應(under-cooling effect)的問題，前述問題對於新一代的晶片的小間距封裝技術會是一個挑戰。
本發明一實施例提供一種積體電路元件，包括：一半導體基板；一凸塊下金屬層，配置於半導體基板上；一導電柱，配置於凸塊下金屬層上；以及一鈷氧化物層，配置於導電柱的側壁表面上。
本發明另一實施例提供一種封裝裝置，包括：一第一基板，包括一凸塊結構；一第二基板，貼附至第一基板；以及一接合焊料層，位於第二基板與第一基板的凸塊結構之間；其中，凸塊結構包括一金屬柱以及一位於金屬柱的側壁表面上的鈷氧化物層。
本發明又一實施例提供一種積體電路元件的製作方法，包括：形成一金屬柱於一半導體基板上；形成一焊料層於金屬柱上；形成一金屬化層覆蓋金屬柱與焊料層，其中金屬化層的材質包括鈷元素；熱回流焊料層以形成一焊料凸塊，其中金屬化層的鈷元素會進入焊料凸塊中；以及氧化金屬化層以形成一金屬氧化物層於金屬柱的側壁表面上。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。
本發明為銅柱凸塊技術提供多個形成側壁保護層的製程的實施例。在整篇說明書中，『銅柱凸塊』一詞代表一凸塊結構，其包括一導電柱(一柱體或是一分隔物)包括銅或是銅合金。銅柱凸塊可直接配置在一半導體晶片上的一電接墊、一重佈線層上以形成一覆晶裝置、或是其他相似的應用。在下文中，會提出許多特定的細節以利於徹底地了解本發明。然而，本領域具有通常知識者當可了解無需這些特定的細節即可實施本發明。在一些例子中，並未詳加描述熟知的結構與製程以避免不必要的混淆本發明。全篇說明書中的『一實施例』代表實施例中描述的一特定的特徵、結構、或特性被包括在至少一實施例中。因此，在全篇說明書各處出現的『一實施例』不必然代表相同的實施例。再者，在一或多個實施例中，特定的特徵、結構、或特性可以任一種適合的方式結合。值得注意的是，下列圖式並未按照比例繪示，更確切地說，這些圖式僅用以介紹。
第1A圖至第1G圖繪示本發明一實施例之一半導體元件的局部在一銅柱凸塊結構製程的各步驟的剖面圖。
請參照第1A圖，一實施例之一用以製作凸塊的基板10可包括一用於半導體積體電路製程中的半導體基板，且積體電路可形成於其中及/或於其上。半導體基板是指任何含有半導體材料的結構，包括，但不限於，塊狀矽、半導體晶圓、絕緣層上矽基板、或是矽鍺基板。亦可使用其他的半導體材料，包括第三族、第四族、及/或第五族元素。基板10可更包括多個隔離結構(未繪示)，例如淺溝槽隔離(shallow trench isolation，STI)結構或局部矽氧化(local oxidation of silicon，LOCOS)結構。隔離結構可定義並隔離各種微電子元件(未繪示)。可以形成在基板10中的各種電子元件的例子包括電晶體，例如金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistors，MOSFET)、互補式金屬氧化物半導體(complementary metal oxide semiconductor，CMOS)電晶體、雙載子接面電晶體(bipolar junction transistors，BJT)、高電壓電晶體、高頻率電晶體、p型通道及/或n型通道場效電晶體(PFETs/NFETs)等；電阻；二極體；電容；電感；保險絲；及/或其他適合的元件。進行各種製程以形成各種微電子元件，包括沉積、蝕刻、植入(implantation)、微影、退火、及/或其他適合的製程。使微電子元件互相連接以形成積體電路元件，例如邏輯元件、記憶體元件(例如靜態隨機存取記憶體，SRAM)、射頻元件(RF device)、輸入/輸出(I/O)元件、系統晶片(system-on-chip，SoC)元件、前述之組合、及/或其他適合類型的元件。
基板10更包括積體電路上的層間介電層以及金屬化結構。金屬化結構中的層間介電層包括低介電常數材料、未摻雜的矽酸鹽玻璃、氮化矽、氮氧化矽、或是其他常用的材料。低介電常數的介電材料的介電常數(k值)可約小於3.9、或是約小於2.8。金屬化結構中的金屬線的材質可為銅或是銅合金。本領域具有通常知識者當可使用適當的製程來形成金屬化層，因此，省略金屬化層的詳細製程。如第1A圖所示，導電區12為一金屬化層，其形成在一頂端的內層介電層中，金屬化層為部分的導線並具有一外露表面，如果有必要的話，可對外露表面進行一平坦化製程，例如化學機械研磨。適合用來形成導電區的材料可包括，但不限於，例如銅、鋁、鋁銅合金、銅合金、或其他導電材料。接觸區12可為一金屬墊區或是一重佈線區，用於接合製程以連接個別晶片中的積體電路至外部結構。
第1A圖亦繪示一保護層14形成在基板10上以及圖案化保護層14以形成一開口，其暴露出一部分的接觸區12，以提供後續的凸塊形成。在至少一實施例中，保護層14的材質為無機材料，例如未摻雜的矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、或前述之組合。在另一實施例中，保護層14係由一高分子層構成，高分子層例如為環氧樹脂、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、聚苯噁唑(polybenzoxazole，PBO)、或其相似物，然而，亦可使用其他相對較軟的介電材料，通常為有機介電材料。
第1A圖更繪示形成一凸塊下金屬層(under-bump-metallurgy，UBM)16。在一些實施例中，凸塊下金屬層16包括形成在基板10上的一第一凸塊下金屬層16a以及一第二凸塊下金屬層16b。舉例來說，凸塊下金屬層16形成在接觸區12的外露部上，並延伸至部分的保護層14上。第一凸塊下金屬層16a(亦可稱為擴散阻障層或是黏著層)的材質包括鈦、鉭、氮化鈦、氮化鉭、或其相似物，其形成方法包括物理氣相沉積法或是濺鍍法。沉積第一凸塊下金屬層16a至一厚度，約為500埃至2000埃，以及在一些實施例中，例如沉積至約1000埃的厚度。第二凸塊下金屬層16b為一銅晶種層，其係以物理氣相沉積法或是濺鍍法形成在第一凸塊下金屬層16a上。第二凸塊下金屬層16b的材質可包括銅合金，其包括銀、鉻、鎳、錫、金、或前述之組合。沉積第二凸塊下金屬層16b至一厚度，約為500埃至10000埃，以及在一些實施例中，例如沉積至約5000埃的厚度。在至少一實施例中，凸塊下金屬層16包括一材質為鈦的第一凸塊下金屬層16a以及一材質為銅的第二凸塊下金屬層16b。
之後，在第1B圖中，在第一凸塊下金屬層16a上形成一罩幕層20，並圖案化罩幕層20以形成一開口18，其暴露出部分的第一凸塊下金屬層16以供凸塊形成。罩幕層20為一乾膜或是一光阻膜經過塗佈、固化、除殘渣(descum)、及/或其相似步驟，之後，進行微影與蝕刻製程，例如乾式蝕刻及/或濕式蝕刻製程。
然後，以一具有焊料潤濕性(solder wettability)的導電材料部分填滿開口18。參照第1C圖，一銅層22形成在開口18中以接觸其下的第二凸塊下金屬層16b。銅層22預計大體上包括一膜層，包括純元素銅、含有無法避免的雜質的銅、及/或含有微量元素的銅合金，該微量元素例如為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、或鋯。形成方法可包括濺鍍、印刷、電鍍、無電鍍、及/或常用的化學氣相沉積法。舉例來說，可進行電化學鍍(electro-chemical plating，ECP)以形成銅層22。在一實施例中，銅層22的厚度大於30微米。在另一實施例中，銅層22的厚度大於40微米。舉例來說，銅層22的厚度約為40微米～50微米，或是約為40微米～70微米，雖然銅層22的厚度亦可大於或是小於前述厚度。在下文中，銅層22被稱為銅柱22。
然後，一金屬蓋層24形成在銅柱22的頂面上。金屬蓋層24可做為一阻障層以防止銅柱22中的銅擴散入接合材料中，例如焊料合金，其係用以接合基板10與外部結構。防止銅擴散可增加封裝體的可靠度與接合強度。金屬蓋層24為一金屬化層，其可包括鎳、錫、錫鉛(tin-lead，SnPb)、金、銀、鈀、銦、鎳鈀金(nickel-palladium-gold，NiPdAu)、鎳金(nickel-gold，NiAu)、其他相似的材料、或合金。金屬蓋層24為一多層結構或一單層結構。在至少一實施例中，金屬蓋層24的厚度約為1微米～5微米。然後，在金屬蓋層24上並在罩幕層20的開口18中形成一焊料層26。焊料層26的材質包括錫、錫銀、錫-鉛、錫銀銅(銅含量小於0.3重量百分比)、錫銀鋅、錫鋅、錫鉍-銦、錫-銦、錫-金、錫鉛、錫銅、錫鋅銦、或是錫銀銻等。在至少一實施例中，焊料層26為無鉛焊料層。
請參照第1D圖，移除罩幕層20以暴露出部分的凸塊下金屬層16。最終結構包括銅柱22、金屬蓋層24、以及焊料層26，且暴露出銅柱22的側壁22a。在本實施例中，罩幕層20為一乾膜，其可以鹼性溶液移除。之後，可以最終結構(包括銅柱22、金屬蓋層24、以及焊料層26)為罩幕以濕式及/或乾式蝕刻製程回蝕刻(etch back)第二凸塊下金屬層16b與第一凸塊下金屬層16a的外露部，並可依凸塊下金屬材料選擇蝕刻的方式。
為保護銅柱22的外露側表面22a，在銅柱22上形成一側壁保護層。如第1E圖所示，在一實施例中，一金屬化層28形成在銅柱22的外露側表面22a上。在一些實施例中，金屬化層28延伸以覆蓋金屬蓋層24與焊料層26的外露表面。金屬化層28的材質包括鈷或鈷合金，例如鈷鎢硼磷(CoWBP)或是鈷鎢磷(CoWP)。可利用鈷基(Cobalt-based)的蓋層抑制銅的擴散與遷移。藉由無電鍍製程或是浸鍍製程，金屬化層28選擇性地形成在凸塊下金屬層16、銅柱22、金屬蓋層24、以及焊料層26的外露表面上，但不形成在保護層14上。藉由使用無電鍍製程，可準確地控制金屬化層28的厚度。在一些實施例中，金屬化層28的厚度約為0.1～10微米。金屬化層28可為單層結構、雙層結構、或是三層結構。
參照第1F圖，進行一熱回流製程(thermally reflowing process)，以經由晶圓加熱製程或是快速熱製程(rapid thermal processing，RTP)熔化焊料層26而形成一半球狀焊料凸塊26a。金屬化層28中的鈷元素混入最終產生的焊料凸塊26a中。在回流之後，在一些實施例中，當溫度低於焊料凸塊26a的熔化溫度時，可選擇性地進行一額外的退火製程，以使鈷元素進一步擴散入焊料凸塊26a中。在最終形成的焊料凸塊26a中，鈷元素的含量約小於0.7原子百分比，或是約小於0.1原子百分比，或是甚至約小於0.01原子百分比。由於額外添加鈷元素，因此，焊料凸塊26a中形成有錫銀鈷(SnAgCox )介金屬化合物(intermetallic compound，IMC)以抑制錫銀介金屬化合物的形成。因此，至少可降低焊料凸塊26a的過冷效應，且焊料凸塊26a可更加均勻地固化。可以觀察到的是，摻雜鈷的焊料凸塊的過冷溫度可降低至約7℃～30℃。
然後，如第1G圖所示，進行一氧化製程以使金屬化層28成為一金屬氧化物層(metal oxide layer)30，以消除銅柱側壁的潤濕問題。在至少一實施例中，金屬氧化物層30為一鈷氧化物(cobalt oxide，CoOx )層。在此，完成一凸塊結構32，其包括銅柱22、金屬蓋層24、焊料凸塊26a、以及金屬氧化物層30。本發明提供一種蓋住銅柱22的側壁表面的方法，其係於移除罩幕層20之後進行一無電鍍鈷的沉積製程，之後，在熱回流焊料層26之後，氧化金屬化層28。除了作為側壁保護層之外，鈷元素可被摻入並重新分布於焊料凸塊26a中以改變焊料的特性，且金屬氧化製程可防止銅柱側壁被焊料潤濕(solder wetting)。不潤濕的效應(non-wetting effect)有利於導線上凸塊(bump-on-trace，BOT)封裝技術。相較於習知的浸錫製程，無電鍍鈷沉積法可較佳地控制側壁保護層的厚度，以形成一較薄的側壁保護層，故可降低製作成本。
然後，可切割基板10並將其封裝至一封裝基板上，或是另一晶片上，並在封裝基板或是另一晶片的接墊上配置焊球或是銅凸塊。第2圖繪示本發明一實施例之一覆晶裝置的剖面圖。翻覆第1G圖中的結構並貼附至第2圖下方的另一基板100。基板100可為一封裝基板、板材(例如印刷電路板)、或是其他適合的基板。凸塊結構32經由各種導電連接點耦接至基板100，以形成一耦接基板10、100的連接結構，其中導電連接點例如為接墊上的接合焊料層102及/或導線104。接合焊料層102可為共熔焊料材料(eutectic solder material)，包括錫、鉛、銀、銅、鎳、鉍、或前述之組合的合金。在一些實施例中，由於接合焊料層102係藉由連接焊料凸塊26a與基板100的一預焊料層而形成，因此，接合焊料層102包括鈷元素。在一實施例中，耦接製程包括提供一助熔劑(flux)、配置晶片、回流熔化的焊料接點、及/或清除剩餘的助熔劑。積體電路基板10、接合焊料層102、以及其他的基板100可稱為封裝裝置200、或是在本實施例中，可稱為覆晶封裝裝置。在至少一實施例中，凸塊結構32與導線104重疊並形成一導線上凸塊互連結構。
請參照第3圖，其繪示本發明一實施例之一凸塊結構的製作方法300的流程圖。製作方法300可製作出上述圖式所示之結構，例如凸塊結構32。可以知道的是，可在製作方法300進行之前、之時、及/或之後進行額外的步驟，且在該製作方法的各種實施例中可取代或是省略下述的一些步驟。
製作方法300的步驟310為在一半導體基板上形成一凸塊下金屬層。在至少一實施例中，導體基板包括一導電區以及一保護層，保護層具有一開口，其暴露出部分的導電區。凸塊下金屬層經由保護層的開口電性連接導電區。在步驟312中，在凸塊下金屬層上形成一罩幕層，其中罩幕層被圖案化並具有一開口暴露出部分的凸塊下金屬層。在下一步驟314中，在罩幕層的開口中形成一銅柱，以電性連接其下的凸塊下金屬層。之後，在步驟316中，在銅柱上形成一金屬蓋層，接著，在步驟318中，在金屬蓋層上形成一焊料層。然後，在步驟320中，移除罩幕層，之後，在步驟322中，進行一凸塊下金屬製程，其係以銅柱為罩幕移除凸塊下金屬層的外露部。製作方法300的步驟324為在凸塊下金屬層、銅柱、金屬蓋層、以及焊料層的外露表面上形成一金屬化層。在一實施例中，金屬化層包括以無電鍍沉積的方式形成的一鈷層或是一鈷合金層之至少其中之一。製作方法300的步驟326為對焊料層進行一熱回流製程。焊料層經回流製程而形成一半球狀的焊料凸塊，且鈷元素摻雜並分散於其中。在下一步驟328中，對金屬化層進行一氧化製程，以形成一金屬氧化物層於銅柱及/或金屬蓋層的側壁表面上。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．基板
12．．．導電區、接觸區
14．．．保護層
16‧‧‧凸塊下金屬層
16a‧‧‧第一凸塊下金屬層
16b‧‧‧第二凸塊下金屬層
18‧‧‧開口
20‧‧‧罩幕層
22‧‧‧銅層、銅柱
22a‧‧‧側壁、側表面
24‧‧‧金屬蓋層
26‧‧‧焊料層
26a‧‧‧焊料凸塊
28‧‧‧金屬化層
30‧‧‧金屬氧化物層
32‧‧‧凸塊結構
100‧‧‧基板
102‧‧‧接合焊料層
104‧‧‧導線
200‧‧‧封裝裝置
300‧‧‧凸塊結構的製作方法
310、312、314、316、318、320、322、324、326、328‧‧‧步驟
第1A圖至第1G圖繪示本發明一實施例之一銅柱凸塊結構的製程剖面圖。
第2圖繪示本發明一實施例之一封裝裝置的剖面圖。
第3圖繪示本發明多個實施例之一銅柱凸塊結構的製作流程圖。
10．．．基板
12．．．導電區、接觸區
14．．．保護層
16．．．凸塊下金屬層
16a．．．第一凸塊下金屬層
16b．．．第二凸塊下金屬層
22．．．銅層、銅柱
24．．．金屬蓋層
26a．．．焊料凸塊
30．．．金屬氧化物層
32．．．凸塊結構

Claims (11)

  1. 一種積體電路元件，包括：一半導體基板；一凸塊下金屬層，配置於該半導體基板上；一導電柱，配置於該凸塊下金屬層上；以及一鈷氧化物層，形成於該導電柱之一側壁表面上，其中該導電柱之一底表面不含有該鈷氧化物層。
  2. 如申請專利範圍第1項所述之積體電路元件，更包括：一焊料層，配置該導電柱上，其中該焊料層包括鈷元素。
  3. 如申請專利範圍第2項所述之積體電路元件，更包括：一金屬蓋層，位於該導電柱與該焊料層之間，其中該鈷氧化物層延伸以覆蓋該金屬蓋層的側壁表面。
  4. 如申請專利範圍第1項所述之積體電路元件，其中該導電柱為一銅柱。
  5. 一種封裝裝置，包括：一第一基板，包括一凸塊結構；一第二基板，貼附至該第一基板；以及一接合焊料層，位於該第二基板與該第一基板的該凸塊結構之間；其中，該凸塊結構包括一金屬柱以及一鈷氧化物層形成於該金屬柱之一側壁表面上，其中該金屬柱之一底表面不含有該鈷氧化物層。
  6. 如申請專利範圍第5項所述之封裝裝置，其中該接合焊料層的材質包括鈷元素。
  7. 如申請專利範圍第5項所述之封裝裝置，其中該第二基板包括一導線，該導線與該凸塊結構重疊以形成一導線上凸塊互連結構。
  8. 一種積體電路元件的製作方法，包括：形成一金屬柱於一半導體基板上；形成一焊料層於該金屬柱上；形成一金屬化層覆蓋該金屬柱與該焊料層，其中該金屬化層的材質包括鈷元素；熱回流該焊料層以形成一焊料凸塊，其中該金屬化層的該鈷元素被驅入該焊料凸塊中；以及氧化該金屬化層以形成一金屬氧化物層於該金屬柱的側壁表面上。
  9. 如申請專利範圍第8項所述之積體電路元件的製作方法，其中該金屬柱為一銅柱，且該金屬化層為一鈷層，該金屬氧化物層為一鈷氧化物層。
  10. 如申請專利範圍第8項所述之積體電路元件的製作方法，其中該金屬化層的形成方法為無電鍍沉積。
  11. 如申請專利範圍第8項所述之積體電路元件的製作方法，更包括：在形成該金屬化層之前，形成一金屬蓋層於該金屬柱與該焊料層之間，其中該金屬蓋層的材質包括鎳。
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