TWI411080B - 半導體元件、封裝結構、及半導體元件的形成方法 - Google Patents

半導體元件、封裝結構、及半導體元件的形成方法 Download PDF

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TWI411080B
TWI411080B TW100100174A TW100100174A TWI411080B TW I411080 B TWI411080 B TW I411080B TW 100100174 A TW100100174 A TW 100100174A TW 100100174 A TW100100174 A TW 100100174A TW I411080 B TWI411080 B TW I411080B
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solder
layer
metal cap
bump
cap layer
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TW100100174A
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TW201128753A (en
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Yi Li Hsiao
Chen Hua Yu
Shin Puu Jeng
Chih-Hang Tung
cheng chang Wei
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Taiwan Semiconductor Mfg
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Description

半導體元件、封裝結構、及半導體元件的形成方法
本發明係關於半導體元件，更特別關於半導體元件中的凸塊結構之製程。
現代的積體電路係由水平排列，且數以百萬計的主動元件如電晶體及/或被動元件如電容組成。這些元件在初期製程彼此絕緣，但在後續續製程中以內連線連接元件以形成功能電路。典型的內連線結構包含水平內連線如金屬線路，與垂直內連線如接孔和接點。現代積體電路的效能與密度取決於內連線。在內連線結構頂部，每一晶片表面上各自形成有露出的焊墊。經由焊墊，晶片可電性連接至封裝基板或另一晶粒。焊墊可用以打線接合或覆晶接合。在一般的凸塊製程中，內連線結構係形成於金屬化層上，接著再形成凸塊下冶金層(UBM)與焊球。覆晶封裝採用凸塊作為晶片之輸入/輸出墊與基板(或封裝之導線架)之間的電性接點。結構上來說，凸塊除了凸塊本身以外，還含有所謂的UBM位於凸塊與輸入/輸出墊之間。位UBM一般含有黏著層、阻障層、與濕潤層依序位於輸入/輸出墊上。凸塊依其材料組成可分為焊料凸塊、金凸塊、銅柱凸塊、或混合金屬凸塊。
一般來說，用於焊料合金之材料為所謂的錫鉛共熔焊料，其中鉛占38重量%。近來半導體產業開始轉用無鉛封裝與無鉛元件的連接技術。上述趨勢導致形成積體電路與封裝之連接結構的焊料凸塊與焊球無鉛。與含鉛焊料或焊球相較，無鉛焊料對環保、勞工、與消費者來說較安全。然而無鉛焊料凸塊的品質與可信度並非永遠符合需求。對更小的腳距與更大的積體密度來說，在製程與覆晶封裝中採用無鉛焊料產生短路的風險更高。
本發明一實施例提供一種半導體元件，包括半導體基板；焊墊區位於半導體基板上；焊料凸塊位於焊墊區上並電性連接至焊墊區；以及金屬蓋層位於至少部份焊料凸塊上；其中金屬蓋層之熔點高於焊料凸塊之熔點。
本發明另一實施例提供一種封裝結構，包括半導體基板；封裝基板；以及凸塊結構位於半導體基板與封裝基板之間，且凸塊結構電性連接半導體基板與封裝基板；其中凸塊結構包括焊料凸塊與金屬蓋層，金屬蓋層覆蓋至少部份焊料凸塊，且金屬蓋層之熔點高於焊料凸塊之熔點。
本發明又一實施例提供一種半導體元件的形成方法，包括形成焊料層於半導體基板上；進行再流動熱製程於焊料層上；以及形成金屬蓋層於至少部份焊料層上；其中金屬蓋層之熔點高於焊料層之熔點。
下述說明之半導體元件中的凸塊製程，可應用於覆晶封裝、晶圓等級的晶片尺寸封裝(WLCSP)、三維積體電路(3D-IC)堆疊、及/或任何先進的封裝技術領域。實施例係關於半導體元件所用之焊料凸塊其形成方法。在下述說明中，多種特例會先置前以利本技藝人士對本發明有全面性的了解。然而本技藝人士應理解，實際上的操作並不需完全符合這些特例。在某些例子中，不會詳細地描述本技藝熟知的結構與製程，以避免不必要地模糊揭露內容。在下述說明中，「一實施例」指的是特定特徵、結構、或至少一實施例中包含的實施例所連結的結構。因此，不同段落中的「一實施例」指的不一定是同一實施例。此外，一或多個實施例中的特定特徵、結構、或特點可由任何合適態樣組合。可以理解的是，下述圖示並非依比例繪示，僅用以方便說明而已。此外在一或多個實施例中，上述特定特徵或結構可採用合適的態樣組合。可以理解的是，下述圖示並未以比例繪示，僅用以示意說明。
第1A-1G圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖。
如第1A圖所示，提供半導體基板10以利後續凸塊製程形成其中，且積體電路亦可形成其中及/或其上。半導體基板10之組成可包含半導體材料，比如但不限定於基體矽、半導體晶圓、絕緣層上矽(SOI)基板、或矽鍺基板。半導體基板10亦可含有III族、IV族、或V族元素。半導體基板10可包含多個絕緣結構(未圖示)如淺溝槽絕緣(STI)結構或局部氧化矽(LOCOS)結構。絕緣結構可用以隔離多個微電子單元(未圖示)。形成於半導體基板10中的多個微電子單元含有電晶體如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙載子連接電晶體(BJT)、高電壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體(PFET/NFET)，電阻，二極體，電容，電感，熔絲，或其他合適單元。形成多種微電子單元的多種製程含有沉積、蝕刻、佈植、微影、回火、或其他合適製程。微電子單元可經由內連線形成積體電路元件如邏輯元件、輸入/輸出元件、系統單晶片(SoC)元件、上述之組合、或其他合適種類的元件。
半導體基板10可更含有層間介電層與金屬化結構於積體電路上。位於金屬化結構中的層間介電層含有低介電常數之介電材料、未掺雜之矽酸鹽玻璃(USG)、氮化矽、氮氧化矽、或其他常用材料。低介電常數之介電材料的介電常數(k值)可小於約3.9，或小於約2.8。金屬化結構中的金屬線之組成可為銅或銅合金。本技藝人士應了解金屬化層之形成方法，在此不贅述。
如第1A圖所示，在半導體基板10上形成焊墊區12與保護層14。焊墊區12係形成於層間介電層上的金屬化層。焊墊區12係部份的導電線路，且可依需要進行平坦化製程於焊墊區12露出的表面上。適用於焊墊區12之材料可為但不限定於銅、鋁、銅合金、或其他現有的導電材料。焊墊區12之組成亦可為銀、金、鎳、鎢、上述之合金、及/或上述之多層結構。在一實施例中，焊墊區12為焊墊區，可在接合製程中使個別晶片之積體電路連線至外部結構。形成於半導體基板10上的保護層14係位於焊墊區12上。藉由微影與蝕刻製程，可圖案化保護層14以形成開口露出部份的焊墊區12。在一實施例中，保護層14之組成為非有機材料如USG、氮化矽、氮氧化矽、氧化矽、或上述之組合上。在另一實施例中，保護層14之組成為有機材料如環氧樹脂、聚亞醯胺、雙苯並環丁烷(BCB)、聚苯并噁唑(PBO)、或其他較軟的有機介電材料。
第1A圖亦顯示凸塊下冶金層16形成於保護層14上並電性連接至焊墊區12。凸塊下冶金層16形成於保護層14上，並露出部份焊墊區12。在一實施例中，凸塊下冶金層16含有擴散阻障層及/或晶種層。擴散阻障層又稱作膠層，覆蓋保護層14之開口的側壁及底部。擴散阻障層之組成可為鈦，亦可為其他材料如氮化鈦、鉭、氮化鉭、或類似物。擴散阻障層之形成方法可為物理氣相沉積法(PVD)或濺鍍法。晶種層可為形成於擴散阻障層上的銅晶種層，其形成方法可為PVD或濺鍍。晶種層之組成可為銅合金，除了銅以外還含有銀、鉻、鎳、錫、金、或上述之組合。在一實施例中，凸塊下冶金層16為銅/鈦層。擴散阻障層之厚度可介於約1000至2000之間，而晶種層之厚度可介於約3000至7000之間，不過上述層狀結構之厚度可大於或小於上述範圍。在後述揭露中的尺寸範圍僅用以舉例，可隨著更小尺寸的積體電路調整。
第1A圖亦顯示遮罩層18形成於凸塊下冶金層16上，並可圖案化遮罩層18以形成開口19。舉例來說，圖案化遮罩層18的方法可為曝光、顯影、及蝕刻。開口19可露出部份凸塊下冶金層16以利形成凸塊。遮罩層18可為乾膜或光阻膜。在一實施例中，遮罩層18為乾膜，其組成可為有機材料如Ajinimoto增層膜(ABF)。在另一實施例中，遮罩層18為光阻。遮罩層18之厚度可大於約5μm，或介於約10μm至約120μm之間。
如第1B圖所示，在遮罩層18之開口19中形成焊料層22，使焊料層22位於凸塊下冶金層16上。焊料層22之組成為錫、錫銀、錫鉛、錫銀銅(銅之重量%小於0.3%)、錫銀鋅、錫鋅、錫鉍銦、錫銦、錫金、錫鉛、錫銅、錫鋅銦、錫銀銻、或類似物。在一實施例中，焊料層22為無鉛焊料層。在某些實施例中，在形成焊料層22之前，可視情況先沉積金屬化層20於開口19中。金屬化層20之厚度小於10μm。在某些實施例中，金屬化層20之厚度介於約1μm至10μm之間，比如4μm至8μm之間，不過金屬化層20之厚度可大於或小於上述範圍。金屬化層20之形成方法可為電鍍法。在一實施例中，金屬化層20之組成可為銅層、銅合金層、鎳層、鎳合金層、或上述之組合。在某些實施例中，金屬化層20含有金、銀、鈀、銦、鎳鈀金、鎳金、或其他類似材料或合金。
接著如第1C圖所示，移除遮罩層18。若遮罩層18之組成為乾膜，其移除方法需採用鹼性溶液。若遮罩層18之組成為光阻，其移除方法為濕式剝除法，其採用之溶劑可為丙酮、N-甲基吡咯烷酮(NMP)、二甲基亞碸(DMSO)、2-(氨基乙氧基)乙醇、或類似物。上述移除步驟將露出未被焊料層22覆蓋的凸塊下冶金層16，並使焊料層22形成焊料柱22a。在一實施例中，焊料柱22a之厚度大於40μm。在其他實施例中，焊料柱22a之厚度介於約40μm至70μm之間，但焊料柱之厚度亦可大於或小於上述範圍。接著如第1D圖所示，移除露出的凸塊下冶金層16並露出其下方的保護層14，且移除方法可為蝕刻如濕蝕刻、乾蝕刻、或類似方法。
如第1E圖所示，於焊料柱22a上進行再流動熱製程，形成球狀的焊料凸塊22b。在熱循環中，可形成金屬間化合物(IMC)層於焊料凸塊22b與金屬化層20之間。形成IMC層可消耗金屬化層20。
如第1F圖所示，形成金屬蓋層24於至少部份露出的焊料凸塊22b上。在一實施例中，金屬蓋層24形成於焊料凸塊22b的所有表面上。在其他實施例中，金屬蓋層24延伸至覆蓋金屬化層20與凸塊下冶金層16之表面上。金屬蓋層24為金屬材料層，其溶點高於焊料層22之熔點。在某些實施例中，金屬蓋層24之組成為銅、鎳、金、銀、鈀、銦、鎳鈀金、鎳金、其他類似材料、或合金。在某些實施例中，金屬蓋層24更包含其他用於半導體封裝的導電材料如銦、鉑、鈷、釩、或上述之合金。在一實施例中，金屬蓋層24之厚度介於約0.02μm至5μm之間，但金屬蓋層24之厚度亦可大於或小於上述範圍。金屬蓋層24可為單層或多層結構。在一實施例中，金屬蓋層24之沉積方法可為無電或浸潤金屬沉積製程，比如無電鎳無電鈀與浸金結構(無電鎳/無電鈀/浸潤金之堆疊結構，ENEPIG)、無電鎳無電鈀結構(無電鎳/無電鈀之堆疊結構，ENEP)、無電鎳層(EN)、無電鎳與浸金結構(無電鎳/浸潤金之堆疊結構，ENIG)、或上述之組合。
上述步驟形成的凸塊結構26具有凸塊下冶金層16、視情況形成的金屬化層20、焊料凸塊22b、與金屬蓋層24。此實施例之凸塊結構26可具有不同尺寸的直徑，且可包含所謂的微凸塊。舉例來說，凸塊結構26之直徑可介於65μm至80μm之間。凸塊結構26之間的腳距可小於150μm，比如介於130μm至140μm之間，甚至更小的尺寸。在微凸塊的應用中，凸塊之間的腳距可介於20μm至50μm之間，且凸塊直徑可介於10μm至25μm之間。
凸塊結構26被金屬蓋層24覆蓋的部份較硬，其熔點亦高於焊料凸塊22b之熔點。在實質上推擠基板時，金屬蓋層24可讓焊料凸塊22b作為彈簧或充氣的氣球，以避免破壞凸塊結構26。某方面來說，金屬蓋層24可作為硬停元件(hard stop)。封裝完成後，凸塊結構26可維持一致的高度，可減少甚至避免短路或橋接等問題。
如第1G圖所示，係應用凸塊結構26之封裝結構的示意圖。在形成凸塊結構26後切割半導體基板10，並將其嵌置於封裝基板或另一晶粒上的焊墊上之銅柱或焊球。經上述步驟後，可將第1F圖之結構連接至另一基板100。基板100可為封裝基板、板子如印刷電路板(PCB)、或其他合適基板。連接結構102接觸基板100的方式可為多種導電接點，比如位於接觸墊104及/或導電線上的焊料層106。焊料層106可為共熔焊料如含有錫、鉛、銀、銅、鎳、鉍、或上述之組合的合金。舉例來說，耦合製程含有採用助焊劑、放置晶片、熔融之焊料接點的再流動熱製程、與清除助焊劑殘餘物。經上述耦合步驟，即形成接點焊料結構108a於半導體基板10與基板100之間。半導體基板10、接點焊料結構108a、與基板100可稱作封裝結構200，或稱之為覆晶封裝。在某些實施例之封裝結構的熱循環步驟中，金屬蓋層24可與焊料凸塊22b及/或焊料層106反應，在接點焊料結構108a中形成金屬間化合物(IMC)。此外，在熱循環步驟後，金屬蓋層24中的金屬元素會擴散至焊料凸塊22b及/或焊料層106。金屬間化合物(IMC)會消耗部份金屬蓋層24。可以發現的是，在焊料凸塊22b上採用金屬蓋層24有助於完成的封裝結構具有更一致的高度，進而改善半導體元件之可信度。
第2A-2C圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖。在下述說明中，將省略與第1A-1G圖重疊的部份。
如第2A圖所示，在第1D圖中蝕刻凸塊下冶金層的製程後，接著形成金屬蓋層24。如此一來，在進行焊料再流動的熱製程之前，已先形成金屬蓋層24於焊料柱22a上。在一實施例中，以無電或浸潤法沉積金屬蓋層24於焊料柱22a的整個表面上。在某些實施例中，金屬蓋層24延伸至覆蓋部份的金屬化層20與凸塊下冶金層16。這將使凸塊結構28a含有凸塊下冶金層16、視情況形成之金屬化層20、焊料柱22a、與金屬蓋層24。在實質上推擠基板時，金屬蓋層24可讓焊料柱22a作為彈簧或充氣的氣球。金屬蓋層24可作為硬停元件，使封裝完成後的凸塊結構28a維持一致的高度，可減少甚至避免短路或橋接等問題。
在另一實施例中，凸塊結構28a接著進行焊料再流動的熱製程。如第2B圖所示，熱製程可再流動焊料柱22a，使其形成具有圓潤邊角的焊料凸塊22c。在一實施例的剖視圖中，焊料凸塊22c具有圓潤邊角。此外在熱循環之步驟後，金屬蓋層24中的金屬元素可能擴散至焊料凸塊22c。這將形成另一焊料凸塊28b，其含有凸塊下冶金層16、視情況形成之金屬化層20、具有圓潤邊角之焊料凸塊22c、與金屬蓋層24。在實質上推擠基板時，金屬蓋層24可讓焊料凸塊22c作為彈簧或充氣的氣球。金屬蓋層24可作為硬停元件，使封裝完成後的凸塊結構28b維持一致的高度，可減少甚至避免短路或橋接等問題。
如第2C圖所示，係應用凸塊結構28b之封裝結構的示意圖。在形成凸塊結構28a或28b後切割半導體基板10，並經由連接結構102將其嵌置於另一基板100。連接結構102可為位於接觸墊104及/或導電線上的焊料層106。經由耦合步驟，可形成接點焊料結構108b於半導體基板10與基板100之間。半導體基板10、接點焊料結構108b、與基板100可稱作封裝結構300。在形成凸塊結構28a於半導體基板10上的情況下，耦合製程的熱能可使焊料柱22a再流動，以形成具有圓潤邊角之焊料凸塊22c，使焊料結構28a轉變為封裝結構300中的焊料結構28b。此外在熱循環後，金屬蓋層24之金屬元素可能會擴散至焊料凸塊22c及/或焊料層106中。可以發現的是，凸塊結構28a與28b的金屬蓋層24有助於完成的封裝結構具有一致的高度，進而改善半導體元件之可信度。
第3A-3D圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖。在下述說明中，將省略與第1A-1G圖重疊的部份。
如第3A圖所示，移除遮罩層形成第1C圖所示之結構後，形成金屬蓋層24。如此一來，在蝕刻凸塊下冶金層16之步驟前，已先形成金屬蓋層24於焊料柱22a與部份露出的凸塊下冶金層16上。在一實施例中，形成金屬蓋層24於焊料柱22a的整個表面上之方法可為電鍍法、無電電鍍法、或化學氣相沉積法(CVD)。
接著如第3B圖所示，進行蝕刻製程如濕蝕刻、乾蝕刻、或類似方法移除焊料柱22a以外的凸塊下冶金層16，直到露出保護層14。上述蝕刻製程將移除焊料柱22a以外的金屬蓋層24與凸塊下冶金層16，亦移除焊料柱22a表面上的部份金屬蓋層24。在一實施例中，位於焊料柱22a頂部上的部份金屬蓋層24被移除，以露出焊料柱22a之頂部表面22t。在某些實施例中，鄰接焊料柱22a較上方的側壁表面之部份金屬蓋層24被移除，以露出焊料柱22a較上方的側壁表面22su。此時金屬蓋層24係保留於焊料柱22a較下方的側壁表面22sL 上。
如第3C圖所示，進行熱製程使焊料柱22a再流動，以形成圓潤表面之焊料凸塊22d。在熱循環步驟後，金屬蓋層24中的金屬元素會擴散至焊料凸塊22d，可形成金屬間化合物(IMC)於焊料凸塊22d與金屬蓋層24之間。這將使凸塊結構30含有凸塊下冶金層16、視情況形成之金屬化層20、焊料柱22d、與金屬蓋層24。金屬蓋層24保留於焊料凸塊22d較下方的側壁表面22sL 上。在實質上推擠基板時，金屬蓋層24可讓焊料凸塊22d作為彈簧或充氣的氣球。金屬蓋層24可作為硬停元件，使封裝完成後的凸塊結構30維持一致的高度，可減少甚至避免短路或橋接等問題。
如第3D圖所示，係應用凸塊結構30之封裝結構的示意圖。在形成凸塊結構30後切割半導體基板10，並經由連接結構102將其嵌置於另一基板100。連接結構102可為位於接觸墊104及/或導電線上的焊料層106。經由耦合步驟，可形成接點焊料結構108c於半導體基板10與基板100之間。半導體基板10、接點焊料結構108c、與另一基板100可稱作封裝結構400。可以發現的是，凸塊結構30的金屬蓋層24有助於完成的封裝結構具有一致的高度，進而改善半導體元件之可信度。
第4A-4E圖係本發明一實施例中，部份導體元件在凸塊製程中的結構剖視圖。在下述說明中，將省略與第1A-1G圖重疊的部份。
如第4A圖所示，在形成焊料層22於遮罩層18之開口19後，移除部份遮罩層18以露出部份的焊料柱22a並保留部份遮罩層18於焊料柱22a靠近底部的部份。在一實施例中，上述步驟露出焊料柱22a之頂部表面22t及較上方的側壁表面22s1 。舉例來說，此步驟可露出超過50%的側壁表面，比如露出約70%至80%之間的側壁表面。
接著如第4B圖所示，形成金屬蓋層24於焊料柱22a露出的表面上，其形成方法可為電鍍法或無電電鍍法。之後再移除殘留的遮罩層18。如此一來，金屬蓋層24可形成於焊料柱22a露出的表面如頂部表面22t及較上方的側壁表面22s1 上。在完全移除遮罩層18後，將露出凸塊下冶金層16與焊料柱22a較下方之側壁表面22s2 。
接著如第4C圖所示，進行蝕刻製程如濕蝕刻、乾蝕刻、或類似方法移除焊料柱22a以外的凸塊下冶金層16，直到露出保護層14。上述蝕刻製程亦移除焊料柱22a表面上的部份金屬蓋層24。在一實施例中，位於焊料柱22a頂部上的部份金屬蓋層24被移除，以露出焊料柱22a之頂部表面22t。在某些實施例中，位於焊料柱22a較上方的側壁上之部份金屬蓋層24被移除，以露出焊料柱22a之側壁頂部表面22s1t ，使金屬蓋層24保留於焊料柱22a之中間部份的側壁表面22sm上。
如第4D圖所示，進行熱製程使焊料柱22a再流動，以形成卵狀之焊料凸塊22e。由於金屬蓋層24之熔點高於焊料，底部的凸塊22e1 將會水平延展出金屬蓋層24。底部的凸塊22e1 具有多種好處如下：具有額外的應力緩衝結構、增加焊料凸塊與其下材料層之間的黏著力、以及提供機械應力緩衝。在熱循環步驟中，金屬蓋層24中的金屬元素會擴散至焊料凸塊22e，可形成金屬間化合物(IMC)於焊料凸塊22e與金屬蓋層24之間。
上述步驟形成的凸塊結構32含有凸塊下冶金層16、視情況形成之金屬化層20、焊料柱22e、與金屬蓋層24。在實質上推擠基板時，金屬蓋層24可讓焊料凸塊22e作為彈簧或充氣的氣球。金屬蓋層24可作為硬停元件，使封裝完成後的凸塊結構30維持一致的高度，可減少甚至避免短路或橋接等問題。
如第4E圖所示，係應用凸塊結構32之封裝結構的示意圖。在形成凸塊結構32後切割半導體基板10，並經由連接結構102將其嵌置於另一基板100。連接結構102可為位於接觸墊104及/或導電線上的焊料層106。經由耦合步驟，可形成接點焊料結構108d於半導體基板10與基板100之間。半導體基板10、接點焊料結構108d、與另一基板100可稱作封裝結構500。可以發現的是，凸塊結構32的金屬蓋層24有助於完成的封裝結構具有一致的高度，進而改善半導體元件之可信度。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．半導體基板
12．．．焊墊區
14．．．保護層
16．．．凸塊下冶金層
18．．．遮罩層
19．．．開口
20．．．金屬化層
22．．．焊料層
22a．．．焊料柱
22b、22c、22d、22e．．．焊料凸塊
22e1 ．．．底部的凸塊
22s1 、22su．．．焊料柱較上方的側壁表面
22s1t ．．．焊料柱之側壁頂部表面
22sL 、22s2 ．．．焊料柱較上方的側壁表面
22sm．．．焊料柱中間部份的側壁表面
22t．．．焊料柱頂部表面
24．．．金屬蓋層
26、28a、28b、30、32．．．凸塊結構
100．．．基板
102．．．連接結構
104．．．接觸墊
106．．．焊料層
108a、108b、108c、108d．．．接點焊料結構
200、300、400、500．．．封裝結構
第1A-1G圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖；
第2A-2C圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖；
第3A-3D圖係本發明一實施例中，部份半導體元件在凸塊製程中的結構剖視圖；以及
第4A-4E圖係本發明一實施例中，部份導體元件在凸塊製程中的結構剖視圖。
10．．．半導體基板
26．．．凸塊結構
100．．．基板
102．．．連接結構
104．．．接觸墊
106．．．焊料層
108a．．．接點焊料結構
200．．．封裝結構

Claims (8)

  1. 一種半導體元件，包括：一半導體基板；一焊墊區位於該半導體基板上；一焊料凸塊位於該焊墊區上並電性連接至該焊墊區；以及一金屬蓋層位於至少部份該焊料凸塊上；其中該金屬蓋層之熔點高於該焊料凸塊之熔點，且其中該焊料凸塊之底部於水平方向延展出該金屬蓋層。
  2. 如申請專利範圍第1項所述之半導體元件，其中該金屬蓋層包括鎳、鈀、金、銅或無鉛焊料中至少一者。
  3. 如申請專利範圍第1項所述之半導體元件，其中該金屬蓋層至少形成於該焊料凸塊的整個表面上、該焊料凸塊較下方的側壁表面上、或該焊料凸塊中間的側壁表面上。
  4. 一種封裝結構，包括：一半導體基板；一封裝基板；以及一凸塊結構位於該半導體基板與該封裝基板之間，且該凸塊結構電性連接該半導體基板與該封裝基板；其中該凸塊結構包括一焊料凸塊與一金屬蓋層，該金屬蓋層覆蓋至少部份該焊料凸塊，且該金屬蓋層之熔點高於該焊料凸塊之熔點。
  5. 如申請專利範圍第4項所述之封裝結構，其中該金屬蓋層包括鎳、鈀、金、銅、或無鉛材料中至少一者。
  6. 如申請專利範圍第4項所述之封裝結構，其中部份該焊料凸塊於水平方向延展出該金屬蓋層。
  7. 一種半導體元件的形成方法，包括：形成一焊料層於一半導體基板上；進行一再流動熱製程於該焊料層上；以及形成一金屬蓋層於至少部份該焊料層上；其中該金屬蓋層之熔點高於該焊料層之熔點，其中該焊料層係一焊料凸塊，且該金屬蓋層至少覆蓋該焊料凸塊其部份的側壁表面。
  8. 如申請專利範圍第7項所述之半導體元件的形成方法，其中形成該金屬蓋層之步驟在該再流動熱製程之後或之前。
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US10522491B2 (en) 2019-12-31
TW201128753A (en) 2011-08-16
US20200126937A1 (en) 2020-04-23
US9960134B2 (en) 2018-05-01
CN102148201A (zh) 2011-08-10
CN102148201B (zh) 2013-08-21
US20130175683A1 (en) 2013-07-11
US9455183B2 (en) 2016-09-27
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US20170005051A1 (en) 2017-01-05
US20110186989A1 (en) 2011-08-04

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