TWI581348B - 形成導電特徵的方法 - Google Patents
形成導電特徵的方法 Download PDFInfo
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- TWI581348B TWI581348B TW104135985A TW104135985A TWI581348B TW I581348 B TWI581348 B TW I581348B TW 104135985 A TW104135985 A TW 104135985A TW 104135985 A TW104135985 A TW 104135985A TW I581348 B TWI581348 B TW I581348B
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- 238000000034 method Methods 0.000 title claims description 93
- 239000000463 material Substances 0.000 claims description 37
- 239000003989 dielectric material Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 6
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 239000003575 carbonaceous material Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
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- 229920001795 coordination polymer Polymers 0.000 claims 1
- 239000002861 polymer material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 174
- 239000004065 semiconductor Substances 0.000 description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
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- 230000000295 complement effect Effects 0.000 description 8
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- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 4
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- 125000002524 organometallic group Chemical group 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910017109 AlON Inorganic materials 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 125000000217 alkyl group Chemical group 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 2
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description
半導體積體電路(IC)工業已經歷了指數式增長。IC材料和設計的技術發展已生產了很多代IC,其每一代都具有比前一代更小且更複雜的電路。在IC演變過程中,功能密度(即,每個晶片區域中相互連接的元件的數量)在普遍增大,同時,幾何尺寸(即,用製造工藝能夠製作的最小部件(或線路))則有所減小。這種按比例縮小的工藝通常帶來了提高生產效率且降低相關成本的有益效果。按比例縮小已增加了IC工藝和製造的複雜性,並且,為實現這些改進,IC工藝和製造也需要類似的發展。然而,同樣需要的是形成導電特徵以連接IC元件中的特徵。
100‧‧‧多層互連結構
101‧‧‧失準
102、104‧‧‧導線
103、105‧‧‧堆疊的介電層中的一層
106‧‧‧孔
108‧‧‧堆疊的介電層
300‧‧‧元件
301‧‧‧基板
302‧‧‧蝕刻終止層
304‧‧‧導電層
304’‧‧‧導電特徵
306‧‧‧抗反射塗膜層
310‧‧‧圖案化遮罩層
312、312’‧‧‧第一介電層
340‧‧‧暴露表面
500‧‧‧半導體元件
501‧‧‧基板
502‧‧‧蝕刻終止層
504‧‧‧導電層
504’‧‧‧導電特徵
506‧‧‧抗反射塗膜層
508‧‧‧圖案化遮罩層
510、510’‧‧‧襯料層
512、512’‧‧‧第一介電層
540‧‧‧暴露表面
601、607‧‧‧具有低介電係數的介電材料
603、605‧‧‧導電特徵
630‧‧‧孔
為協助讀者達到最佳理解效果,建議在閱讀本揭露時同時應。應理解的是,根據工業中的常規標準,各種特徵并未按比例示出。事實上,為更清楚地論述,各種特徵尺寸可任意地增大或減小。
圖1根據本揭露實施例示出了半導體元件的失準的孔的示例。
圖2根據本揭露實施例示出了形成半導體元件的導電特徵的流程圖。
圖3A、3B、3C、3D、3E、3F和3G根據圖2中的方法示出了在不同製造階段所形成的導電特徵的截面圖。
圖4根據本揭露實施例示出了形成半導體元件的導電特徵的流程
圖。
圖5A、5B、5C、5D、5E、5F、5G、5H和5I根據圖4中的方法示出了在不同製造階段所形成的導電特徵的截面圖。
圖6A和6B中的每一個根據本揭露實施例提供了半導體元件的兩種導電特徵的比較示例,該比較示例分別通過傳統方法以及圖2和圖4中揭露的方法而形成。
本說明書提供了數個不同的實施方法或實施例,可用於實現本發明的不同特徵。以下所描述的組件和裝置的具體示例用以簡化本揭露。當然,這些只是示例並且旨在不局限於此。例如,以下所描述的在第二特徵之上或在第二特徵上形成第一特徵,則包括了以直接接觸的方式形成該第一和第二特徵的實施例,並且也包括了在該第一和第二特徵之間形成附加特徵的實施例,而這樣的該第一和第二特徵可以不是直接接觸的。另外,本揭露在不同示例中可重複參考數字和/或參考字母。該重複的目的在於簡明及清楚,但其本身不決定所描述的實施例和/或構造之間的關係。
此外,空間上的相關術語,諸如“在...的下面”、“在...的下方”、“低於”、“在...的上方”以及“上面”等,此處可用於簡單地描述如圖中所示的一個元件或特徵相對於另一(多個)元件或另一(多個)特徵的關係。該空間上的相關術語旨在包括除了圖中所描述的方向外,還包括在使用或操作中的元件的不同方向。另外,裝置可被定向(旋轉90度或以其它方向定向),並且此處所用的空間上的相關描述符號可同樣作相應地說明。
多層互連用於連接各種元件(電晶體、電阻器和電容等)以形成IC。圖1示出了典型的多層互連結構100。在典型的多層互連結構中,如圖1所示,導線102和104(例如,銅線)鋪設在堆疊的介電層108中,
並且通過孔106從一層(例如,103)連接至另一層(例如,105)。銅線和孔通常採用單鑲嵌或雙鑲嵌工藝製成。在這種工藝中,以版面圖形的方式成型襯底介電層以形成一種渠道,然後將銅填充并溢出該渠道,並且採用化學機械研磨(CMP)的方式移除多餘的銅,從而在渠道中形成銅線。隨後,在該襯底介電層之上形成另一介電層,並且重複上述工藝以形成孔和上層銅線。該多層介電層採用蝕刻微影技術(或黃光蝕刻微微影)工藝而形成板面圖形。有時,蝕刻微影技術工藝之間的堆疊誤差可導致孔與其需對準的銅線之間產生失準(例如,101)。失準的孔,例如孔106,可導致其與鄰近的銅線發生意外的橋接(短路),從而造成IC缺陷;或導致襯底介電層過度蝕刻,從而形成IC可靠度問題。這種孔-線失準的問題隨著IC持續小型化已變得更加難以解決。
本揭露提出了一種新的方式,該方式提供一種防止孔失準的導電特徵。例如,圖2示出了方法200,其用於在半導體基板上製造一種有助於防止孔失準的導電特徵。圖3A、3B、3C、3D、3E、3F和3G是根據圖2中方法200所製造的元件300的實施例的截面圖。應理解的是圖3A-3G和元件300只是典型的且示範性的。在一個實施例中,半導體元件300是互補金屬氧化物半導體(CMOS)元件的互連部分(例如,導線)。
此外,應理解的是方法200包括了具有互補金屬氧化物半導體(CMOS)技術工藝流程特徵的步驟,並且因此在此處只作簡要描述。其它步驟可在方法200之前、之後和/或在方法200期間實施。還應理解的是,半導體元件300的一部分,如圖3A-3G所示,可通过互補金屬氧化物半導體(CMOS)技術工藝流程製造而成,並且因此一些工藝在此處只作簡要描述。此外,半導體元件300可包括各種其它元件和特徵,諸如其它電晶體、雙極性結型電晶體、電阻器、電容、二極
體、熔斷器等,但為了更好地理解本揭露的發明構思而簡化了該半導體元件300。該半導體元件300包括多個可相互連接的的半導體元件(例如,電晶體)。
例如,元件300可以是在操作積體電路期間製造的中間元件,或者可以是以下一部分:其可包括靜態隨機存取記憶器(SRAM)和/或其它邏輯電路;諸如電阻器、電容和電感器的被動零件;以及諸如P型溝道場效電晶體(PFET)、N型溝道場效電晶體(NFET)、金屬氧化物半導體場效電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極型電晶體、高壓型電晶體、高頻型電晶體以及其它存儲單元的主動零件;和/或其組合。
方法200開始於方框202,即,提供包括導電層304和圖案化遮罩層310的基板301。在圖3A所示的實施例中,圖案化遮罩層310可包括位於導電層304上方的多個圖案化特徵。在一些特定的實施例中,基板301還可包括位於導電層下方的蝕刻終止(ETS)層302,和/或位於圖案化遮罩層310和導電層304之間的抗反射塗膜(ARC)層306。
更具體而言,根據多個實施例,導電層304可由任意適合的金屬材料(諸如銅(Cu)、鋁(Al)、鎢(W)和/或鈷(Co))製成。蝕刻終止層302包括具有密度高於導電層304材料的介電材料。例如,蝕刻終止層302可包括以下材料:該材料選自於由SiCN、SiCO、SiO2、SiN和/或AlON組成的組,同時,蝕刻終止層302也可使用其它適合的材料,並且其同樣屬於本揭露的範圍內。圖案化遮罩層310的圖案化特徵可包括光阻材料,或只包括阻劑材料。抗反射塗膜層306可由以下材料形成:該材料選自於由氧化矽、氮化矽和/或氮氧化矽組成的組。
參考圖2和圖3B,方法200繼續至方框204,即,在圖案化遮罩層310和抗反射層306上沉積第一介電層312。在一個實施例中,該第一介電層312可由以下材料形成:旋塗式玻璃(SOG)材料、旋塗式介電
(SOD)材料、樹脂材料、有機金屬聚合材料、氮化矽(SiN)、二氧化矽(SiO2)、非晶矽、碳基材料、氮化鈦(TiN)、氧化鈦(TiO)和/或氮化鉭(TaN)。此外,沉積該第一介電層312還包括旋塗式塗膜方法、化學蒸鍍(CVD)方法和/或原子層沉積(ALD)方法。
然後,方法200繼續至方框206,即,選擇性地蝕刻第一介電層312以形成凹陷的第一介電層312’。由此而暴露了圖案化遮罩層310的上表面。如圖3C所示的實施例,圖案化遮罩層310的上表面與圖案化遮罩層310朝向導電層304的底面相對。在一些特定的實施例中,第一介電層312所選擇的蝕刻可採用反應離子蝕刻(RIE)工藝實施,其用於調整凹陷第一介電層312,同時採用這樣的RIE工藝使圖案化遮罩層310基本上保持未改變/基本上保持完整。
方法200繼續至方框208,即,移除圖案化遮罩層310。如圖3D所示,在移除圖案化遮罩層310之後,暴露了抗反射層306的頂面(例如,340)。抗反射層306的暴露表面340包括相反的圖案化特徵,其與圖案化遮罩層310提供的圖案化特徵相反。即,現在暴露了抗反射層306頂面由圖案化特徵覆蓋的部分。因此,在一個實施例中,第一介電層312/312’可稱為“反向調整模式”材料。在一些特定的實施例中,移除圖案化遮罩層310可包括乾蝕刻、濕蝕刻和本領域熟知的各種適合的蝕刻工藝。
方法200繼續至方框210,即,如圖3E所示,通過暴露表面340選擇性地蝕刻抗反射層306、導電層304和/或蝕刻終止層302。在圖3E所示的實施例中,被蝕刻的導電層形成了具有楔形輪廓的導電特徵204’。在一個示例中,楔形輪廓可被實施為從底部(蝕刻終止層302)至頂部(抗反射層306)逐漸變小的導電特徵304’。更具體而言,如圖3E所示的實施例,導電特徵304’包括具有寬度為“W1”的較低部分以及寬度為“W2”的較高部分,並且W1大於W2。蝕刻導電層304可包括乾
蝕刻、電漿體基乾蝕刻和/或其它蝕刻工藝。在一個示例中,蝕刻導電層304可在流有化學製品的電漿體蝕刻腔室中實施,該化學製品諸如氟基氣體材料、氯基氣體材料和/或烷基氣體材料。
結合圖3F參考圖2,方法200繼續至方框212,即,在所形成的導電特徵304’上沉積第二介電層314。在一些特定的實施例中,該第二介電層314可以是低介電係數(例如,k<3.0)的介電材料,並且這種低介電係數的介電材料可採用旋塗式塗膜和/或CVD工藝沉積而成。第二介電層314可構造為與每一個形成的導電特徵隔離/絕緣。然後,方法200進入至方框214,即,實施化學機械研磨(CMP)工藝。該CMP工藝通過移除多餘的材料(例如,314)和導電材料(例如,304/304’)使元件300的頂面平坦化,從而使導電特徵304’的研磨表面和第二介電層314的研磨表面二者共面,如圖3G所示。
圖4示出了方法400,該方法400用於在半導體基板上製造有助於防止孔失準的導電特徵。圖5A、5B、5C、5D、5E、5F、5G、5H和5I是根據圖4中方法400所製造的元件400的實施例的截面圖。應理解的是圖5A-5I以及元件500只是典型的且示範性的。在一個實施例中,半導體元件500是互補性金屬氧化物半導體(CMOS)元件的互連部分(例如,導線)。
此外,應理解的是方法400包括了以下步驟:該步驟具有互補性金屬氧化物半導體(CMOS)技術工藝流程的特徵,且因此在此處只做簡要描述。其它步驟可在方法400前、后和/或方法400期間實施。還應理解的是,如圖5A-5I所示,半導體元件500的一部分可由互補性金屬氧化物半導體(CMOS)技術工藝流程製造,因此一些工藝在此處只做簡要描述。此外,半導體元件500可包括各種其它元件和特徵,諸如其它電晶體、雙極面結型電晶體、電阻器、電容、二極體、熔斷器等,但為了更好地理解本揭露的發明內容而將其簡化。半導體元件
500包括了可互連的多個半導體元件(例如,電晶體)。
例如,元件500可以是在操作積體電路期間製造的中間元件,或者可以是以下一部分:其可包括靜態隨機存取記憶器(SRAM)和/或其它邏輯電路;諸如電阻器、電容和電感器的被動零件;以及諸如P型溝道場效電晶體(PFET)、N型溝道場效電晶體(NFET)、金屬氧化物半導體場效電晶體(MOSFET)、互補性金屬氧化物半導體(CMOS)電晶體、雙極型電晶體、高壓型電晶體、高頻型電晶體以及其它存儲單元的主動零件;和/或其組合。
方法400開始於方框402,即,提供包括導電層504和圖案化遮罩層508的基板501。在圖5A所示的實施例中,圖案化遮罩層508可包括位於導電層504上方的多個圖案化特徵。在一些特定的實施例中,基板501還可包括位於導電層504下方的蝕刻終止層(ESL)502,和/或包括位於圖案化遮罩層508和導電層504之間的抗反射塗膜(ARC)層506。導電層504可由任意適合的金屬材料(諸如銅(Cu)、鋁(Al)、鎢(W)和/或鈷(Co))製成。蝕刻終止層502包括具有密度高於導電層504材料的介電材料。例如,蝕刻終止層502可包括以下材料:該材料選自於由SiCN、SiCO、SiO2、SiN和/或AlON組成的組,同時,蝕刻終止層502也可使用其它適合的材料,並且其同樣屬於本揭露的範圍內。圖案化遮罩層508的圖案化特徵可包括光阻材料,或只包括阻劑材料。抗反射塗膜層506可由以下材料形成:該材料選自於由氧化矽、氮化矽和/或氮氧化矽組成的組。
方法400繼續至方框402,即,在圖案化遮罩層508和抗反射塗膜層506上沉積襯料層510。根據各種所示實施例,沉積襯料層510包括採用各種適合的沉積方法,例如CVD方法、ALD方法和/或旋塗式塗膜方法。更具體而言,襯料層510由以下材料製成:該材料選自由定向自組裝材料、氮化鈦(TiN)、氧化鈦(TiO)、氮化鉭(TaN)、氮化矽
(SiN)、二氧化矽(SiO2)和有機金屬聚合材料組成的組。在一個特定的實施例中,襯料層的厚度範圍可在約¼跨距(pitch)至約1跨距之間。一般而言,跨距可以是定義為積體電路的兩個特徵(例如,互連線)之間的中心至中心的距離。
方法400繼續至方框404,即,在襯料層510上沉積第一介電層512。在一個實施例中,該第一介電層512可由以下材料形成:旋塗式玻璃(SOG)材料、旋塗式介電(SOD)材料、樹脂材料、有機金屬聚合材料、氮化矽(SiN)、二氧化矽(SiO2)、非晶矽、碳基材料、氮化鈦(TiN)、氧化鈦(TiO)和/或氮化鉭(TaN)。此外,沉積該第一介電層512還包括旋塗式塗膜方法、CVD方法和/或ALD方法。
然後,方法400繼續至方框406,即,選擇性地蝕刻第一介電層512以形成凹陷的第一介電層512’。由此而暴露了襯料層510的上表面。如圖5D所示的實施例,凹陷的第一介電層512’的上表面低於完整的襯料層510的上表面。在一些特定的實施例中,第一介電層512所選擇的蝕刻可採用反應離子蝕刻(RIE)工藝和/或電漿體蝕刻工藝實施,其用於調整凹陷第一介電層512,同時採用這樣的RIE工藝使襯料層510基本上保持未改變/基本上保持完整。
方法400繼續至方框408,即,選擇性地蝕刻襯料層510。如圖5E所示,蝕刻完整的襯料層510的一部分(例如,頂部部分),從而使被蝕刻的襯料層510’暴露圖案化遮罩層508的頂面。在一個實施例中,襯料層510所選擇的蝕刻可採用反應離子蝕刻(RIE)工藝和/或電漿體蝕刻工藝實施,其用於調整凹陷/蝕刻襯料層510,同時採用這樣的RIE工藝使圖案化遮罩層508基本上保持未改變/基本上保持完整。
方法400繼續至方框410,即,移除圖案化遮罩層508並且移除凹陷的第一介電層512’。如圖5F所示,在移除圖案化遮罩層508和凹陷的第一介電層512’之後,暴露了抗反射層506的頂面(例如,540)。抗
反射層506的暴露表面540包括相反的圖案化特徵,其與圖案化遮罩層508提供的圖案化特徵相反。即,現在暴露了抗反射層506頂面由圖案化特徵覆蓋的部分。因此,襯料層510’/510現可用作硬質遮罩層或簡單的遮罩層,其用於將圖案轉移至耦合層(例如,導電層504)。在一些特定的實施例中,移除圖案化遮罩層508可包括乾蝕刻、濕蝕刻和本領域熟知的各種適合的蝕刻工藝。
然後,方法400繼續至方框412,即,如圖5G所示,通過暴露表面540選擇性地蝕刻抗反射層506、導電層504和/或蝕刻終止層502。在圖5G所示的實施例中,被蝕刻的導電層形成了具有楔形輪廓的導電特徵504’,該楔形輪廓與圖3E中所論述的楔形輪廓相類似。即,導電特徵504’包括兩個傾斜的側壁,並且導電特徵504’的較低部分寬於導電特徵504’的較高部分。蝕刻導電層504可包括乾蝕刻、電漿體基乾蝕刻和本領域熟知的各種適合的金屬蝕刻工藝。在一個示例中,蝕刻導電層504可在流有化學製品的電漿體蝕刻腔室中實施,該化學製品諸如氟基氣體材料、氯基氣體材料和/或烷基氣體材料。在形成導電特徵504’之後,方法400可包括方框414,即,移除襯料層510’/510。在一些實施例中,移除襯料層可包括乾蝕刻、濕蝕刻和/或其它蝕刻工藝。
結合圖5H參考圖4,方法400繼續至方框416,即,在所形成的導電特徵504’上沉積第二介電層514。在一些特定的實施例中,該第二介電層514可以是低介電係數(例如,k<3.0)的介電材料,並且這種低介電係數的介電材料可採用旋塗式塗膜和/或CVD工藝沉積而成。此外,第二介電層514可構造為與每一個形成的導電特徵隔離/絕緣。然後,方法400進入至方框418,即,實施化學機械研磨(CMP)工藝。該CMP工藝通過移除多餘的材料(例如,514)和導電材料(例如,504/504’)使元件500的頂面平坦化,從而使導電特徵504’的研磨表面
和第二介電層514的研磨表面二者共面,如圖5I所示。
現參考圖6A和6B,其示出了分別由傳統方法(圖6A)和本揭露方法(圖6B)所形成的兩個導電特徵之間的比較。在一些實施例中,由傳統方法形成的每一個導電特徵603之間,可沉積低介電係數的介電材料(例如,601),從而使每一個導電特徵隔離。一般而言,為了形成導電特徵603,圖案化遮罩層(例如,硬質遮罩層)用於通過蝕刻工藝將圖案直接轉移至耦合的導電層,從而形成了用於後續填充低介電係數材料(例如,603)的蝕刻溝道或通道。如圖6A和6B所示,通過採用傳統方法,導電特徵603包括一傾斜的側壁,並且該側壁從頂部至底部逐漸減小(即,導電特徵的較高部分寬於導電特徵的較低部分)。換言之,導電特徵603包括了從頂部至底部逐漸減小的寬度。這種減小的寬度可造成多個問題。例如,多層互連用於連接各種元件(電晶體、電阻器、電容等)以形成IC。在一個典型的多層互連結構中,導線(例如,導電特徵603)鋪設在堆疊的介電層(例如,低介電係數的介電材料601)中並且通過孔從一層連接至另一層。一般而言,在導線上形成孔之前可使用化學機械研磨(CMP)。如果導線包括如603所示的(從頂部至底部)逐漸減小的寬度,則可產生孔的失準。失準的孔可導致其與鄰近的銅線發生意外的橋接(短路),從而造成IC缺陷;或導致襯底介電層過度蝕刻,從而形成IC可靠度問題。
因此,根據以上所論述的,本揭露提供各種有益效果。然而,應理解的是,不是所有此處所描述的全部有益效果都是必要的,其它實施例可提供不同的有益效果,並且所有實施例不要求具有特殊的有益效果。
本揭露的其中一個有益效果是:本揭露提出了一種新的方式,該方式提供一種從底部至頂部逐漸減小的導電特徵。重新參考圖6A和6B,由本揭露方法形成的導電特徵605(圖6B)與由傳統方法形成的
導電特徵(圖6A)形成了鮮明的對比,導電特徵605包括從頂部至底部逐漸增大的寬度。導電特徵的這種(從頂部至底部)逐漸增大的寬度有效地提供了額外的靈活性,從而即使在發生孔失準的情況下也可形成孔。如上所述,CMP工藝通常用於研磨/磨平半導體特徵的表面,並且通常在形成孔之前實施。如果一個半導體特徵包括了從頂部至底部增大的寬度,那麼即使在由CMP工藝研磨之後實施,這種半導體特徵也能由此而提供用於形成孔的基板面。本發明的另一個有益效果是提供了包括完整的低介電係數的介電材料,其構造為與每一個耦合的導電特徵相隔離。通常,低介電係數的介電材料容易受到蝕刻步驟(例如,電漿體蝕刻)的損壞,因為在傳統方法中,這種低介電係數的介電材料是在填充導電材料之前通過蝕刻步驟而形成,從而形成所希望的導電特徵。受損的介電材料可使所製造的IC性能受到不良的影響。然而,在本揭露的實施例中,低介電係數的介電材料(例如,314、514、607)是在形成導電特徵之後形成(沉積)。因此,通過本揭露的方法而形成的低介電係數的介電材料不會受到蝕刻工藝而引起的損壞。
本揭露提供一種用於形成導電特徵的方法的實施例。該方法包括在導電層上形成圖案化的遮罩層;在圖案化遮罩層上形成第一介電層;移除第一介電層的一部分,以暴露圖案化遮罩層的一部分;移除圖案化遮罩層的該部分;以及移除導電層的該部分,以形成具有楔形輪廓的導電特徵。
本揭露提供一種用於形成導電特徵的方法的另一實施例。該方法包括在導電層上形成圖案化遮罩層;在圖案化遮罩層上形成襯料層;在襯料層上形成第一介電層;移除第一介電層和襯料層的該部分,以暴露圖案化遮罩層的該部分;移除圖案化遮罩層的該部分;以及移除導電層的該部分,以形成具有楔形輪廓的導電特徵。
本揭露還提供了形成導電特徵的方法的另一實施例。該方法包
括在導電層上形成圖案化遮罩層;在圖案化遮罩層和導電層上形成第一介電層;選擇性地蝕刻第一介電層,由此而暴露圖案化遮罩層的上表面,其中第一介電層的上表面低於第一圖案化遮罩層的頂面;移除圖案化遮罩層;以及選擇性地蝕刻導電層,以形成具有楔形輪廓的導電特徵。
上述概括了幾個實施例的特徵,從而使本領域技術人員可以更好地理解本揭露的各方面。本領域技術人員應理解的是,其可容易地將本揭露作為設計或修改其它工藝的基礎,從而達到此處所引用的實施例的相同目的和/或實現相同的有益效果。本領域技術人員還應理解的是,這種等同的構造不能背離本揭露的精神和範圍,並且在不背離本揭露的精神和範圍的情況下可進行各種改變、替換和更改。
100‧‧‧多層互連結構
101‧‧‧失準
102、104‧‧‧導線
103、105‧‧‧堆疊的介電層中的一層
106‧‧‧孔
108‧‧‧堆疊的介電層
Claims (10)
- 一種形成導電特徵的方法,包括:在導電層上形成圖案化遮罩層;在該圖案化遮罩層上形成第一介電層;移除該第一介電層的一部分,以暴露該圖案化遮罩層的一部分;移除該圖案化遮罩層的該部分;以及將第一介電層作為遮罩以移除該導電層的一部分,藉以形成具有楔形輪廓的導電特徵。
- 根據權利要求1所述的方法,其中該導電特徵具有頂部部分和底部部分,該頂部部分具有第一寬度,並且該底部部分具有大於該第一寬度的第二寬度。
- 根據權利要求1所述的方法,還包括在該已形成的導電特徵上沉積第二介電層;以及實施化學機械研磨(CMP)於該第二介電層和該已形成的導電特徵上。
- 一種形成導電特徵的方法,包括:在導電層上形成圖案化遮罩層;在該圖案化遮罩層上形成襯料層;在該襯料層上形成第一介電層;移除該第一介電層和該襯料層的一部分,以暴露該圖案化遮罩層的一部分;移除該圖案化遮罩層的該部分;以及將第一介電層作為遮罩以移除該導電層的一部分,藉以形成具有楔形輪廓的導電特徵。
- 根據權利要求4所述的方法,還包括在該已形成的導電特徵上沉積第二介電層,其中第二介電層由低介電係數的介電材料形成。
- 根據權利要求4所述的方法,其中選擇性地蝕刻該第一介電層包括移除該第一介電層的一部分,從而使該蝕刻的第一介電層的頂面低於該襯料層的頂面。
- 一種形成導電特徵的方法,包括:在導電層上形成圖案化遮罩層;在圖案化遮罩層和該導電層上形成第一介電層;選擇性地蝕刻該第一介電層,由此而暴露該圖案化遮罩層的上表面,其中該第一介電層的上表面低於該圖案化遮罩層的頂面;移除該圖案化遮罩層,以及將第一介電層作為遮罩以選擇性地蝕刻該導電層,藉以形成具有楔形輪廓的導電特徵。
- 根據權利要求7所述的方法,還包括在該被蝕刻的導電層上沉積第二介電層,由此而填充在該導電層中的孔。
- 根據權利要求7所述的方法,其中該第一介電質層由以下至少一種方式形成:旋塗式玻璃材料、旋塗式介電材料、樹脂材料、有機金屬聚合材料、氮化矽(SiN)、二氧化矽(SiO2)、非晶矽、碳基材料、氮化鈦(TiN)、氧化鈦(TiO)和/或氮化鉭(TaN)。
- 根據權利要求7所述的方法,其中該基板包括蝕刻終止層(ESL),該蝕刻終止層設置在該導電層下方。
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