201123264 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體雙重圖案化製程，特別是 有關於一種製作小於微影製程極限的圖案的半導體雙重圖 案化製程。 【先前技術】 動態隨機存取記憶體（Dynamic Random Access Memory，DRAM)屬於一種揮發性記憶體（v〇iatiie memory)’主要的作用原理是利用電容内儲存電荷的多寡來 代表一個二進位位元(bit)是1還是〇，以儲存賢料。為達到 向达、度的要求’目前最有效的方法是透過縮小製造製程和 採用單元設計技術來減小晶片的尺寸。減小晶片尺寸的另 一種方法疋實現更為有效的陣列架構，在連續幾代發展 後’儲存技術通常會變成某種單元佈局的限制，單元尺寸 的每一次改善都需要進行大量的工作來減少蝕刻的最小尺 寸。 因此，亟需一種新穎的半導體圖案化製程，以有效地 縮小單元尺寸。 【發明内容】 有鑑於此，本發明之一實施例係提供一種半導體雙重 圖案化製程，包括於-基板上依序形成一被圖案化層，一 非晶碳層和-光阻層；進行-微影步驟，形成複數^光阻 圖案，其中上述些光阻圖案皆具有—第—寬度；移 9095-A34490TWF 4 201123264 上述些光阻圖案覆蓋的上述非晶碳層，以形成複數個非晶 碳圖案；於上述些非晶碳圖案的側壁上形成複數個絕緣間 隙壁，其中上述些絕緣間隙壁皆具有一第二寬度；移除上 述些非晶碳圖案；移除未被上述些絕緣間隙壁覆蓋的上述 被圖案化層。 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範 例，做為本發明之參考依據。在圖式或說明書描述中，相 似或相同之部分皆使用相同之圖號。且在圖式中，實施例 之形狀或是厚度可擴大，並以簡化或是方便標示。再者， 圖式中各元件之部分將以分別描述說明之，值得注意的 是，圖中未繪示或描述之元件，為所屬技術領域中具有通 常知識者所知的形式，另外，特定之實施例僅為揭示本發 明使用之特定方式，其並非用以限定本發明。 第1〜10圖係顯示本發明實施例之半導體雙重圖案化 製程的剖面示意圖。本發明實施例之半導體雙重圖案化製 程係將光阻圖案轉移至一非晶碳層上形成非晶碳 (amorphous carbon，α-C)圖案，再於其上形成絕緣間隙壁 做為蝕刻遮罩來蝕刻被圖案層，由於非晶碳圖案的特徵間 距(feature pitch)在形成絕緣間隙壁的高溫製程中不會因高 溫而收縮，因而形成的絕緣間隙壁可具有較光阻圖案更小 且更為穩定的特徵間距(feature pitch)。另外，相較於習知 利用雙重曝光步驟完成的雙重圖案化製程，本發明實施例 之半導體雙重圖案化製程僅利用一道曝光步驟，可以簡化 9095-A34490TWF 5 201123264 避免因對準不佳或絲圖案尺寸補定造成的可 靠度下降。 Μ $ 1 ^ ’可利用物理氣相沉積法(PVD)或化學 亂目、’儿積法(CVD)等薄膜沉積方式，於—基板2〇〇上依序 形成被圖案化層202、_第一硬遮罩層2〇4、一第二硬遮 罩層2〇i第-蝕刻停止層208、-非晶碳層.210、一第 触亥Ητ止層212、-抗反射層214和—光阻層216。在本 發明實施例中，可因被圖案化層搬最終形成_的高寬 比而選擇性形成上述第一硬遮罩層2〇4、第二硬遮罩層 2〇6第姓刻停止層208或第二蝕刻停止層2丨2。在本實 施例中，第-硬遮罩層2〇4和第二硬遮罩層施可為不同 的材料，例如第一硬遮罩層2〇4可為氮化矽層，第二硬遮 罩層206可為非晶碳層。在本實施例中，第一蝕刻停止層 208和第二蝕刻停止層212可為氮氧化矽層。在本實施例 中，形成非晶碳層210的製程溫度可介於300°c〜了⑼它之 間。 接著，請參考第2圖，進行一微影步驟，形成複數個 光阻圖案216a’其中光阻圖案216a皆具有一第一寬度Wl。 在本發明實施例中，第一寬度的最小尺寸可為微影步驟 的關鍵尺寸，而光阻圖案216a具有週期性，且具有特徵間 距(feature pitcl^P]。 然後’請參考第3圖’可進行一非等向性钱刻步驟， 移除未被光阻圖案216a覆蓋的第二餘刻停止層212和非晶 碳層210 ’直到露出第一钱刻停止層208，以形成第二蚀刻 停止層圖案212a和非晶碳圖案210a。如第3圖所示，非晶 9095-A34490TWF 6 201123264 碳圖案210a皆具有第一寬度％。在非等向性敍刻步 行期間，光阻圖案216a也會被蝕刻而去除。 之後’請參考第4目，可利用物理氣相沉積法$ 或化學氣相沉積法(CVD)等薄膜沉積方式，順應性 絕緣層218’覆蓋第一姓刻停止層2〇8、第二餘刻停止層圖 案212a和非晶碳圖案21〇a。在本發明實施例中，覆蓋第一 侧停止層208側壁的絕緣層218具有一第二寬度 值可大於或等於第一寬度Wi。 、 接著，请參考第5圖，可進行一回蝕刻步驟，以於非 晶碳圖案21〇a的側壁上，自對準地形成複數個絕緣間隙壁 218a，並露出第一蝕刻停止層2〇8和第二蝕刻停止層圖案 212a。在本發明實施例中，形成於相鄰兩個第一蝕刻停止 層208側壁上的絕緣間隙壁⑽彼此之間可具有一間距 S ’其值可以等於第一寬度I，因此，絕緣間隙壁218a也 具有週期性。 然後，請參考第6圖，可再進行一回蝕刻步驟，移除 第一蝕刻停止層圖案212a和部分第一姓刻停止層208，直 到露出非晶碳圖案210a的頂面，以於未被非晶碳圖案21〇a 和絕緣間隙壁218a覆蓋的第一蝕刻停止層2〇8中形成凹陷 220。 之後，請參考第7圖，可利用電漿灰化法(plasma ashing) ’移除非晶碳圖案21 〇a。在本發明一實施例中，上 述電漿灰化法(plasma ashing)的電漿可包括氮電漿或氧電 漿。如第7圖所示，週期性的絕緣間隙壁218a具有特徵間 距(feature pitch)P；2。在本發明一實施例中，絕緣間隙壁2i8a 9095-A34490TWF 7 201123264 的特徵間距p2小於如筮0 __ P > ^1^4, 第圖所示之光阻圖案216a的特徵 明間距p2可為特徵間距A的二分之-。 進行。例中，第5〜7圖所示的製程可在同-機台 請參考第8圖，可進行—祕刻步驟，以移除 1二:218a的側壁上的例如原生氧化物(natwe 非等向性_㈣，難土 綱硬解，進订一 ㈣^ 未被絕緣間隙壁218a覆蓋的第一 餘亥丨分止層208，直到露出笔一说 個第-_停止\遮罩層施，以形成複數 m Λ a。此時，絕緣間隙壁應的第 一寬又W2係寸於第一寬度w】和間距s。 然^請參考第9圖’再利用絕緣間隙壁2他和第一 触刻停止層圖㈣8續為钱刻硬遮罩，進行—非等向㈣ 刻步驟’移除未被絕緣間隙壁論覆蓋的第 以形成複數個第二硬遮罩圖案2(^如第9圖所^ 第一硬遮罩圖案2〇6a與其上的絕緣間隙壁218a具有相同 的寬度W2和特徵間距p2。 明參考第1〇圖，再利用絕緣間隙壁⑽& -=停止層圖案2〇8a和第二硬遮軍圖案寫&做為_ T笛進行一非等向性飯刻步驟，移除未被陶隙壁 218—a、第-钱刻停止層圖案遞a和第二硬遮罩圖案 覆盖的第—硬遮罩層綱，以形成複數個第-硬遮罩圖案 2〇r=後，可進行-乾#刻步驟，同時移除絕緣間隙壁 218a和第一蝕刻停止層圖案2〇8a。接著，可利用包括氮電 漿或氧電漿的電襞灰化法(plasma ashing),移除非晶碳材質BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor double patterning process, and more particularly to a semiconductor dual patterning process for fabricating patterns that are less than the lithography process limit. [Prior Art] Dynamic Random Access Memory (DRAM) belongs to a kind of volatile memory (v〇iatiie memory). The main principle of operation is to use the amount of charge stored in the capacitor to represent a binary bit. (bit) is 1 or 〇 to store the good. In order to meet the requirements of reach, the most effective method is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the wafer is to implement a more efficient array architecture. After several generations of development, the storage technology usually becomes a limitation of a certain cell layout. Every improvement in cell size requires a lot of work to reduce etching. The smallest size. Therefore, there is a need for a novel semiconductor patterning process to effectively reduce cell size. SUMMARY OF THE INVENTION In view of the above, an embodiment of the present invention provides a semiconductor double patterning process, including sequentially forming a patterned layer, an amorphous carbon layer and a photoresist layer on a substrate; a lithography step of forming a plurality of photoresist patterns, wherein each of the photoresist patterns has a first-width; and the above-mentioned amorphous carbon layer covered by the photoresist pattern is formed by the above-mentioned photoresist pattern to form a plurality of amorphous carbons. a plurality of insulating spacers are formed on sidewalls of the amorphous carbon patterns, wherein the insulating spacers have a second width; removing the amorphous carbon patterns; removing the insulating spacers The above patterned layer covered. BEST MODE FOR CARRYING OUT THE INVENTION The following is a detailed description of the embodiments and the accompanying drawings are intended to be a reference for the present invention. In the drawings or the description of the specification, the same drawing numbers are used for the similar or identical parts. Also, in the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. Figs. 1 to 10 are schematic cross-sectional views showing a semiconductor double patterning process according to an embodiment of the present invention. The semiconductor double patterning process of the embodiment of the present invention transfers the photoresist pattern onto an amorphous carbon layer to form an amorphous carbon (α-C) pattern, and then forms an insulating spacer thereon as an etch mask. To etch the patterned layer, since the characteristic pitch of the amorphous carbon pattern does not shrink due to high temperature in a high-temperature process for forming the insulating spacer, the formed insulating spacer may have a smaller and more resistive pattern than the photoresist pattern. For a stable feature pitch. In addition, the semiconductor double patterning process of the embodiment of the present invention can be simplified by using only one exposure step, which can simplify 9095-A34490TWF 5 201123264, avoiding poor alignment or silk pattern, compared to the conventional double patterning process which is completed by the double exposure step. The reliability caused by the size compensation is reduced. Μ $ 1 ^ 'The patterned layer 202 can be sequentially formed on the substrate 2 by means of physical vapor deposition (PVD) or chemical filming, CVD or other thin film deposition methods. A hard mask layer 2〇4, a second hard mask layer 2〇i first-etch stop layer 208, an amorphous carbon layer 210, a first touch stop layer 212, an anti-reflection layer 214, and Photoresist layer 216. In the embodiment of the present invention, the first hard mask layer 2〇4 and the second hard mask layer 2〇6 may be selectively formed due to the aspect ratio of the patterned layer being finally formed. 208 or a second etch stop layer 2丨2. In this embodiment, the first hard mask layer 2〇4 and the second hard mask layer may be made of different materials, for example, the first hard mask layer 2〇4 may be a tantalum nitride layer, and the second hard mask layer The cover layer 206 can be an amorphous carbon layer. In the present embodiment, the first etch stop layer 208 and the second etch stop layer 212 may be a hafnium oxynitride layer. In the present embodiment, the process temperature for forming the amorphous carbon layer 210 may be between 300 ° C and ( 9 ). Next, referring to FIG. 2, a lithography step is performed to form a plurality of photoresist patterns 216a', wherein the photoresist patterns 216a each have a first width W1. In the embodiment of the present invention, the minimum size of the first width may be a critical dimension of the lithography step, and the photoresist pattern 216a has periodicity and has a feature pitch (feature pitcl^P]. Then 'Please refer to FIG. 3' An anisotropic engraving step may be performed to remove the second residual stop layer 212 and the amorphous carbon layer 210' that are not covered by the photoresist pattern 216a until the first stop layer 208 is exposed to form a second etch. The layer pattern 212a and the amorphous carbon pattern 210a are stopped. As shown in Fig. 3, the amorphous 9095-A34490TWF 6 201123264 carbon pattern 210a has a first width %. During the anisotropic walking, the photoresist pattern 216a is also It will be removed by etching. After that, please refer to item 4, which can be covered by a thin film deposition method such as physical vapor deposition method or chemical vapor deposition (CVD), and the compliant insulating layer 218' covers the first-order stop layer 2 〇8, the second residual stop layer pattern 212a and the amorphous carbon pattern 21〇a. In the embodiment of the invention, the insulating layer 218 covering the sidewall of the first side stop layer 208 has a second width value greater than or equal to the first One width Wi., then, please refer to Figure 5. An etching step may be performed to form a plurality of insulating spacers 218a on the sidewalls of the amorphous carbon pattern 21〇a, and expose the first etch stop layer 2〇8 and the second etch stop layer pattern 212a. In the embodiment of the present invention, the insulating spacers (10) formed on the sidewalls of the adjacent two first etch stop layers 208 may have a spacing S' between them, and the value may be equal to the first width I. Therefore, the insulating gap The wall 218a also has a periodicity. Then, referring to FIG. 6, an etching step may be further performed to remove the first etch stop layer pattern 212a and a portion of the first surname stop layer 208 until the amorphous carbon pattern 210a is exposed. The top surface is formed with a recess 220 in the first etch stop layer 2〇8 which is not covered by the amorphous carbon pattern 21〇a and the insulating spacer 218a. Thereafter, referring to FIG. 7, the plasma ashing method can be utilized ( Plasma ashing) 'Removing the amorphous carbon pattern 21 〇a. In an embodiment of the invention, the plasma ashing plasma may include nitrogen plasma or oxygen plasma. As shown in FIG. It is shown that the periodic insulating spacers 218a have a feature pitch (fe A feature pitch) P; 2. In an embodiment of the invention, the insulating spacer 2i8a 9095-A34490TWF 7 201123264 has a characteristic pitch p2 smaller than 筮0 __ P > ^1^4, the photoresist pattern 216a shown in the figure The characteristic clear pitch p2 can be the binary of the feature pitch A. In the example, the process shown in the fifth to seventh steps can be in the same machine, please refer to the eighth figure, and the secret process can be performed to move Except for the primary oxides on the sidewalls of the first two: 218a (natwe non-isotropic _ (four), hard soil hard solution, order one (four) ^ first 丨 丨 丨 208 208 208 without the insulating spacer 218a Until the pen is exposed, say the first - _ stop \ mask layer to form a complex number m Λ a. At this time, the first width and the W2 of the insulating spacer should be in the first width w and the spacing s. However, please refer to Figure 9 'Reusing the insulating spacer 2 and the first etch stop layer diagram (4) 8 continued as a hard mask, proceeding - non-isotropic (four) engraving step 'removal without insulation spacer theory First, a plurality of second hard mask patterns 2 are formed (the first hard mask pattern 2〇6a has the same width W2 and feature pitch p2 as the insulating spacers 218a thereon. 1 , , 再 , , 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘The wall 218-a, the first-money stop layer pattern and the second hard mask pattern cover the first hard mask layer to form a plurality of first-hard mask patterns 2〇r=, then - The dry etching step removes the insulating spacer 218a and the first etch stop layer pattern 2〇8a. Then, the amorphous ashing method including nitrogen plasma or oxygen plasma can be used to remove the amorphous Carbon material
9095-A34490TWF 201123264 的第二硬遮Π，。然後’可再進行一乾姓刻步驟， 以移除位於第一硬遮罩圖牵9 w 系204a的側壁上的例如原生氧 化物(native oxide)。之後，再利用第一 為蝕刻硬遮罩，進行一非等向茅U4a做 F寻向性蝕刻步驟，移除未 硬遮罩圖案204a覆蓋的被圖宏 ^ 宏她日同宏709 層2〇2,以形成複數個圖 的寬度w2和特徵間距！V二，_218&具有相同 被圖案化層逝。 4上述製程之後，係圖案化9095-A34490TWF The second hard cover of 201123264. Then, a dry-step process can be performed to remove, for example, a native oxide on the sidewall of the first hard mask. Then, the first is to etch the hard mask, and a non-isotropic U4a is subjected to the F-direction etching step, and the un-hard mask pattern 204a is removed to be covered by the macro 2 macro 709 layer 2 〇 2, to form the width w2 and feature spacing of the multiple figures! V 2, _218 & have the same patterned layer. 4 after the above process, the patterning
本發明實施例提供一種丰宴 成小於微影製程極限的圖宰，1 _圖-化1I ’以形 高溫製程(職〜職)所光阻圖案轉移至經由 , u 小成的一非晶碳層上，以形成非 晶碳（amorphous carbon，a_r、m 电 則’再於其上形成厚度約 ί 絕緣間隙壁做為蝴罩來姓刻 «㈣’ •非晶碳圖案_特徵間距(feature pitch)在 形成絕緣間隙壁的高溫製程中不會因高溫而收縮，因而絕 緣間隙壁可具有精確的間距和特徵間距(feature pitch)，且 絕緣間隙壁的特徵間距（feature pitch)可以小於微影製程的 極限（即光阻圖案的最小特徵間距）。另外，相較於習知利 用雙重曝光步驟完成的雙重圖案化製程，本發明實施例之 半導體雙重圖案化製程僅利用一道曝光步驟即可完成小於 微影製程極限的蝕刻遮罩，可以大為簡化製程，且避免因 對準不佳或光阻圖案尺寸不穩定造成的可靠度下降。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍内，當可作些許之更動與潤飾，因此本發明之保護範圍 9095-A34490TWF 9 201123264 當視後附之申請專利範圍所界定為準。 【圖式簡單說明】 第1〜10圖係顯示本發明實施例之半導體雙重圖案化 製程的剖面示意圆。 【主要元件符號說明】 2 00〜基板， 202〜被圖案化層； 2 02 a〜圖案， 2〇4〜第一硬遮罩層； 204a〜第一硬遮罩圖案； 206〜第二硬遮罩層； 206a〜第二硬遮罩圖案； 208〜第一蝕刻停止層； 208a〜第一蝕刻停止層圖案； 210〜非晶碳層； 210a〜非晶碳層圖案， 212〜第二蝕刻停止層； 212a〜第二蝕刻停止層圖案； 214〜抗反射層； 216〜光阻層； 216 a〜光阻圖案； 218〜絕緣層； 218a〜絕緣間隙壁；Embodiments of the present invention provide a graph of a feast that is less than the limit of the lithography process, and a photoresist pattern of a high-temperature process (a job-to-job) is transferred to an amorphous carbon via a small-sized process. On the layer, to form amorphous carbon (a_r, m electric' and then form a thickness of about ί. The insulating spacer is used as a butterfly cover to name «(4)' • amorphous carbon pattern_feature pitch In the high-temperature process of forming the insulating spacer, it does not shrink due to high temperature, so the insulating spacer can have precise pitch and feature pitch, and the feature pitch of the insulating spacer can be smaller than the lithography process The limit (ie, the minimum feature spacing of the photoresist pattern). In addition, the semiconductor double patterning process of the embodiment of the present invention can be completed by using only one exposure step compared to the conventional double patterning process which is completed by the double exposure step. The etch mask of the lithography process limit can greatly simplify the process and avoid the reliability degradation caused by poor alignment or unstable size of the photoresist pattern. The above disclosure is not intended to limit the invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention 9095-A34490TWF 9 201123264 The scope of the patent application is defined as follows. [Simplified Schematic Description] Figures 1 to 10 show cross-sectional schematic circles of a semiconductor double patterning process according to an embodiment of the present invention. [Description of Main Components] 2 00~ Substrate, 202~patterned layer; 2 02 a~ pattern, 2〇4~first hard mask layer; 204a~first hard mask pattern; 206~second hard mask layer; 206a~second hard mask a mask pattern; 208 to a first etch stop layer; 208a to a first etch stop layer pattern; 210 to an amorphous carbon layer; 210a to an amorphous carbon layer pattern, 212 to a second etch stop layer; 212a to a second etch stop layer Pattern; 214~ anti-reflective layer; 216~ photoresist layer; 216 a~ photoresist pattern; 218~ insulating layer; 218a~ insulating spacer;
9095-A34490TWF 2011232649095-A34490TWF 201123264
220〜凹陷； W1〜第一寬度； W2〜第二寬度；220~ recessed; W1~first width; W2~second width;
Pi〜第一特徵間距； P2〜第二特徵間距； S〜間距。Pi~first feature spacing; P2~second feature spacing; S~ spacing.
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