JP2012054359A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

Info

Publication number
JP2012054359A
JP2012054359A JP2010195026A JP2010195026A JP2012054359A JP 2012054359 A JP2012054359 A JP 2012054359A JP 2010195026 A JP2010195026 A JP 2010195026A JP 2010195026 A JP2010195026 A JP 2010195026A JP 2012054359 A JP2012054359 A JP 2012054359A
Authority
JP
Japan
Prior art keywords
rewiring
wiring
semiconductor device
surface layer
barrier metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010195026A
Other languages
English (en)
Inventor
Tatsuo Uda
達夫 右田
Hirokazu Ezawa
弘和 江澤
Soichi Yamashita
創一 山下
Shinya Shima
真也 志摩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2010195026A priority Critical patent/JP2012054359A/ja
Priority to TW100128611A priority patent/TWI576974B/zh
Priority to CN201110254765.4A priority patent/CN102386147B/zh
Priority to US13/222,332 priority patent/US9190373B2/en
Publication of JP2012054359A publication Critical patent/JP2012054359A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05019—Shape in side view being a non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05149—Manganese [Mn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

【課題】再配線間のリークを抑制しつつ、再配線のピッチを微細化するとともに、再配線上のビア開口時のマージンを上げる。
【解決手段】緩衝層４上には再配線７ｂが形成され、再配線７ｂ上には表面層８ｂが形成されている。表面層８ｂは、再配線７ｂから幅方向にはみ出すようにして再配線７ｂに沿うように配置され、再配線７ｂよりもエッチング耐性が高い。
【選択図】 図２

Description

本発明の実施形態は半導体装置および半導体装置の製造方法に関する。
半導体デバイスの高集積化と高機能化を達成するために、動作速度の向上やメモリの大容量化が要求されている。それに合わせて半導体基板上の再配線形成プロセスにおいても、１０ｕｍピッチ以下の微細な再配線が要求されている。
再配線のピッチが微細化すると、再配線間でリークが発生する恐れがあった。また、再配線上にさらに配線やバンプ等を形成する際のマージンが減少し、フォトリソグラフィーによる加工が困難になっていた。
特開２００５−１０９１１０号公報
本発明の一つの実施形態の目的は、再配線間のリークを抑制しつつ、再配線のピッチを微細化するとともに、再配線上のビア開口時のマージンを上げることが可能な半導体装置および半導体装置の製造方法を提供することである。
実施形態の半導体装置によれば、半導体基板と、再配線と、表面層とが設けられている。半導体基板は、配線およびパッド電極が形成されている。再配線は、前記半導体基板上に形成されている。表面層は、前記再配線よりも幅の広いことを特徴とする。
図１（ａ）〜（ｅ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図２（ａ）〜（ｄ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図３（ａ）〜（ｃ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図４（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図５（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図６（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図７は、第２実施形態に係る半導体装置の概略構成を示す断面図である。
以下、実施形態に係る半導体装置および半導体装置の製造方法について図面を参照しながら説明する。なお、これらの実施形態により本発明が限定されるものではない。
（第１実施形態）
図１〜図６は、第１実施形態に係る半導体装置の製造方法を示す断面図である。
図１（ａ）において、基材層１上には、パッド電極２ａおよび配線２ｂが形成されるとともに、パッド電極２ａおよび配線２ｂが覆われるようにして保護膜３が形成されている。また、保護膜３には、パッド電極２ａを露出させる開口部３ａおよび配線２ｂの一部を露出させる開口部３ｂが形成されている。
なお、基材層１としては、例えば、ロジック回路またはＤＲＡＭなどの集積回路が形成された半導体基板を用いることができる。また、パッド電極２ａおよび配線２ｂの材料は、例えば、ＡｌまたはＡｌを主成分とした金属を用いることができる。また、保護膜３の材料は、例えば、シリコン酸化膜またはシリコン酸窒化膜またはシリコン窒化膜などの絶縁体を用いることができる。
次に、図１（ｂ）に示すように、感光性樹脂などを保護膜３上に塗布することにより、保護膜３上に緩衝層４を形成する。なお、緩衝層４の材料としては、例えば、ポリイミド系樹脂を用いることができる。ウェハストレスを低減させるために、ポリイミド系樹脂よりも硬化温度の低いアクリル系樹脂またはフェノール系樹脂を用いるようにしてもよい。
次に、図１（ｃ）に示すように、フォトリソグラフィー技術を用いることにより、パッド電極２ａおよび配線２ｂの一部をそれぞれ露出させる開口部４ａ、４ｂを緩衝層４に形成する。
次に、図１（ｄ）に示すように、スパッタ、メッキ、ＣＶＤ、ＡＬＤまたは蒸着などの方法を用いることにより、パッド電極２ａ、配線２ｂ、保護膜３および緩衝層４上にアンダーバリアメタル膜５を形成する。なお、アンダーバリアメタル膜５としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。なお、Ｔｉの代わりに、ＴｉＮ、ＴｉＷ、Ｗ、Ｔａ、Ｃｒ、Ｃｏ等の材料を使用することもできる。Ｃｕの代わりに、Ａｌ、Ｐｄ、Ａｕ、Ａｇ等の材料を使用することもできる。
次に、図１（ｅ）に示すように、スピンコートなどの方法を用いることにより、アンダーバリアメタル膜５上にレジスト膜６を形成する。
次に、図２（ａ）に示すように、レジスト膜６の露光および現像を行うことにより、開口部６ａ〜６ｃをレジスト膜６に形成する。なお、開口部６ａは、パッド電極２ａ上に配置し、開口部６ｂは、緩衝層４上に配置し、開口部６ｃは、配線２ｂ上に配置することができる。
次に、図２（ｂ）に示すように、電解メッキにて第１の導体を開口部６ａ〜６ｃに埋め込むことにより、アンダーバリアメタル膜５を介してパッド電極２ａ、緩衝層４および配線２ｂ上に再配線７ａ〜７ｃをそれぞれ形成する。さらに、電解メッキにて第２の導体を開口部６ａ〜６ｃに埋め込むことにより、再配線７ａ〜７ｃ上に表面層８ａ〜８ｃをそれぞれ形成する。ここで、再配線７ａは、パッド電極２ａとの接続に使用することができる。再配線７ｃは、配線２ｂとの接続に使用することができる。再配線７ｂ、緩衝層４上での再配線７ａ、７ｃの引き回しなどに使用することができる。
なお、表面層８ａ〜８ｃは再配線７ａ〜７ｃよりもエッチング耐性の高い材料を用いることができ、表面層８ａ〜８ｃに対する再配線７ａ〜７ｃのエッチング選択比は１以上であることが望ましい。例えば、再配線７ａ〜７ｃの材料は、ＣｕまたはＣｕを主成分とする金属、表面層８ａ〜８ｃの材料は、Ｍｎ、Ｔａ、Ｎｉ、Ｚｎ、Ｃｒ、Ｃｏ、ＳｎおよびＰｂのうちの少なくともいずれか１つから選択することができる。また、再配線７ａ〜７ｃの幅は、６０μｍ以下、好ましくは４０μｍ以下、さらに好ましくは２０μｍ以下であることが望ましい。
次に、図２（ｃ）に示すように、アッシングなどの方法により、アンダーバリアメタル膜５上のレジスト膜６を除去する。
次に、図２（ｄ）に示すように、再配線７ａ〜７ｃの側面をエッチングすることにより、表面層８ａ〜８ｃよりも幅が狭くなるように再配線７ａ〜７ｃを細線化する。
ここで、表面層８ａ〜８ｃは再配線７ａ〜７ｃよりもエッチング耐性の高い材料を用いることにより、表面層８ａ〜８ｃに比べて再配線７ａ〜７ｃの側面のエッチングを促進することができる。このため、再配線７ａ〜７ｃにそれぞれ沿うようにして再配線７ａ〜７ｃからそれぞれ幅方向にはみ出すように表面層８ａ〜８ｃを再配線７ａ〜７ｃ上に形成することができる。
この時、再配線７ａ〜７ｃの側面をエッチングすると同時に、アンダーバリアメタル膜５をエッチングすることにより、再配線７ａ〜７ｃの周囲のアンダーバリアメタル膜５を除去するようにしてもよい。従って、表面層８ａ〜８ｃはアンダーバリアメタル膜５ともエッチング比があることが好ましい。
次に、図３（ａ）に示すように、感光性樹脂などを配線２ｂ、緩衝層４および表面層８ａ〜８ｃ上に塗布することにより、配線２ｂ、緩衝層４および表面層８ａ〜８ｃ上に緩衝層９を形成する。なお、緩衝層９の材料としては、例えば、ポリイミド系樹脂を用いることができる。ウェハストレスを低減させるために、ポリイミド系樹脂よりも硬化温度の低いアクリル系樹脂またはフェノール系樹脂を用いるようにしてもよい。
次に、図３（ｂ）に示すように、フォトリソグラフィー技術を用いることにより、パッド電極２ａ上の表面層８ａおよび配線２ｂの一部をそれぞれ露出させる開口部９ａ、９ｂを緩衝層９に形成する。
次に、図３（ｃ）に示すように、スパッタ、メッキ、ＣＶＤ、ＡＬＤまたは蒸着などの方法を用いることにより、配線２ｂ、保護膜３、緩衝層４、９および表面層８ａ上にアンダーバリアメタル膜１０を形成する。なお、アンダーバリアメタル膜１０としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。
次に、図４（ａ）に示すように、スピンコートなどの方法を用いることにより、アンダーバリアメタル膜１０上にレジスト膜１１を形成する。
次に、図４（ｂ）に示すように、レジスト膜１１の露光および現像を行うことにより、パッド電極２ａ上の表面層８ａを露出させる開口部１１ａをレジスト膜１１に形成する。
次に、図５（ａ）に示すように、電解メッキにてバリア層１２およびハンダ層１３、１４を開口部１１ａに順次埋め込むことにより、アンダーバリアメタル膜１０を介して表面層８ａ上に突出電極を形成する。なお、例えば、バリア層１２の材料はＮｉ、ハンダ層１３の材料はＣｕ、ハンダ層１４の材料はＳｎを用いることができる。
次に、図５（ｂ）に示すように、アッシングなどの方法により、アンダーバリアメタル膜１０上のレジスト膜１１を除去する。
次に、図６（ａ）に示すように、バリア層１２およびハンダ層１３、１４からなる突出電極をマスクとして、アンダーバリアメタル膜１０をエッチングすることにより、バリア層１２およびハンダ層１３、１４からなる突出電極の周囲のアンダーバリアメタル膜１０を除去する。
次に、図６（ｂ）に示すように、ハンダ層１３、１４をリフローすることにより、ハンダ層１３、１４を合金化し、バリア層１２上に合金ハンダ層１５を形成する。
以上の工程は基材層１がウェハの状態で行うことができる。そして、以上の工程の後、このウェハを個片化することより、半導体チップを切り出すことができる。
ここで、再配線７ａ〜７ｃを細線化することにより、再配線７ａ〜７ｃ間のリークを抑制しつつ、再配線７ａ〜７ｃのピッチを微細化することが可能となるとともに、再配線７ａ〜７ｃよりもそれぞれ幅の広い表面層８ａ〜８ｃを再配線７ａ〜７ｃ上にそれぞれ形成することにより、開口部９ａを再配線７ａ上に形成する時のマージンを上げることが可能となる。
また、再配線７ａ〜７ｃの周囲のアンダーバリアメタル膜５をエッチング除去するのと同時に再配線７ａ〜７ｃの細線化を行うことにより、工程数の増大を抑制することができる。
なお、上述した実施形態では、突出電極としてハンダボールを用いる方法について説明したが、ニッケルバンプ、金バンプまたは銅バンプなどを用いるようにしてもよい。また、上述した実施形態では、アンダーバリアメタル膜５、１０として、ＴｉとＣｕとの積層構造を用いる方法について説明したが、ＴｉまたはＣｕを単体で用いるようにしてもよいし、Ｃｒ、Ｐｔ、Ｗなどを単体として用いるようにしてもよし、これらの金属の積層構造を用いるようにしてもよい。
また、突出電極の接合方法としては、半田接合や合金接合などの金属接合を用いるようにしてもよいし、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などを用いるようにしてもよい。
（第２実施形態）
図７は、第２実施形態に係る半導体装置の概略構成を示す断面図である。
図７において、緩衝層２１上には、アンダーバリアメタル膜２２を介して再配線２３が形成され、再配線２３上には、表面層２４が形成されている。
なお、緩衝層２１の材料としては、例えば、ポリイミド系樹脂を用いることができる。ウェハストレスを低減させるために、ポリイミド系樹脂よりも硬化温度の低いアクリル系樹脂またはフェノール系樹脂を用いるようにしてもよい。また、アンダーバリアメタル膜２２としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。なお、Ｔｉの代わりに、ＴｉＮ、ＴｉＷ、Ｗ、Ｔａ、Ｃｒ、Ｃｏ等の材料を使用することもできる。Ｃｕの代わりに、Ａｌ、Ｐｄ、Ａｕ、Ａｇ等の材料を使用することもできる。
表面層２４は再配線２３よりもエッチング耐性の高い材料を用いることができる。例えば、再配線２３の材料はＣｕ、表面層２４の材料は、Ｍｎ、Ｔａ、Ｎｉ、Ｚｎ、Ｃｒ、Ｃｏ、ＳｎおよびＰｂのうちの少なくともいずれか１つから選択することができる。
また、再配線２３の断面形状は、トップ幅Ｂがボトム幅Ａよりも狭い台形状とすることができる。表面層２４の断面形状は、トップ幅Ｄがボトム幅Ｃよりも狭い台形状とすることができる。なお、再配線２３および表面層２４の断面形状を台形状とするために、再配線２３および表面層２４が埋め込まれるレジスト開口部の断面形状を逆台形状とすることができる。
ここで、表面層２４の幅は再配線２３のボトム幅Ａよりも広くなるように設定されている。また、｜Ａ−Ｂ｜＞｜Ｃ−Ｄ｜の関係を満たすことが好ましい。例えば、再配線２３の厚さは５μｍ、ボトム幅Ａは４μｍ、トップ幅Ｂは３μｍに設定することができる。表面層２４の厚さは０．１μｍ、ボトム幅Ｃは５μｍ、トップ幅Ｄは４．９８μｍに設定することができる。この時、｜Ａ−Ｂ｜は１μｍ、｜Ｃ−Ｄ｜は０．０２μｍとなる。
ここで、再配線２３の断面形状は、トップ幅Ｂがボトム幅Ａよりも狭い台形状とすることにより、再配線２３とその下地との密着強度を増大させることができ、再配線２３の剥がれを抑制しつつ、再配線２３の微細化を図ることができる。
また、表面層２４の幅は再配線２３のボトム幅Ａよりも広くなるように設定することで、上面から見た時に表面層２４によって再配線２３が見えなくなるようにすることができる。このため、ウェハ面内やウェハ間で再配線２３の側面の傾斜角にバラツキが発生する場合においても、上面から光を照射した時の反射光の輝度を均一化することができる。このため、このような反射光を用いて外観検査や寸法測長を行う場合においても、良品を誤って欠陥と判定する誤検出や、配線端の誤認識による誤測長を低減することができ、品質管理の精度を向上させることができる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１ 基材層、２ａ パッド電極、２ｂ 配線、３ 保護膜、３ａ、３ｂ、４ａ、４ｂ、６ａ〜６ｃ、９ａ、９ｂ、１１ａ 開口部、４、９、２１ 緩衝層、６、１１ レジスト膜、５、１０、２２ アンダーバリアメタル膜、７ａ〜７ｃ、２３ 再配線、８ａ〜８ｃ、２４ 表面層、１２ バリア層、１３、１４ ハンダ層、１５ 合金ハンダ層

Claims (7)

  1. 配線およびパッド電極が形成された半導体基板と、
    前記半導体基板上に形成された再配線と、
    前記再配線よりも幅の広い表面層とを備えることを特徴とする半導体装置。
  2. 前記表面層に対する前記再配線のエッチング選択比が１以上であることを特徴とする請求項１に記載の半導体装置。
  3. 前記再配線の材料はＣｕ、前記表面層の材料はＭｎ、Ｔａ、Ｎｉ、Ｚｎ、Ｃｒ、Ｃｏ、ＳｎおよびＰｂのうちの少なくともいずれか１つから選択されることを特徴とする請求項１または２に記載の半導体装置。
  4. 前記再配線のトップ幅はボトム幅よりも狭いことを特徴とする請求項１から３のいずれか１項に記載の半導体装置。
  5. 前記表面層の幅は前記再配線のボトム幅よりも広いことを特徴とする請求項４に記載の半導体装置。
  6. 半導体基板上にアンダーバリアメタル膜を形成する工程と、
    開口部を有するレジストパターンを前記アンダーバリアメタル膜上に形成する工程と、
    前記アンダーバリアメタル膜上に再配線を形成する工程と、
    前記再配線上に表面層を形成する工程と、
    前記再配線の側面をエッチングすることにより、前記表面層よりも幅を狭くする工程とを備えることを特徴とする半導体装置の製造方法。
  7. 前記再配線の側面をエッチングすると同時に、前記アンダーバリアメタル膜をエッチングすることにより、前記再配線の周囲の前記アンダーバリアメタル膜を除去することを特徴とする請求項６に記載の半導体装置の製造方法。
JP2010195026A 2010-08-31 2010-08-31 半導体装置および半導体装置の製造方法 Pending JP2012054359A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2010195026A JP2012054359A (ja) 2010-08-31 2010-08-31 半導体装置および半導体装置の製造方法
TW100128611A TWI576974B (zh) 2010-08-31 2011-08-10 Semiconductor device and method for manufacturing semiconductor device
CN201110254765.4A CN102386147B (zh) 2010-08-31 2011-08-31 半导体装置及半导体装置的制造方法
US13/222,332 US9190373B2 (en) 2010-08-31 2011-08-31 Bump structure with underbump metallization structure and integrated redistribution layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010195026A JP2012054359A (ja) 2010-08-31 2010-08-31 半導体装置および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JP2012054359A true JP2012054359A (ja) 2012-03-15

Family

ID=45696036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010195026A Pending JP2012054359A (ja) 2010-08-31 2010-08-31 半導体装置および半導体装置の製造方法

Country Status (4)

Country Link
US (1) US9190373B2 (ja)
JP (1) JP2012054359A (ja)
CN (1) CN102386147B (ja)
TW (1) TWI576974B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200004199A (ko) * 2018-07-03 2020-01-13 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074406A (ja) * 2010-09-03 2012-04-12 Toshiba Corp 半導体装置および半導体装置の製造方法
US9646942B2 (en) * 2012-02-23 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for controlling bump height variation
US8633117B1 (en) * 2012-11-07 2014-01-21 International Business Machines Corporation Sputter and surface modification etch processing for metal patterning in integrated circuits
CN104465574B (zh) * 2013-09-12 2017-09-26 中国科学院金属研究所 一种以FeP合金作为接焊层的凸点封装结构
JP6436531B2 (ja) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
TWI606771B (zh) 2015-04-01 2017-11-21 群創光電股份有限公司 顯示面板
CN106158902B (zh) * 2015-04-01 2019-11-01 群创光电股份有限公司 显示面板
US9418886B1 (en) * 2015-07-24 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming conductive features
US10797010B2 (en) * 2017-12-29 2020-10-06 Texas Instruments Incorporated Semiconductor package having a metal barrier
US11410947B2 (en) 2019-12-19 2022-08-09 Texas Instruments Incorporated Brass-coated metals in flip-chip redistribution layers

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629399A (ja) * 1992-07-09 1994-02-04 Toshiba Corp 半導体装置の製造方法
JP2001144223A (ja) * 1999-09-29 2001-05-25 Samsung Electronics Co Ltd 再配置チップサイズパッケージ及びその製造方法
JP2001217310A (ja) * 2000-02-02 2001-08-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003060031A (ja) * 2001-08-14 2003-02-28 Oki Electric Ind Co Ltd 半導体装置及びその製造方法。
JP2004071942A (ja) * 2002-08-08 2004-03-04 Denso Corp 電解めっきを用いた配線の形成方法
JP2006210406A (ja) * 2005-01-25 2006-08-10 Fujikura Ltd 配線とそれを備えた半導体装置
JP2010062178A (ja) * 2008-09-01 2010-03-18 Toyota Motor Corp 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3383329B2 (ja) * 1992-08-27 2003-03-04 株式会社東芝 半導体装置の製造方法
JP3502800B2 (ja) 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法
JP2002198374A (ja) * 2000-10-16 2002-07-12 Sharp Corp 半導体装置およびその製造方法
US6489229B1 (en) * 2001-09-07 2002-12-03 Motorola, Inc. Method of forming a semiconductor device having conductive bumps without using gold
JP3860028B2 (ja) 2001-12-25 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4119740B2 (ja) 2002-12-18 2008-07-16 富士通株式会社 半導体装置の製造方法
JP3938128B2 (ja) 2003-09-30 2007-06-27 セイコーエプソン株式会社 半導体装置とその製造方法、回路基板、電気光学装置、及び電子機器
US7723225B2 (en) * 2006-02-07 2010-05-25 Stats Chippac Ltd. Solder bump confinement system for an integrated circuit package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629399A (ja) * 1992-07-09 1994-02-04 Toshiba Corp 半導体装置の製造方法
JP2001144223A (ja) * 1999-09-29 2001-05-25 Samsung Electronics Co Ltd 再配置チップサイズパッケージ及びその製造方法
JP2001217310A (ja) * 2000-02-02 2001-08-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003060031A (ja) * 2001-08-14 2003-02-28 Oki Electric Ind Co Ltd 半導体装置及びその製造方法。
JP2004071942A (ja) * 2002-08-08 2004-03-04 Denso Corp 電解めっきを用いた配線の形成方法
JP2006210406A (ja) * 2005-01-25 2006-08-10 Fujikura Ltd 配線とそれを備えた半導体装置
JP2010062178A (ja) * 2008-09-01 2010-03-18 Toyota Motor Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200004199A (ko) * 2018-07-03 2020-01-13 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
KR102574452B1 (ko) * 2018-07-03 2023-09-04 삼성전자 주식회사 반도체 칩 및 이를 포함하는 반도체 패키지

Also Published As

Publication number Publication date
CN102386147A (zh) 2012-03-21
US9190373B2 (en) 2015-11-17
CN102386147B (zh) 2016-06-01
TWI576974B (zh) 2017-04-01
TW201214641A (en) 2012-04-01
US20120049356A1 (en) 2012-03-01

Similar Documents

Publication Publication Date Title
JP2012054359A (ja) 半導体装置および半導体装置の製造方法
US12009350B2 (en) Semiconductor package and method of fabricating the same
US7977789B2 (en) Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
US8384222B2 (en) Semiconductor device and manufacturing method thereof
US6455408B1 (en) Method for manufacturing semiconductor devices having redistribution patterns with a concave pattern in a bump pad area
US8183147B2 (en) Method of fabricating a conductive post on an electrode
US7969003B2 (en) Bump structure having a reinforcement member
KR20120056051A (ko) 반도체 패키지의 제조 방법 및 반도체 패키지
JP2012069704A (ja) 半導体装置及びその製造方法
CN108242437B (zh) 半导体装置以及半导体装置的制造方法
JP2009177072A (ja) 半導体装置及びその製造方法
KR101071074B1 (ko) 반도체 디바이스 제조 방법
JPH11354560A (ja) 半導体装置の製造方法
US8704367B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2012054366A (ja) 半導体装置および半導体装置の製造方法
US7358177B2 (en) Fabrication method of under bump metallurgy structure
JP4506767B2 (ja) 半導体装置の製造方法
JP2018116975A (ja) 半導体装置及び半導体装置の製造方法
JP2007258629A (ja) チップサイズパッケージの製造方法
JP2005150578A (ja) 半導体装置及びその製造方法
JP3972211B2 (ja) 半導体装置及びその製造方法
JP2007258354A (ja) 半導体装置の製造方法
JP5068830B2 (ja) 半導体装置
JP4794507B2 (ja) 半導体装置
JP2004281896A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120809

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130115

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130129

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130329

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130910