TWI539602B - 半導體裝置及製造半導體裝置之方法 - Google Patents

半導體裝置及製造半導體裝置之方法 Download PDF

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TWI539602B
TWI539602B TW102142824A TW102142824A TWI539602B TW I539602 B TWI539602 B TW I539602B TW 102142824 A TW102142824 A TW 102142824A TW 102142824 A TW102142824 A TW 102142824A TW I539602 B TWI539602 B TW I539602B
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region
ridge
field plate
semiconductor device
forming
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TW102142824A
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TW201424002A (zh
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安德魯斯 麥瑟
提爾 施勒塞爾
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英飛凌科技股份有限公司
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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半導體裝置及製造半導體裝置之方法
本說明書涉及一種半導體裝置和一種製造半導體裝置的方法。
通常在汽車和工業電子設備中採用的MOS功率電晶體或者MOS功率裝置當被接通時應該具有低的接通電阻(Ron)。在斷開狀態中，它們應該具有高的擊穿電壓特性並且承受源極-汲極電壓。例如，當被切斷時，MOS功率電晶體應該承受幾十到幾百伏特的汲極到源極電壓Vds。作為進一步的實例，MOS功率電晶體以低電壓降Vds在大約2到20V的閘極-源極電壓下傳導可以高達幾百安培的非常大的電流。
根據通常採用的技術，使用包括汲極延展區域或者基於所謂的低表面電場(resurf)概念的橫向MOS電晶體。根據該低表面電場概念，在斷開狀態中，電荷被配置在漂移區域之下的摻雜部分移除。可替代地，此摻雜部分可被實現，作為配置在漂移區域之上並且與漂移區域絕緣的電極。為了進一步降低Rdson和寄生電容，正在找尋用於實現電晶體的新概念。
根據一個實施例，一種在半導體基板中形成的半導體裝置包 括第一主表面和電晶體。該電晶體包括源極區域、汲極區域、通道區域、漂移區和鄰近於通道區域的閘電極，閘電極被配置為控制在通道區域中形成的通道的傳導性。通道區域和漂移區在源極區域和汲極區域之間沿著第一方向配置，該第一方向平行於第一主表面。通道區域具有沿著第一方向延伸的第一突脊的形狀。該電晶體還包括鄰近於漂移區配置的第一場板。
根據進一步的實施例，一種在半導體基板中形成的半導體裝置包括第一主表面和電晶體。該電晶體包括源極區域、汲極區域、通道區域、漂移區和鄰近於通道區域的閘電極，閘電極被配置為控制在通道區域中形成的通道的傳導性。通道區域和漂移區在源極區域和汲極區域之間沿著第一方向配置，該第一方向平行於第一主表面。通道區域具有沿著第一方向延伸的第一突脊的形狀，該第一突脊具有第一寬度d1，使得：d1 2 x ld，其中ld表示在第一突脊和閘極介電質之間的介面處形成的耗盡區的長度，閘極介電質被配置在第一突脊和閘電極之間。
根據進一步的實施例，描述了一種在半導體基板中製造半導體裝置的方法，該半導體基板包括第一主表面和電晶體。根據該方法，形成該電晶體包括形成源極區域、汲極區域、通道區域、漂移區和鄰近於通道區域的閘電極，其中通道區域和漂移區被形成為在源極區域和汲極區域之間沿著第一方向配置，該第一方向平行於第一主表面。形成通道區域包括在半導體基板中形成第一突脊，第一突脊沿著第一方向延伸，第一突脊具有第一寬度d1，使得：d1 2 x ld，其中ld表示在第一突脊和閘極介電質之間的介面處形成的耗盡區的長度，閘極介電質被配置在第一突脊和閘電極之間。
1‧‧‧半導體裝置
100‧‧‧半導體基板
110‧‧‧主表面
120‧‧‧井注入部分
200‧‧‧電晶體
201、2010、S40‧‧‧源極區域
202、2020、2060‧‧‧源電極
205、2050、S40‧‧‧汲極區域
206‧‧‧汲電極
210、2100、S30‧‧‧閘電極
211‧‧‧絕緣閘介電材料
212、S15‧‧‧閘極溝槽
220、2200、S10‧‧‧通道區域
220a、260a‧‧‧頂側
220b、260b‧‧‧側壁
225‧‧‧注入區域
250、2501、2502、S35‧‧‧場板
251、2510、2520‧‧‧場板介電層
252、S25‧‧‧場板溝槽
260、2600、S20‧‧‧漂移區
d1、d2‧‧‧寬度
t1、t2‧‧‧深度
V1、V2‧‧‧電位
S17、S27‧‧‧傳導層
所包括的附圖用於提供本發明的實施例的進一步理解並且在本說明書中結合並且構成其一個部分。附圖示例了本發明的實施例並且與說明書一起用於解釋原理。將易於理解本發明的其它實施例和許多預期的優點，因為藉由參考以下詳細說明，它們變得更好的理解。附圖的元件並不是必要地相對於彼此成比例。類似的圖式元件符號標注相應的類似的部分。
第1A圖示出根據一個實施例的半導體裝置的一個實例的平面視圖；第1B圖示出第1A圖所示的半導體裝置的截面視圖；第1C圖示出根據一個實施例的半導體裝置的截面視圖，其沿著與沿截取第1B圖的截面視圖的方向垂直的方向來截取；第1D圖示出該半導體裝置的進一步截面視圖，其沿著與沿其截取第1B圖的截面視圖的方向垂直的方向來截取；第2圖示出根據進一步實施例的半導體裝置的平面視圖；第3A圖到第3D圖示出在執行一種製造方法的加工方法時半導體基板的截面視圖；以及第4A圖和第4B圖概略地示出了示例根據實施例的用於製造半導體裝置的步驟的流程圖。
在以下詳細說明中，對於附圖進行參考，附圖形成它的一個部分，並且在其中藉由示例的方式示例可以在其中實施本發明的具體實施例。在這方面，方向性術語諸如“頂”、“底”、“前”、“後”、“首”、“尾”等是參考所描述的圖式的定向而使用的。因為本發明的實施例的組件能夠以多種不同的定向來定位，所以方向性術語是為了示例的目的而使用而且絕非 加以限制。應該理解在不偏離由申請專利範圍限定的範圍的情況下，可以利用其它的實施例並且可以作出結構或者邏輯變化。
實施例的說明不是限制性的。尤其，在下文中描述的實施例的元件可以與不同的實施例的元件組合。
在以下說明中使用的術語“晶圓”、“基板”或者“半導體基板”可以包括具有半導體表面的任何以半導體為基礎的結構。晶圓和結構應該被理解為包括矽、矽絕緣體(SOI)、矽藍寶石(SOS)、摻雜和非摻雜半導體、被基部半導體基礎支撐的矽的外延層和其它半導體結構。半導體不需要是以矽為基礎的。半導體同樣能夠是矽-鍺、鍺或者砷化鎵。根據本申請案的實施例，通常，碳化矽(SiC)或者氮化鎵(GaN)是半導體基板材料的進一步實例。
如在本說明書中使用的術語“橫向的”和“水平的”意指描述平行於半導體基板或者半導體本體的第一表面的定向。這能夠例如是晶圓或者晶片的表面。
如在本說明書中使用的術語“垂直的”意指描述垂直於半導體基板或者半導體本體的第一表面佈置的定向。
附圖和說明書藉由緊鄰摻雜類型“n”或者“p”而指示“-”或者“+”來示例相對摻雜濃度。例如，“n-”意味著低於“n”摻雜區域的摻雜濃度的摻雜濃度，而“n+”摻雜區域具有比“n”摻雜區域更高的摻雜濃度。具有相同的相對摻雜濃度的摻雜區域並不是必然具有相同的絕對摻雜濃度。例如，兩個不同的“n”摻雜區域可能具有相同或者不同的絕對摻雜濃度。在附圖和說明書中，為了更好地理解起見，摻雜部分經常被表明為是“p”或者“n”摻雜的。如同應該清楚地被理解的，這表明絕非意旨在是限制性的。摻雜類型 能夠是任意的，只要所描述的功能性得以實現。此外，在所有的實施例中，摻雜類型都能夠被顛倒過來。
如在本說明書中採用地，術語“耦接”和/或“電耦接”並非意在意味著元件必須被直接地耦接在一起-可以在“耦接”或者“電耦接”的元件之間提供居間的元件。術語“電連接的”意旨描述在被電連接在一起的元件之間的低歐姆電連接。
通常，為了圖案化材料層，可以使用其中提供適當的光阻材料的光蝕刻方法。使用適當的光罩來光蝕刻圖案化光阻材料。圖案化的光阻層能夠在隨後的加工步驟期間被用作遮罩。例如，如通常地那樣，硬遮罩層或者由適當的材料(諸如氮化矽、多晶矽或者碳)製成的層可被提供在要被圖案化的材料層上。例如，使用蝕刻程序來光蝕刻圖案化硬遮罩層。以圖案化的硬遮罩層作為蝕刻遮罩，材料層被圖案化。
如在本文所使用地，術語“具有”、“含有”、“包含”、“包括”等是開放式術語，其表明所陳述的元件或者特徵的存在但是並不排除額外的元件或者特徵。冠詞“一(a)”、“一(an)”和“該(the)”意旨包括複數以及單數，除非上下文清楚地另有表明。
第1A圖示出根據一個實施例的半導體裝置的平面視圖，並且第1B圖示出在I和I'之間截取的半導體裝置的截面視圖。
第1圖所示的半導體裝置包括源極區域201、汲極區域205、通道區域220和漂移區260。源極區域201、汲極區域205和漂移區260可以摻雜有第一導電類型的摻雜劑，例如n型摻雜劑。源極和汲極區域201、205的摻雜濃度可以高於漂移區260的摻雜濃度。通道區域220被配置在源極區域201和漂移區260之間。通道區域220摻雜有第二導電類型的摻雜 劑，例如，被p摻雜的。漂移區260可以被配置在通道區域220和汲極區域205之間。源極區域201、通道區域220、漂移區260和汲極區域205沿著第一方向配置。
當將適當的電壓施加到閘電極210時，在通道區域220中形成的通道的傳導性將受到閘電壓控制。閘電極210利用絕緣閘介電材料211例如氧化矽)從通道區域220絕緣。藉由控制在通道區域220中形成的通道的傳導性，從源極區域201經由在通道區域220中形成的通道和漂移區260到汲極區域205的電流可以受到控制。
源極區域201連接到源電極202。汲極區域205連接到汲電極206。
第1A圖所示的配置實現了半導體裝置1，該半導體裝置1包括在具有第一主表面110的半導體基板100中形成的電晶體200。根據一個實施例，電晶體200還可以包括鄰近於漂移區260配置的場板250。場板250利用絕緣場介電層251(例如場氧化物)而與漂移區260絕緣。當被接通時，在通道區域220和絕緣閘介電材料211之間的邊界處形成反轉層。因此，電晶體200處於經由漂移區260從源極區域201到汲極區域205的傳導狀態中。當電晶體200被斷開時，在通道區域220和絕緣閘介電材料211之間的邊界處沒有形成傳導通道，從而沒有電流流動。此外，在斷開狀態中，適當的電壓可以被施加到場板250。在斷開狀態中，場板250耗盡了從漂移區260的電荷載子，使得半導體裝置的反向電壓特性得以改進。在包括場板的半導體裝置中，與不具有場板的裝置相比，漂移區260的摻雜濃度可以增加而不惡化反向電壓特性。由於漂移區260的更高摻雜濃度，導通電阻Rdson進一步被降低，導致裝置特性得以改進。
第1B圖示出在第1A圖中I和I'之間示例的半導體裝置1的截面視圖。在I和I’之間的方向對應於第一方向。如所示出地，源極區域201從主表面110到基板100的深度方向延伸，即關於主表面110而垂直地延伸。通道區域220和漂移區260在源極區域201和汲極區域205之間沿著平行於第一主表面110的第一方向配置。汲極區域205同樣地沿著基板的深度方向從第一主表面110延伸。如由點線示意地，在圖式的描繪平面之前和之後的平面中，閘極溝槽212鄰近於通道區域220配置。以相應的方式，場板溝槽252可以被鄰近於漂移區260配置。閘極溝槽212和場板溝槽252沿著基板的深度方向從第一主表面110延伸。結果，通道區域220具有第一突脊的形狀。由於存在場板溝槽252，漂移區260還具有第二突脊的形狀。第1B圖進一步示出在本體區域220之下和在漂移區260的一部分之下配置的本體連接注入區域225。本體連接注入區域225將通道區域220連接到源極接點202，從而避免否則能夠在這個部分處形成的寄生雙極電晶體。而且，本體連接注入區域225在漂移區260之下延伸，從而在電晶體200的斷開狀態中，漂移區260可以更加容易地耗盡。
第1C圖和第1D圖示意在第1A圖中的II和II'與III和III'之間截取的基板的截面視圖。在II和II'之間和在III和III'之間的方向垂直於第一方向。如在第1C圖中所示，通道區域220具有突脊的形狀，該突脊具有寬度d1和深度或者高度t1。例如，第一突脊可以具有頂側220a和兩個側壁220b。側壁220b可以關於第一主表面110而垂直地延伸或者以大於75°的角度延伸。閘電極210可以鄰近於突脊的至少兩側配置。
而且，在III和III'之間的截面視圖中，漂移區260還具有第二突脊的形狀，第二突脊具有寬度d2和深度或者高度t2。例如，第二突脊 可以具有頂側260a和兩個側壁260b。側壁260b可以關於第一主表面110而垂直地延伸或者以大於75°的角度延伸。漂移區260可以鄰近於頂側260a或者鄰近於突脊的至少兩側配置。
在每一個突脊之下，配置深本體連接注入區域225，其將在下文中解釋。閘介電層211被配置在閘電極210和通道區域220之間。以類似的方式，場介電層251被配置在場板250和漂移區260之間。
根據一個實施例，通道區域220的寬度d1是：d1 2 x ld，其中d1表示在閘介電層211和通道區域220之間的介面處形成的耗盡區的長度。例如，耗盡區的寬度可以被確定為：
其中εS表示半導體材料的介電常數(對於矽為11.9*ε0)，k表示波茲曼常數(1.38066*10-23J/K)，T表示溫度，ln表示自然對數，NA表示半導體本體的雜質濃度，ni表示本質載子濃度(在27℃下對於矽為1.45*1010)，q表示基本電荷(1.6*10-19C)。
通常，假設在電晶體中，在對應於閾值電壓的閘電壓下耗盡區的長度對應於耗盡區的最大寬度。例如，沿著半導體基板100的第一主表面110，第一溝槽的寬度可為大蓋20-130nm，例如，40-120nm。
而且，長度與寬度的比率可以滿足以下關係：s1/d1>2.0，其中s1表示如還在第1A圖中示意地沿著第一方向測量的突脊的長度。根據進一步的實施例，s1/d1>2.5。如在第1C圖和第1D圖中所示，通道區域220的寬度d1可以不同於漂移區260的寬度d2。根據進一步的實施例，漂移區260可以包括如在第1D圖中所示的未被圖案化為形成突脊的平坦表面。
根據其中寬度d1 2 x ld的實施例，電晶體200是所謂的“全耗盡”電晶體，其中當閘電極被設定為接通電位時，通道區域220被完全地耗盡。在這種電晶體中，能夠實現最佳次閾值電壓並且短通道效應可以被有效地抑制，導致裝置特性得以改進。
在另一方面，在包括場板的電晶體中，期望的是使用具有比寬度d1大得多的寬度d2的漂移區260。由於漂移區d2的更大寬度，漂移區260的電阻Rdson可以進一步被降低，導致裝置特性被進一步改進。為了改進在本體區域220中半導體裝置的特性並且進一步改進在漂移區260中的裝置特性，完成對閘電極和場板250的圖案化，從而提供不同寬度的第一和第二突脊。
如已經參考第1B圖而進一步討論地，源極和汲極區域201、205以基板的深度方向延伸。因此，藉由適當地設定源極和汲極區域201、205的深度，可以根據需求來設定電晶體的電性質。由於閘電極210和場板250鄰近於通道區域220和漂移區260而在深度方向延伸的特殊額外特徵，沿著通道區域220的全部深度t1利用閘電極來控制在通道區域220中形成的通道的傳導性是可能的。以相應的方式，場板250沿著第二突脊的深度t2影響著漂移區260的行為。因此，源極區域201和汲極區域205的深度確定了電晶體200的有效寬度。因此，藉由設定源極和汲極區域201、205的深度，可以確定裝置的寬度和特性。例如，源極和汲極區域201、205的深度可以大於1μm。
通常，當在接通狀態中操作時，鄰近於閘介電層211在通道區域220中形成傳導反轉層。根據一個實施例，反轉層沿著該兩個側壁220b和220a中的至少一個延伸，電流主要地平行於第一主表面110流動。
如在第1C圖和第1D圖中示意地，閘電極可以被配置在突脊的至少兩側處。根據進一步的實施例，閘電極可以沿著突脊的兩個垂直側配置，而無閘電極鄰近於突脊的水平部分配置。以類似的方式，場板250可以被配置在漂移區260的三側處。儘管如此，根據一個實施例，場板250仍然可以鄰近於漂移區260的僅僅垂直部分配置。根據第1圖所示實施例，閘電極210和場板250被相互分離。
根據一個實施例，在漂移區260內的摻雜濃度可以是恒定的。根據進一步的實施例，摻雜濃度可以隨著距源極區域201的距離的增加而增加。此外，閘介電層211的厚度可以小於場板介電層251的厚度。場板介電層251的厚度可以是恒定的或者可以隨著距源極區域201的距離增加而增加。而且，鄰近於突脊的水平表面的場板介電層251的厚度可以不同於鄰近於突脊的垂直部分的場板介電層251的厚度。例如，場板介電層251的垂直部分的厚度可以大於場板介電層251的水平部分。第1圖所示半導體裝置還可以包括延伸到半導體基板100的第一主表面110的接點。根據進一步的實施例，該半導體裝置還可以包括到第二主表面的接點，該第二主表面相對於半導體基板100的第一主表面110。根據一個實施例，被電耦接到源極區域201的源極接點202可以延伸到第一主表面110並且被電耦接到汲極區域205的汲電極206可以延伸到與第一主表面110相對的第二主表面。
第2圖示出半導體裝置的進一步實施例。半導體裝置100包括電晶體2000，電晶體2000包括連接到源電極2020的源極區域2010。電晶體2000還包括連接到汲電極2060的汲極區域2050。電晶體2000還包括鄰近於通道區域2200配置並且利用閘介電層2110而與通道區域2200絕 緣的閘電極2100。電晶體2000還包括鄰近於通道區域2200配置的漂移區2600。源極區域2010、通道區域2200、漂移區2600和汲極區域2050沿著第一方向延伸。
電晶體2000還包括利用第一場板介電質2510而與漂移區2600絕緣的第一場板2501。而且，電晶體2000還包括利用第二場板介電層2520而與漂移區2600絕緣的第二場板2502。根據第2圖所示實施例，第二場板2502具有不同於第一場板2501的形狀和構造的形狀和構造。例如，漂移區2600可以具有在第一場板2501之下的第一突脊的形狀和在第二場板之下的第二突脊的形狀，並且第一突脊的寬度不同於第二突脊的寬度。例如，第二突脊的寬度可以大於第一突脊的寬度。而且，第二場板介電質2520的厚度可以不同於第一場板介電質2510的厚度。例如，第二場板介電質2520的厚度可以大於第一場板介電質2510的厚度。因此，對於第一和第二場板2501、2502，很多參數可以是不同的。第一和第二場板2501、2502可以被維持於不同的電位V1、V2。如應該清楚理解地，根據一個實施例，電晶體2000可以包括多於兩個場板。
第3A圖到第3D圖示例了根據一個實施例製造半導體裝置的步驟。
半導體基板可以藉由執行通常已知的淺溝槽隔離製程(STI)和注入步驟而被預先處理。例如，可以執行井注入步驟從而形成井注入部分120，隨後進行用於提供深本體連接注入區域225的進一步注入步驟和用於形成通道區域220的摻雜步驟。此外，可以執行注入步驟從而定義漂移區260。在第3A所示實施例中，漂移區260是n摻雜的而通道區域220是p摻雜的。深本體連接注入區域225是重度p摻雜的。如應該清楚理解地， 可以應用顛倒的摻雜類型。
第3A圖示出在第1A圖所示I和I'之間的截面視圖。在接著的步驟中，可選地，使用硬遮罩來光蝕刻地定義和蝕刻閘極溝槽212和場板溝槽252。例如，溝槽可具有大致500到5000nm的深度。在相鄰閘極溝槽212之間的距離可以是30到300nm，並且在相鄰場板溝槽252之間的距離可以是200到2000nm。閘極溝槽212和場板溝槽252被定義從而將通道區域220和漂移區260圖案化為第一和第二突脊。此後，例如藉由低壓CVD方法形成場板介電層251。例如，場板氧化物層可以具有30到500nm的厚度。此後，可以執行光蝕刻步驟，使得從不必要的部分蝕刻場氧化物。
第3B圖示出所產生的結構的一個實例的截面視圖。第3B圖的截面視圖在如第1A圖中所示IV和IV之間截取。如所示出地，場板溝槽252可延伸到比閘極溝槽212更深的深度。場介電層251僅僅在場板溝槽252中形成。
此後，可例如藉由熱氧化來形成閘介電層211。例如，閘介電層211可具有5到50nm的厚度。然後，形成形成柵電極210和場板250的傳導材料。例如，可以沉積多晶矽。例如，多晶矽層可以具有50到200nm的厚度。多晶矽材料可以是n摻雜的或者可以是非摻雜的並且可以在沉積之後摻雜。然後，傳導材料被圖案化從而形成閘電極210和場板250。
第3C圖示出所產生的結構的一個實例。如所示出地，形成閘電極210以鄰近於通道區域220，並且放置場板250以鄰近於漂移區260。此後，界定接觸溝槽以提供到源極和汲極區域201、205的連接。例如，接觸通槽可選地使用硬遮罩層而可以被光蝕刻地定義和蝕刻。然後，可以執行例如利用n型摻雜劑的傾斜注入步驟，以致於形成源極區域201和汲極 區域205。例如，源極區域201和汲極區域205可以延伸到不同的深度。例如，源極區域201和漏極區域205可以延伸到大致500到5000nm的深度。例如，源極區域201和汲極區域205中任一者可以延伸到與閘極通槽212的深度大致相同或者更小的深度。術語“大致相同的深度”意旨在意味著由於製程引起的變化，源極區域201和汲極區域205中任一者的深度可以比閘極溝槽212的深度小大約10%。可選地，可以執行進一步的p+注入步驟，以進一步摻雜直接地在通道區域220之下配置的部分，以形成p+摻雜本體連接注入區域225。可在定義源極和汲極區域201、205之前或者之後執行這個進一步的p+注入步驟。然後，在接觸溝槽中填充用於形成源電極202和汲電極206的傳導材料。例如，傳導材料可以包括多晶矽或者包括Ti、TiN和鎢(W)的疊層。傳導材料可以被回蝕刻。可以形成接點並且可以執行通用於電晶體製造的進一步的加工步驟。
根據另一個實施例，能夠在以後的加工階段，例如在所謂的MOL(中段製程(mid-of-line))加工步驟期間執行傾斜注入步驟和接觸溝槽加工。
根據進一步的實施例，接觸溝槽可以被蝕刻到比在第3D圖中示意的更深的深度，以致於提供與半導體裝置的第二主表面的接點。
第3D圖示出所產生的結構的一個實例。
第4A圖示意根據一個實施例的製造半導體裝置的方法。如在第4A圖中示意地，該方法可以包括在半導體基板中形成電晶體，該半導體基板包括第一主表面，其中形成電晶體包括形成源極區域(S40)、汲極區域(S40)、通道區域(S10)、漂移區(S20)和鄰近於通道區域的閘電極(S30)，其中通道區域和漂移區被形成為沿著第一方向配置，該第一方向 平行於在源極區域和汲極區域之間的第一主表面，其中通道區域在具有沿著第一方向延伸的第一突脊的形狀的基板部分中形成，第一突脊具有第一寬度d1，使得：d1 2 x ld，其中ld表示在閘電極和第一突脊之間的介面處形成的耗盡區的長度。可選地，該方法還可以包括形成場板(S35)。根據實施例，單一加工方法的順序性可以改變並且能夠根據一般的製程要求確定。
第4B圖示例了根據進一步的實施例的一種製造半導體裝置的方法。根據該實施例，一種製造半導體裝置的方法包括在半導體基板中形成電晶體，該半導體基板包括第一主表面，其中形成電晶體包括形成源極區域(S40)、汲極區域(S40)、通道區域(S10)、漂移區(S20)和鄰近於通道區域的閘電極(S30)，其中通道區域和漂移區被形成為沿著第一方向配置，第一方向平行於在源極區域和汲極區域之間的第一主表面。形成通道區域(S10)可包括在半導體基板中定義第一突脊，該第一突脊沿著第一方向延伸。定義第一突脊並且形成閘電極(S30)可以藉由在半導體基板中形成閘極溝槽(S15)並且形成傳導層(S17)從而填充相鄰溝槽而完成。
根據進一步的實施例，形成漂移區(S20)可以包括在半導體基板中定義第二突脊，該第二突脊沿著第一方向延伸。定義第二突脊並且形成場板(S35)可以藉由在半導體基板中形成場板溝槽(S25)並且形成傳導層(S27)從而填充相鄰溝槽而完成。
藉由形成閘極溝槽和可選地場板溝槽並且此後形成傳導層從而填充相鄰溝槽來形成電晶體意指所謂的鑲嵌(damascene)製造方法。根據這種方法，能夠免除圖案化傳導層從而形成鄰近於第一突脊的垂直側壁的部分的閘電極。類似地，能夠免除圖案化傳導層從而形成鄰近於第二突脊的垂直側壁的部分的場板。因此，這種方法進一步簡化製造半導體裝 置的方法。
如已經在前面示例地，本說明書的實施例涉及一種被實現為所謂的橫向裝置的半導體裝置，其使得電流能夠大致平行於半導體基板200的第一主表面110流動。因此，例如，可以以容易的方式形成源極和汲極區域並且所有的裝置組件可以鄰近於基板的第一主表面110來加工。通道區域220具有突脊的形狀，因此實現三維結構。閘電極210被配置在沿著通道區域220的整個深度延伸的閘極溝槽212中。因此，可在電晶體的全部深度上完成在通道區域220中形成的傳導通道的控制。而且，由於存在場板250，完成了利用場板250在漂移區260中的電荷補償。根據一個實施例，場板250被配置在沿著基板的深度方向延伸的場板溝槽252中。因此，在斷開狀態中，利用場板250耗盡漂移區260中的電荷載子可以容易地並且有效地完成。根據其中通道區域220具有擁有特殊寬度的突脊的形狀的實施例，當施加對應於接通狀態的閘電壓時，電晶體可以被完全地耗盡。由此，實現了具有改進的次閾值斜率特性的電晶體。此外，有效電晶體寬度增加，從而電晶體的有效面積增加，而不增加所要求的空間。
雖然以上已經描述了本發明的實施例，但是顯然，可以實現進一步的實施例。例如，進一步的實施例可包括在申請專利範圍中請求保護的特徵的任何次級組合或者在以上給出的實例中描述的元件的任何次級組合。因此，所附申請專利範圍的這個精神和範圍不應該限制於本文包含的實施例的說明。
1‧‧‧半導體裝置
200‧‧‧電晶體
201‧‧‧源極區域
202‧‧‧源電極
205‧‧‧汲極區域
206‧‧‧汲電極
211‧‧‧絕緣閘介電材料
220‧‧‧通道區域
250‧‧‧場板
260‧‧‧漂移區

Claims (25)

  1. 一種包括在具有一第一主表面的一半導體基板中形成的一電晶體的半導體裝置，該電晶體包括：一源極區域；一汲極區域；一通道區域；一漂移區；一閘電極，鄰近於該通道區域，該閘電極被配置以控制在該通道區域中形成的一通道的一傳導性，該通道區域和該漂移區在該源極區域和該汲極區域之間沿著一第一方向配置，該第一方向平行於該第一主表面，該通道區域具有沿著該第一方向延伸的一第一突脊一的形狀；以及一第一場板，被配置為鄰近於該漂移區，其中該第一場板被配置在該半導體基板內。
  2. 如申請專利範圍第1項所述的半導體裝置，其中該閘電極被配置在該突脊的至少兩側處。
  3. 如申請專利範圍第1項所述的半導體裝置，其中該突脊包括一頂側和二側壁。
  4. 如申請專利範圍第3項所述的半導體裝置，其中當該半導體裝置在一接通狀態中操作時，沿著該側壁至少其中之一形成一傳導反轉層。
  5. 如申請專利範圍第1項所述的半導體裝置，其中該漂移區的一部分具有沿著該第一方向延伸的一第二突脊的一形狀。
  6. 如申請專利範圍第5項所述的半導體裝置，其中部分的該第一場板被配置在該第二突脊的至少兩側處。
  7. 如申請專利範圍第5項所述的半導體裝置，其中該第二突脊具有與該第一突脊的一寬度不同的一寬度。
  8. 如申請專利範圍第1項所述的半導體裝置，其中該閘電極和該第一場板相互隔離。
  9. 如申請專利範圍第1項所述的半導體裝置，還包括一第二場板，該第二 場板被配置在該第一場板和該汲極區域之間沿著該第一方向鄰近於該第一主表面。
  10. 如申請專利範圍第9項所述的半導體裝置，其中該第二場板被耦接到一電位並且該第一場板被耦接到與耦接到該第二板的該電位不同的一電位。
  11. 如申請專利範圍第5項所述的半導體裝置，其中該漂移區的另外部分具有沿著該第一方向延伸的一第三突脊的一形狀，該半導體裝置還包括一第二場板，該第二場板被配置在該第一場板和該汲極區域之間鄰近於該第三突脊。
  12. 如申請專利範圍第11項所述的半導體裝置，其中該第三突脊具有與該第二突脊的一寬度不同的一寬度。
  13. 如申請專利範圍第1項所述的半導體裝置，其中該第一突脊的一寬度d是：d2 x ld，其中ld表示在該第一突脊和該閘電極之間的一介面處形成的一耗盡區的一長度。
  14. 如申請專利範圍第1項所述的半導體裝置，其中該源極區域和該汲極區域被配置在該半導體基板內並且大致地延伸到該閘電極沿著該半導體基板的一深度方向從該第一主表面延伸至的一深度。
  15. 一種在包括一第一主表面和一電晶體的一半導體基板中形成的半導體裝置，該電晶體包括：一源極區域；一汲極區域；一通道區域；一漂移區；一閘電極，為鄰近於該通道區域，該閘電極被配置為控制在該通道區域中形成的一通道的一傳導性，該通道區域和該漂移區在該源極區域和該汲極區域之間沿著一第一方向配置，該第一方向平行於該第一主表面，該通道區域具有沿著該第一方向延伸的一第一突脊的一形狀，該第一突脊具有一第一寬度d1，使得： d1 2 x ld，其中ld表示在該第一突脊和一閘極介電質之間的一介面處形成的一耗盡區的一長度，該閘極介電質被配置在該第一突脊和該閘電極之間；以及一場板，被配置在該半導體基板內。
  16. 如申請專利範圍第15項所述的半導體裝置，其中以下等式成立：s1/d1>2.0，其中s1表示沿著一第一方向測量的該突脊的該長度。
  17. 如申請專利範圍第15項所述的半導體裝置，其中該場板被配置為鄰近於該漂移區。
  18. 如申請專利範圍第15項所述的半導體裝置，其中該漂移區是的一摻雜部分，該摻雜部分具有隨著距該源極區域的距離增加而增加的一摻雜濃度。
  19. 如申請專利範圍第15項所述的半導體裝置，還包括被配置在該閘電極和該突脊之間的一閘極介電層和被配置在該場板和該漂移區之間的一場氧化物，其中該場氧化物層的一厚度隨著距該源極區域的距離增加而增加。
  20. 如申請專利範圍第15項所述的半導體裝置，其中該閘電極被配置在該第一突脊的至少兩側處。
  21. 一種在半導體基板中製造一半導體裝置的方法，該半導體基板包括一第一主表面和一電晶體，其中形成該電晶體包括：形成一源極區域、一汲極區域、一通道區域、一漂移區、鄰近於該通道區域的一閘電極和一場板，其中該通道區域和該漂移區被形成為在該源極區域和該汲極區域之間沿著一第一方向配置，該第一方向平行於該第一主表面，其中形成該通道區域包括在該半導體基板中形成一第一突脊，該第一突脊沿著該第一方向延伸，該第一突脊具有一第一寬度d1，使得：d1 2 x ld，其中ld表示在該第一突脊和一閘極介電質之間的一介面處形成的一耗盡區的一長度，該閘極介電質被配置在該第一突脊和該閘電極之間，其中該場板被配置在該半導體基板內。
  22. 如申請專利範圍第21項所述的方法，其中形成該第一突脊並且形成該閘電極是藉由一方法完成的，該方法包括在該半導體基板中形成閘極溝槽並且形成一傳導層從而填充相鄰溝槽。
  23. 如申請專利範圍第21項所述的方法，其中該場板被配置為鄰近於該漂移區。
  24. 如申請專利範圍第23項所述的方法，其中形成一場板包括在該半導體基板中形成場板溝槽並且形成一傳導層從而填充該場板溝槽。
  25. 如申請專利範圍第23項所述的方法，其中形成該閘電極包括在該半導體基板中形成閘極溝槽以及形成一場板包括在該半導體基板中形成場板溝槽，其中該閘極溝槽和該場板溝槽被形成，使得在相鄰閘極溝槽之間的一間距不同於在相鄰場板溝槽之間的一間距，形成該閘極溝槽以及形成該場板溝槽是藉由一聯合蝕刻程序而執行的。
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