CN110071169A - 具有体接触与介电间隔部的半导体器件及对应的制造方法 - Google Patents

具有体接触与介电间隔部的半导体器件及对应的制造方法 Download PDF

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Publication number
CN110071169A
CN110071169A CN201910062909.2A CN201910062909A CN110071169A CN 110071169 A CN110071169 A CN 110071169A CN 201910062909 A CN201910062909 A CN 201910062909A CN 110071169 A CN110071169 A CN 110071169A
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area
conduction type
semiconductor substrate
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semiconductor devices
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黄伟峻
T.法伊尔
M.珀尔兹尔
M.勒施
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明公开了具有体接触与介电间隔部的半导体器件及对应的制造方法。一种半导体器件包括延伸到半导体衬底的第一主表面中的沟槽，以及在所述沟槽中的栅极电极和栅极电介质。栅极电介质使栅极电极与半导体衬底分离。具有第一导电类型的第一区被形成在所述半导体衬底中位于第一表面处与所述沟槽相邻。具有第二导电类型的第二区被形成在所述半导体衬底中位于所述第一区下方与所述沟槽相邻。具有第一导电类型的第三区被形成在所述半导体衬底中位于所述第二区下方与所述沟槽相邻。半导体衬底中的接触开口延伸到所述第二区中。电绝缘间隔部被设置在由接触开口形成的半导体衬底的侧壁上，并且接触开口中的导电材料邻接所述侧壁上的电绝缘间隔部。

Description

具有体接触与介电间隔部的半导体器件及对应的制造方法
技术领域
本发明涉及具有体接触（body contact）与介电间隔部的半导体器件及对应的制造方法。
背景技术
例行地使功率MOSFET的沟道尺寸减小来增加性能。器件的沟道与器件的体区的凹槽接触之间的距离也变得更小，从而导致若干关键性的折衷，包括：到凹槽中的p+接触注入物与沟道掺杂剂的相互作用；以及在耗尽电容使栅极控制降低以及寄生源极电容增大时，阈值电压特性的斜率减小。
沟道和凹槽接触之间的距离可以保持足够大，但是这导致较高的Rdson（导通状态电阻）。可以通过使用产生较小栅极电容的较薄氧化物来解决阈值电压特性的斜率的减小。然而，较小栅极电容增加栅极总电荷品质因数（FOMg）。
因此，需要具有较小的沟道尺寸和可接受的FOMg的新的功率MOSFET。
发明内容
根据半导体器件的实施例，所述半导体器件包括：延伸到半导体衬底的第一主表面中的沟槽；在沟槽中的栅极电极和栅极电介质，所述栅极电介质使栅极电极与半导体衬底分离；具有第一导电类型的第一区，所述第一区被形成在半导体衬底中位于第一表面处并且与沟槽相邻；具有第二导电类型的第二区，所述第二区被形成在半导体衬底中位于第一区下方并且与沟槽相邻；具有第一导电类型的第三区，所述第三区被形成在半导体衬底中位于第二区下方并且与沟槽相邻；在半导体衬底中的接触开口，所述接触开口延伸到第二区中；电绝缘间隔部，所述电绝缘间隔部位于由接触开口形成的半导体衬底的侧壁上；以及导电材料，所述导电材料位于所述接触开口中并且邻接由接触开口形成的半导体衬底的侧壁上的电绝缘间隔部。还提供了对应的制造方法。
本领域技术人员在阅读下面的详细描述时和在查看附图时将认识到附加的特征和优点。
附图说明
绘图的元件未必相对于彼此成比例。相似的参考标号指定对应类似的部分。各种图示的实施例的特征可以组合，除非它们互相排斥。在绘图中描绘实施例，并且在下面的描述中详述所述实施例。
图1至4图示具有体接触与介电间隔部的半导体器件的实施例的相应部分横截面视图。
图5A至5D图示用于制造在图1至4中示出的半导体器件的一些处理步骤的实施例。
图6图示在图1至4中示出的半导体器件实施例的部分俯视图。
图7至10图示具有体接触与介电间隔部的半导体器件的附加实施例的相应部分横截面视图。
图11A至11Q图示制造在图10中示出的半导体器件的方法的实施例。
图12图示具有体接触与介电间隔部以及集成的肖特基势垒二极管的半导体器件的实施例的部分横截面视图。
具体实施方式
在本文中描述的实施例提供具有减小的沟道尺寸和良好的FOMg的功率MOSFET，以及对应的制造方法。通过沿着接触的侧壁到功率器件的高掺杂体接触区引入间隔部电介质，可以进一步减小沟道区的横向尺寸，同时还减小源极电容并增加高掺杂体接触区与沟道区之间的距离。在半导体衬底中的接触开口/凹槽与栅极沟槽之间的器件体区的小鳍状部分与接触开口/凹槽并联，从而减小IV曲线和DIBL（漏极诱导的势垒下降）摆动。高掺杂体接触区通过沿着接触开口/凹槽的间隔部电介质而与沟道区解耦合，从而改进阈值电压稳定性。介电间隔部还沿着沟道侧面引入应力，其应该减小Rdson和泄漏。
图1图示具有体接触与介电间隔部的半导体器件100的部分横截面视图。半导体器件100包括半导体衬底102，所述半导体衬底102具有延伸到半导体衬底102的前表面106中的栅极沟槽104。半导体衬底102可以包括任何类型的半导体材料，诸如单元素半导体（例如Si、Ge等）、绝缘体上硅、二元半导体（例如SiC、GaN、GaAs等）、三元半导体等，其具有或不具有（一个或多个）外延层。在每个栅极沟槽104中设置栅极电极108和栅极电介质110，所述栅极电介质110使对应的栅极电极108与半导体衬底102分离。可以将场板112设置在栅极沟槽104中位于栅极电极108下方，每个场板112通过比栅极电介质110更厚的场电介质114而与半导体衬底102和对应的栅极电极108分离。替换地或附加地，可以将场板设置在专用场板沟槽中，所述专用场板沟槽在图1中未被示出。
具有第一导电类型（例如，在n沟道器件的情况下为n型，或者在p沟道器件的情况下为p型）的第一（源极/发射极）区116被形成在半导体衬底102中位于前表面106处并且与每个栅极沟槽104相邻。具有第二导电类型（例如，在n沟道器件的情况下为p型，或者在p沟道器件的情况下为n型）的第二（体）区118被形成在半导体衬底102中位于源极/发射极区116下方并且与每个栅极沟槽104相邻。具有第一导电类型的第三（漂移）区120被形成在半导体衬底102中例如作为外延层的部分，位于体区118下方并且与每个栅极沟槽104相邻。第一导电类型的漏极/集电极区122被形成在半导体衬底102的与前表面106相对的背表面124处，并且被比漂移区120更重地掺杂。
在图1中示出的半导体器件100是垂直功率MOSFET，其具有在垂直方向上沿着栅极电介质110在体区118中延伸的沟道区126。通过将足够的栅极电压施加到栅极电极108，少数载流子（在p型体区118的情况下为电子，或者在n型体区118的情况下为空穴）沿着栅极电介质110在沟道区126中聚集，并且导电路径经由漂移和沟道区120、126而在源极/发射极区116和漏极/集电极区122之间完成。
诸如二氧化硅、氮化硅、正硅酸乙酯（TEOS）等之类的层间电介质128被形成在半导体衬底102的前表面106上以使一个或多个上覆（overlying）金属层（未示出）与下伏（underlying）半导体衬底102分离。接触开口130延伸通过层间电介质128并且延伸到半导体衬底102中。在一个实施例中，接触开口130在层间电介质128中的最小宽度（w1）大于接触开口130在半导体衬底102中的最小宽度（w2）。相邻栅极沟槽104之间的漂移区120的宽度在图1中被标记为w3，并且其可以在几百纳米的范围内，例如大约300 nm或者更多或者更少。在半导体衬底102中形成的接触开口130的部分在本文中还被称为凹槽。导电材料132填充接触开口130以形成体接触插塞134，所述体接触插塞134由于以上描述的宽度差异（w1>w2）而在接触开口130中具有阶梯式剖面。
接触开口130至少延伸到体区118中。在图1中图示的实施例中，接触开口130在体区118内终止，使得体接触插塞134通过体区118的区段而与漂移区120分离。第二导电类型并且比体区118更重地掺杂的高掺杂（例如，p+）体接触区136被形成在体区118中与接触开口130的底部相邻。高掺杂体接触区136在接触开口130的底部处邻接体接触插塞134，并且与其欧姆接触。
电绝缘间隔部138被设置在由接触开口130形成的半导体衬底102的侧壁140上。接触开口130中的导电材料132邻接由接触开口130形成的半导体衬底102的侧壁140上的电绝缘间隔部138。通过沿着由接触开口130形成的半导体衬底102的侧壁140提供电绝缘间隔部138，可以减小沟道区126的横向尺寸，同时还减小源极电容并且增加体接触插塞134和沟道区126之间的距离。作为结果，通过设置在由接触开口130形成的半导体衬底102的侧壁140上的电绝缘间隔部138，体接触插塞134与沟道区126更好地解耦合。诸如氧化物、氮化物、碳、TEOS等之类的任何适合的电绝缘材料可以用于电绝缘间隔部138。
根据在图1中示出的实施例，电绝缘间隔部138延伸到半导体衬底102的前表面106上，沿着由接触开口130形成的层间电介质128的侧壁142延伸，并且延伸到层间电介质128的背对半导体衬底102的表面144上。在这样的接触凹槽间隔部配置的情况下，形成在半导体衬底102中的高掺杂体接触区136和体接触插塞134之间的欧姆接触仅仅出现在接触开口130的底部处。如先前在本文中描述的那样，半导体衬底102可以包括一个或多个外延层，诸如Si外延层。例如，重掺杂的漏极/集电极区122可以已由半导体晶片制造，并且体区118和漂移区120可以被形成在生长于重掺杂的漏极/集电极区122上的一个或多个外延层中。
图2图示具有掩埋的介电插塞的半导体器件200的另一实施例的部分横截面视图。图2中示出的实施例与图1中示出的实施例类似。然而，不同的是，设置在接触开口130中的电绝缘间隔部138的部分沿着由接触开口130形成的半导体衬底102的侧壁140凹陷在半导体衬底102的前表面106下方。根据该实施例，电绝缘间隔部138在高掺杂体接触区136的形成之前凹陷。作为结果，作为电绝缘间隔部138在选择区中的移除的结果而暴露的源极/集电极区116的部分在体接触形成工艺期间被注入。在对应的退火工艺之后，比体区118更重地掺杂的第二导电类型的第一高掺杂体接触区136被形成在体区118中与接触开口130的底部相邻。第二导电类型的第二高掺杂体接触区202可以被形成在作为电绝缘间隔部138的选择性移除的结果而暴露的源极/集电极区116的部分中。第一高掺杂体接触区136在接触开口130的底部处邻接体接触插塞134并且与其欧姆接触，而第二高掺杂体接触区202沿着接触开口130的没有电绝缘间隔部138的部分邻接体接触插塞134并且与其欧姆接触。在图2中示出的实施例的变化可以省略第二高掺杂体接触区202，使得源极/集电极区116沿着接触开口130的侧壁以及可能地沿着半导体主体102的前表面106的部分至少部分地未被电绝缘间隔部138覆盖。例如，第一高掺杂体接触区136可以由在接触开口130的底部处的注入（例如，p+）形成。被注入的一些掺杂剂种类还可能到达接触开口130的侧壁的未被覆盖的部分。在第一选项中，源极/集电极区116的未被覆盖的部分被注入并且在最终产物中包括高掺杂的接触区202。在第二选项中，注入基本上不影响源极/集电极116的掺杂，使得最终产物不包括高掺杂的接触区202，但是具有如下总（净）掺杂浓度：所述总（净）掺杂浓度足以充当器件的源极/集电极并且确保维持良好的欧姆接触（例如，n+）。
图3图示具有体接触与介电间隔部的半导体器件300的又另一实施例的部分横截面视图。图3中示出的实施例与图2中示出的实施例类似。然而，不同的是，体区118的区段302延伸到半导体衬底102的前表面106，并且每个源极/集电极区116被横向设置在相邻栅极沟槽104和延伸到半导体衬底102的前表面106的体区118的区段302之间。接触开口130被形成在延伸到半导体衬底102的前表面106的体区118的区段302中。电绝缘间隔部138沿着延伸到半导体衬底102的前表面106的体区118的区段302的侧壁140凹陷在半导体衬底102的前表面106下方，使得侧壁140的上部部分没有电绝缘间隔部138。
图4图示具有体接触与介电间隔部的半导体器件400的仍另一实施例的部分横截面视图。图4中示出的实施例与图3中示出的实施例类似。然而，不同的是，接触开口130比体区118延伸到半导体衬底102中从前表面106测量的更深的深度（d_co）并且延伸到下伏漂移区120中，使得体接触插塞134延伸到漂移区120中。根据该实施例，在接触开口130的底部处邻接体接触插塞134的高掺杂体接触区136被形成在漂移区120中，并且提供结果得到的与漂移区120的pn结的阻断能力。上部高掺杂体接触区202在半导体衬底102的前表面106处提供与体接触插塞134的低欧姆连接。
在一些实施例中，源极/集电极区116具有在10 nm至50nm之间的范围内的深度，体区118具有在100 nm与200nm之间的范围内的深度，层间电介质128具有在50 nm与300 nm之间的范围内的厚度，层间电介质128中的接触开口130具有在200 nm与220 nm之间的范围内的最小宽度w1，半导体主体100中的接触（凹槽）开口130具有在100 nm与140 nm之间的范围内的最小宽度w2，沟道区126在垂直方向上的长度在50nm与200nm之间的范围内，和/或横向沟道长度小于250nm。其他深度、厚度、宽度和长度范围被设想到。
图5A至5D图示用于制造在图1至4中示出的半导体器件的一些处理步骤的实施例。
图5A示出在形成了栅极沟槽104、源极/集电极区116、体区118、漂移区120、以及漏极/集电极区122之后的在半导体衬底102的前表面106上形成的层间电介质128。
图5B示出在层间电介质128中形成的开口500。可以使用自对准工艺、使用光刻对准工艺等来形成开口500。开口130的关键尺寸变化和覆盖物（overlay）的量限定要形成的接触条带的宽度。
图5C示出与层间电介质128中的开口500对准并且被蚀刻到半导体主体100中的凹槽502。凹槽502至少延伸到体区118中。层间电介质128中的开口500和蚀刻到半导体主体100中的凹槽502形成接触开口130。凹槽502可以被完全蚀刻通过体区118，使得接触开口130延伸到下伏漂移区120中，例如，如在图4中示出的那样。在任一情况下，由开口130形成的层间电介质128的侧壁142被回蚀以限定要形成的电绝缘间隔部138的厚度（t_s）。在一个实施例中，电绝缘间隔部138的厚度在10 nm与30 nm之间的范围内。在一个实施例中，在接触开口130的每一侧与对应栅极沟槽104之间的半导体鳍或条带504的宽度小于100 nm，例如在80 nm与100 nm之间。
图5D示出在层间电介质128的背对半导体衬底102的表面144上、在层间电介质128的回蚀的侧壁142上、在源极/发射极区116的前表面106上、以及在形成于半导体衬底102中的凹槽502（其至少延伸到体区118中）的侧壁140上形成的电绝缘间隔部138。在沉积导电材料132之前，所述导电材料132填充接触开口130，从接触开口130的底部移除电绝缘间隔部138。也可以从源极/发射极区116的前表面106以及沿着形成于半导体衬底102中的凹槽502的侧壁140的上部部分移除电绝缘间隔部138，例如，如在图2至4中示出的那样。
图6图示在图1至4中示出的半导体器件实施例的部分俯视图。图6的顶部半部图示在图1中示出的半导体器件100的上部特征。图6的底部半部图示在图2至4中示出的半导体器件200、300、400的上部特征。在每一种情况下，栅极沟槽104（在图6中的视图之外）、源极区116、体区118以及接触开口130各自是条带形的，并且在半导体衬底102的纵向方向上延伸。图6中的虚线给该图的顶部半部和底部半部划界。
图7图示具有体接触与介电间隔部的半导体器件700的实施例的部分横截面视图。图7中示出的实施例与图4中示出的实施例类似。然而，不同的是，第二导电类型的柱/柱形物/条带区702被形成在漂移区120中，并且在接触开口130的底部下方邻接高掺杂体接触区136。第二导电类型的柱/柱形物/条带区702比栅极沟槽104和高掺杂体接触区136延伸到半导体衬底102中如从前表面106测量的更大的深度。在一个实施例中，第二导电类型的柱/柱形物/条带区702延伸到在半导体衬底102的底部表面124处的漏极/集电极区122，并且与其邻接。
此外，根据在图7中图示的实施例，第二导电类型的附加高掺杂体接触区202被形成在体区118的与接触开口130相邻的区段中。附加体接触区202比体区118更重地掺杂。源极/发射极区116邻接附加体接触区202的面对邻近栅极沟槽104的侧表面704，并且延伸到附加体接触区202的前表面706上。填充接触开口的导电材料也邻接附加体接触区的前表面。
图8图示具有体接触与介电间隔部的半导体器件800的另一实施例的部分横截面视图。图8中示出的实施例与图7中示出的实施例类似。然而，不同的是，栅极沟槽104不包括场板。
图9图示具有体接触与介电间隔部的半导体器件900的又另一实施例的部分横截面视图。图9中示出的实施例与图7中示出的实施例类似。然而，不同的是，第一导电类型的柱/柱形物/条带区902被形成在每个栅极沟槽104下面的漂移区120中。第一导电类型的柱/柱形物/条带区902通过漂移区120的区段而与第二导电类型的柱/柱形物/条带区702横向分离。第一导电类型的柱/柱形物/条带区902延伸到在半导体衬底102的背表面124处的漏极/集电极区122，并且与其邻接。漏极/集电极区122比第一导电类型的柱/柱形物/条带区902更重地掺杂。
图10图示具有体接触与介电间隔部的半导体器件1000的仍另一实施例的部分横截面视图。图10中示出的实施例与图8中示出的实施例类似。然而，不同的是，第一导电类型的柱/柱形物/条带区902被形成在每个栅极沟槽104下面的漂移区120中。第一导电类型的柱/柱形物/条带区902通过漂移区120的区段而与第二导电类型的柱/柱形物/条带区702横向分离。第一导电类型的柱/柱形物/条带区902延伸到在半导体衬底102的背表面124处的漏极/集电极区122，并且与其邻接。漏极/集电极区122比第一导电类型的柱/柱形物/条带区902更重地掺杂。
在图7至10中图示的半导体器件700、800、900、1000被示出为n沟道器件，但是器件区的导电类型可以被反转以代替地实现p沟道器件。
图11A至11Q图示制造在图10中示出的半导体器件1000的方法的实施例。
图11A示出半导体衬底1100，其具有在衬底1100的背表面1101处的n+区1102和邻接n+区1102的n-区1104。半导体衬底1100可以包括任何类型的半导体材料，诸如单元素半导体（例如Si、Ge等）、绝缘体上硅、二元半导体（例如SiC、GaN、GaAs等）、三元半导体等，其具有或不具有（一个或多个）外延层。n-区1104可以被形成，例如作为外延层的部分。在半导体衬底1100的前表面1103上形成硬掩模1106。开口1108被蚀刻通过硬掩模1106，例如通过使用各向异性蚀刻工艺，以暴露半导体衬底1100的前表面1103的部分。
图11B示出在由硬掩模1106中的开口1108暴露的半导体衬底1100的部分凹陷在衬底1100的前表面1103下方之后的半导体衬底1100。凹陷1110的深度可以基于应用而变化。
图11C示出在硬掩模1106被移除并且间隔部氧化物1112被形成在衬底1100的前表面1103上之后的半导体衬底1100。开口1114被蚀刻通过间隔部氧化物1112，以暴露半导体衬底1100的凹陷表面1110的部分。
图11D示出在凹槽1116被蚀刻到半导体衬底1100的凹陷表面1110的暴露部分中之后的半导体衬底1100。凹槽1116具有侧壁1118和底部1120。凹槽1116的深度可以取决于应用而变化。
图11E示出在如下之后的半导体衬底1100：在形成于半导体衬底1100的凹陷表面1110中的凹槽1116的侧壁1118和底部1120上形成牺牲氧化物1122。
图11F示出在p型柱/柱形物/条带区1124通过形成于半导体衬底1100的凹陷表面1110中的凹槽1116的底部1120而被注入到n-层1104中之后的半导体衬底1100。
图11G示出在间隔部氧化物1112和牺牲氧化物1122被移除并且衬底1100的凹陷部分被填充有氧化物1126之后的半导体衬底1100。例如通过CMP（化学机械抛光）工艺来从半导体衬底1100的前表面1103移除间隔部氧化物1112和牺牲氧化物1122，所述CMP工艺在衬底1100的半导体材料上停止。
图11H示出在沟槽1128被蚀刻到衬底1100的未被牺牲氧化物1126保护的部分中之后的半导体衬底1100。每个沟槽1128具有侧壁1130和底部1132。
图11I示出在沟槽1128的侧壁1130和底部1132上形成牺牲氧化物1134之后的半导体衬底1100。
图11J示出在n型柱/柱形物/条带区1136通过每个沟槽1128的底部1132而被注入到n-层1104中之后的半导体衬底1100。在一个实施例中，p型柱/柱形物/条带区1124延伸到在半导体衬底的背表面1101处的n+层1102，而n型柱/柱形物/条带区在到达n+层之前在n-层中终止。
图11K示出在如下各项之后的半导体衬底1100：牺牲氧化物1134被移除、栅极氧化物被形成在每个沟槽1128的侧壁1130和底部1132上、以及每个沟槽1128被填充有诸如掺杂多晶硅之类的导电材料。栅极氧化物和导电材料例如通过CMP（化学机械抛光）工艺而被平坦化，所述CMP工艺在衬底1100的半导体材料上停止。结果得到的沟槽结构形成栅极沟槽1138，其中的每一个包括在沟槽1138中的栅极电极1140和栅极电介质1142，所述栅极电介质1142使栅极电极1140与半导体衬底1100分离。
图11L示出在例如通过干法和/或湿法蚀刻而使衬底1100的前表面在栅极沟槽1138之间凹陷从而使衬底1100的该区中的n-层1104凹陷之后的半导体衬底1100。而且，栅极电极1140被覆盖有氧化物1144。
图11M示出在p型体区1146和n型源极/发射极区1148被形成在栅极沟槽1138之间的n-层1104中之后的半导体衬底1100。p型掺杂剂被注入到在栅极沟槽1138之间的半导体衬底1100中并且被退火以形成p型体区1146，并且n型掺杂剂被注入在栅极沟槽1138之间并且被退火以形成源极/发射极区1148。
图11N示出在如下各项之后的半导体衬底1100：层间电介质1150被形成在半导体衬底1100的前表面上、开口1152被形成在层间电介质1150中、并且凹槽1154被蚀刻到半导体衬底1100的由层间电介质1150中的开口1152暴露的部分中。层间电介质1150中的开口1152比在半导体衬底1100中蚀刻的接触凹槽1154更宽。从源极/发射极区1148的前面1156的最靠近接触接触凹槽1154的部分以及从源极/发射极区1148的面对接触凹槽1154的侧面1158移除层间电介质材料，从而暴露源极/发射极区1148的这些面1156、1158。层间电介质材料保留在源极/发射极区1148下方的接触凹槽1154的侧壁1160上以形成介电间隔部1151，但是被从接触凹槽1154的底部1162移除。
图11O示出在如下各项之后的半导体衬底1100：源极/发射极区1148的暴露表面1156、1158被蚀刻掉以便使每个源极/发射极区1148在朝向邻近栅极沟槽1138的方向上横向凹陷，从而暴露体区1146的前面1164的最靠近接触凹槽1166的部分。
图11P示出在如下各项之后的半导体衬底1100：p型掺杂剂被注入到衬底1100的暴露部分中并且随后被退火以在每个接触凹槽1166的底部处形成第一高掺杂（例如，p+）体接触区1168，并且在每个体区1146的前面1164的最靠近对应接触凹槽1166的暴露部分中形成第二高掺杂（例如，p+）体接触区1170。
图11Q示出在诸如金属之类的导电材料1172被沉积在衬底之上以填充接触开口1166之后的半导体衬底1100。导电材料邻接半导体衬底1100的凹陷部分，并且例如通过CMP工艺而被平坦化。在图11A至11Q中图示的半导体器件区被示出为n沟道器件的器件区，但是器件区的导电类型可以被反转以代替地实现p沟道器件。
由p型和n型柱/柱形物/条带1124、1136形成的超级结电荷平衡结构导致减小的导通电阻，同时维持所需要的击穿电压。通过在体接触开口中提供介电间隔部1151来使沟道区1174与下伏p型柱/柱形物/条带1124分离，p型柱/柱形物/条带1124所需要的宽度可以被减小，这进而降低注入p型柱/柱形物/条带1124所需要的能级，所述p型柱/柱形物/条带1124用来形成超级结结构并且实现电荷平衡。利用深体接触开口以及具有下伏p型柱/柱形物/条带的接触沟槽，可以维持所需要的电压，同时还将碰撞电离位置重新定位到p型柱/柱形物/条带附近。这样的构造引起雪崩电流的更大部分直接流过p型柱/柱形物/条带并且分散到源极金属，并且通过这样做，有效地避免围绕源极/发射极区的高电流密度以及随后接通寄生BJT（这能够另外毁坏器件）。栅极沟槽1138的深度可以变化以调整栅极电荷和栅极电阻。
图12图示具有体接触与介电间隔部的半导体器件1200的实施例的部分横截面视图。图12中示出的实施例与图10和11Q中示出的实施例类似。然而，不同的是，半导体器件1200还包括肖特基势垒二极管1202，其形成在半导体衬底102中位于形成于衬底102中的相邻体接触开口/凹槽130之间。肖特基势垒二极管1202通过沿着肖特基势垒二极管1202的每个纵向侧延伸的相应接触开口/凹槽130而与每个邻近栅极沟槽104间隔开。由每个相邻接触开口/凹槽130形成的半导体衬底102的一个侧壁1204邻接肖特基势垒二极管1202。肖特基势垒二极管1202包括肖特基接触1206，其位于形成于衬底102中的邻近接触开口/凹槽130之间的半导体衬底102的前面106上。任何适合的金属或金属硅化物可以用于肖特基接触1206。p+半导体材料的护环1208可以被提供在肖特基势垒二极管1202的边缘周围，从而围绕肖特基接触1206。在瞬时事件期间，在肖特基结被大水平的反向电流流动损坏之前，护环1208将相邻半导体区驱动到雪崩击穿中。
肖特基势垒二极管1202具有低泄漏、低正向电压，并且当与功率MOSFET合并时具有低反向恢复电荷Qrr。具有由第二导电类型的柱/柱形物/条带区702和第一导电类型的漂移区120形成的下伏超级结结构的栅极沟槽104位于栅极区和二极管台面二者的侧面。当器件1200既在肖特基势垒处又在晶体管的体二极管处断开时，位于接触开口/凹槽130的底部处的体接触136下面的超级结结构减小泄漏。器件区的导电类型在图12中可以被反转以实现p沟道器件而不是n沟道器件。
为了易于描述而使用空间相对术语，诸如“下面”、“下方”、“下部”、“上方”、“上部”等等来解释一个元件相对于第二元件的定位。这些术语意图包含除了与图中描绘的那些不同的定向之外的器件的不同定向。此外，诸如“第一”、“第二”等等之类的术语还用于描述各种元件、区、区段等，并且也不意图是限制性的。贯穿本描述，相似的术语指代相似的元件。
如在本文中使用的，术语“具有”、“含有”、“包含”、“包括”等等是开放式的术语，其指示说明的元件或特征的存在但是不排除附加的元件或特征。冠词“一”、“一个”和“该”旨在包括复数以及单数，除非上下文清楚地另外指示。
考虑到变化和应用的以上范围，应该理解的是，本发明不由前述描述限制，它也不由附图限制。代替地，本发明仅由所附权利要求及其法律等同物限制。

Claims (28)

1.一种半导体器件，包括：
延伸到半导体衬底的第一主表面中的沟槽；
在所述沟槽中的栅极电极和栅极电介质，所述栅极电介质使所述栅极电极与所述半导体衬底分离；
具有第一导电类型的第一区，所述第一区被形成在所述半导体衬底中位于第一表面处并且与所述沟槽相邻；
具有第二导电类型的第二区，所述第二区被形成在所述半导体衬底中位于所述第一区下方并且与所述沟槽相邻；
具有第一导电类型的第三区，所述第三区被形成在所述半导体衬底中位于所述第二区下方并且与所述沟槽相邻；
在所述半导体衬底中的接触开口，所述接触开口延伸到所述第二区中；
电绝缘间隔部，所述电绝缘间隔部位于由所述接触开口形成的所述半导体衬底的侧壁上；以及
导电材料，所述导电材料位于所述接触开口中并且邻接由所述接触开口形成的所述半导体衬底的侧壁上的电绝缘间隔部。
2.根据权利要求1所述的半导体器件，其中所述电绝缘间隔部沿着由所述接触开口形成的所述半导体衬底的侧壁而凹陷在所述半导体衬底的第一主表面下方。
3.根据权利要求1所述的半导体器件，其中所述接触开口在所述第二区内终止使得所述导电材料通过所述第二区的区段而与所述第三区分离。
4.根据权利要求3所述的半导体器件，此外包括被形成在所述第二区中与所述接触开口的底部相邻的第二导电类型的附加区，其中所述附加区比所述第二区更重地掺杂并且在所述接触开口的底部处邻接所述导电材料。
5.根据权利要求1所述的半导体器件，其中所述接触开口延伸通过所述第二区并且延伸到所述第三区中，使得所述导电材料延伸到所述第三区中。
6.根据权利要求5所述的半导体器件，此外包括第二导电类型的第一附加区，其被形成在所述第三区中并且在所述接触开口的底部处邻接所述导电材料。
7.根据权利要求6所述的半导体器件，此外包括形成在所述第三区中的第二导电类型的第二附加区，其中第二导电类型的第二附加区在所述接触开口的底部下方邻接第二导电类型的第一附加区，并且比所述沟槽和第二导电类型的第一附加区二者延伸到所述半导体衬底中如从第一主表面测量的更大的深度，并且其中第二导电类型的第一附加区比第二导电类型的第二附加区更重地掺杂。
8.根据权利要求7所述的半导体器件，此外包括在所述半导体衬底的与所述第一主表面相对的第二主表面处形成的第一导电类型的第一附加区，其中第一导电类型的第一附加区比所述第三区更重地掺杂，并且其中第二导电类型的第二附加区延伸到第一导电类型的第一附加区，并且与其邻接。
9.根据权利要求8所述的半导体器件，此外包括形成在所述第三区中位于所述沟槽下面的第一导电类型的第二附加区，其中第一导电类型的第一附加区比第一导电类型的第二附加区更重地掺杂，并且其中第二导电类型的第二附加区通过所述第三区的区段而与第一导电类型的第二附加区横向分离。
10.根据权利要求9所述的半导体器件，其中第一导电类型的第二附加区延伸到第一导电类型的第一附加区，并且与其邻接。
11.根据权利要求9所述的半导体器件，此外包括在所述沟槽中位于所述栅极电极下方的场板，其中所述场板与所述栅极电极电绝缘。
12.根据权利要求1所述的半导体器件，其中所述第二区的区段延伸到所述半导体衬底的第一主表面，其中所述第一区横向设置在所述沟槽与延伸到所述半导体衬底的第一主表面的所述第二区的区段之间，并且其中所述接触开口被形成在延伸到所述半导体衬底的第一主表面的所述第二区的区段中。
13.根据权利要求12所述的半导体器件，其中所述电绝缘间隔部沿着延伸到所述半导体衬底的第一主表面的所述第二区的区段的侧壁凹陷在所述半导体衬底的第一主表面下方，使得所述侧壁的上部部分没有所述电绝缘间隔部。
14.根据权利要求13所述的半导体器件，此外包括第二导电类型的第一附加区，其被形成在所述第二区中与没有所述电绝缘间隔部的侧壁的上部部分相邻，其中第二导电类型的第一附加区比所述第二区更重地掺杂并且沿着没有所述电绝缘间隔部的侧壁的上部部分而邻接所述导电材料。
15.根据权利要求14所述的半导体器件，其中所述接触开口延伸通过所述第二区并且延伸到所述第三区中，使得所述导电材料延伸到所述第三区中。
16.根据权利要求15所述的半导体器件，此外包括形成在所述第三区中的第二导电类型的第二附加区，其中第二导电类型的第二附加区比所述第二区更重地掺杂并且在所述接触开口的底部处邻接所述导电材料。
17.根据权利要求14所述的半导体器件，其中所述接触开口在所述第二区内终止，使得所述导电材料通过所述第二区的区段而与所述第三区分离。
18.根据权利要求17所述的半导体器件，此外包括被形成在所述第二区中与所述接触开口的底部相邻的第二导电类型的第二附加区，其中第二导电类型的第二附加区比所述第二区更重地掺杂并且在所述接触开口的底部处邻接所述导电材料。
19.根据权利要求1所述的半导体器件，此外包括在所述半导体衬底的第一主表面上的层间电介质，其中所述接触开口延伸通过所述层间电介质并且延伸到所述半导体衬底中，并且其中所述层间电介质中的接触开口的宽度比所述半导体衬底中的更大，使得所述导电材料在所述接触开口中具有阶梯式剖面。
20.根据权利要求1所述的半导体器件，此外包括在所述半导体衬底的第一主表面上的层间电介质，其中所述接触开口延伸通过所述层间电介质并且延伸到所述半导体衬底中，并且其中所述电绝缘间隔部延伸到所述半导体衬底的第一主表面上并且沿着由所述接触开口形成的所述层间电介质的侧壁延伸。
21.根据权利要求1所述的半导体器件，其中所述电绝缘间隔部延伸到所述半导体衬底的第一主表面上。
22.根据权利要求1所述的半导体器件，此外包括在与所述接触开口相邻的第二区的区段上形成的第二导电类型的附加区，其中第二导电类型的附加区比所述第二区更重地掺杂，其中所述第一区邻接第二导电类型的附加区的面对所述沟槽的侧表面，并且延伸到第二导电类型的附加区的前表面上，并且其中所述导电材料还邻接第二导电类型的附加区的前表面。
23.根据权利要求1所述的半导体器件，其中所述电绝缘间隔部包括氧化物、氮化物、碳或正硅酸乙酯。
24.根据权利要求1所述的半导体器件，其中所述半导体衬底的第一主表面的一部分在与所述接触开口相邻的区中凹陷，并且其中所述导电材料邻接所述第一主表面的凹陷部分。
25.根据权利要求1所述的半导体器件，此外包括肖特基势垒二极管，所述肖特基势垒二极管被形成在所述半导体衬底中位于所述接触开口的与所述沟槽相对的一侧处，使得所述肖特基势垒二极管通过所述接触开口而与所述沟槽间隔开，其中由所述接触开口形成的所述半导体衬底的侧壁之一邻接所述肖特基势垒二极管。
26.根据权利要求25所述的半导体器件，此外包括：
在所述半导体衬底的与所述第一主表面相对的第二主表面处形成的第一导电类型的第一附加区；以及
在所述接触开口下面的第三区中形成并且延伸到第一导电类型的第一附加区的第二导电类型的第一附加区，
其中第一导电类型的第一附加区比所述第三区更重地掺杂。
27.根据权利要求26所述的半导体器件，此外包括：
在所述半导体衬底中位于所述肖特基势垒二极管的背对所述沟槽的一侧处的附加接触开口；以及
在所述附加接触开口下面的第三区中形成并且延伸到第一导电类型的第一附加区的第二导电类型的第二附加区。
28.根据权利要求1所述的半导体器件，其中所述电绝缘间隔部沿着所述第一区的侧壁凹陷在所述半导体衬底的第一主表面下方，其中所述第一区包括与所述第一区的侧壁相邻的第二导电类型的第一附加区，并且其中所述第一区形成所述半导体器件的源极或集电极。
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