TWI524404B - Packaging substrate processing methods - Google Patents

Packaging substrate processing methods Download PDF

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TWI524404B
TWI524404B TW100102627A TW100102627A TWI524404B TW I524404 B TWI524404 B TW I524404B TW 100102627 A TW100102627 A TW 100102627A TW 100102627 A TW100102627 A TW 100102627A TW I524404 B TWI524404 B TW I524404B
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package substrate
substrate
resin
cutting
view
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TW100102627A
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TW201140674A (en
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Kazuma Sekiya
Koichi Kondo
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Disco Corp
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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  • Engineering & Computer Science (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

封裝基板之加工方法 技術領域
本發明係有關於一種複數半導體晶片經樹脂密封之封裝基板的加工方法。
背景技術
在半導體裝置的製造程序中，形成有LSI等迴路之複數半導體晶片安裝於引線框架或印刷基板且各電極經接合連接後，藉由利用樹脂密封來形成CSP(晶片尺寸包裝(Chip Size Package))基板或BGA(球形陣列(Ball Grid Array))基板等封裝基板。
其後，藉由將封裝基板以切削刀片等切割而單分化，來製造經樹脂密封之各個半導體裝置。如此所製造之半導體裝置係廣泛利用於行動電話或電腦等電子機器。
隨著近年電子機器之小型化/薄型化，半導體裝置之小型化/薄型化亦受到殷切期待，在半導體裝置之製造程序中，有以下期望：希望能研磨半導體晶片經樹脂密封之封裝基板的樹脂密封面而薄化之。
就封裝基板的研磨而言，例如日本特開2008-272866號公報所揭示之被稱為研磨器的研磨裝置係受到廣泛使用。該種研磨裝置具備吸引保持封裝基板等被研磨物的保持台，以及與保持台所保持之被研磨物對向配設之研磨石，並藉由研磨石在砥接於被研磨物的狀態下滑動來執行研 磨。
[習知技術文獻] [專利文獻]
[專利文獻1]特開2008-272866號公報
發明揭示
然而，由於以樹脂密封半導體晶片時熱的影響等，在封裝基板上容易產生翹曲。即便欲以研磨裝置的保持台來吸引保持有翹曲的封裝基板，因從封裝基板與保持台沒有密接的部分洩漏負壓，而無法保持封裝基板，故有無法研磨封裝基板的問題。
本發明係有鑑於此點而完成者，其目的在於提供一種封裝基板的加工方法，係可製造將即使具有翹曲之基板研磨而成薄型半導體裝置。
依據本發明，提供一種封裝基板之加工方法，該封裝基板係將半導體晶片固定於由形成格子狀之複數的分割預定線所劃分之基板上的各區域，並以樹脂密封，具有樹脂面與該樹脂面之相反側的電極面者；該封裝基板之加工方法的特徵在於具有：翹曲修正步驟，其係自該封裝基板之樹脂面側或電極面側沿著分割預定線以切削刀片切削而形成切削溝，修正該封裝基板的翹曲；以及研磨步驟，係在實施了該翹曲修正步驟後，以保持台來保持該封裝基板的 該電極面側，並研磨該樹脂面，將該封裝基板薄化成為預定之厚度。
較佳地，在前述翹曲修正步驟中，自前述封裝基板之前述電極面側沿著前述分割預定線以前述切削刀片切割該封裝基板，而形成達到前述預定厚度之切削溝。
較佳地，封裝基板的加工方法係在實施前述翹曲修正步驟前，更具備支持構件配設步驟，係將支持構件配設於前述封裝基板之前述電極面側者；前述翹曲修正步驟係自前述封裝基板之前述樹脂面側沿著前述分割預定線以前述切削刀片切割該封裝基板而形成達到該支持構件之切削溝。
依據本發明之封裝基板的加工方法，因藉由形成於封裝基板之切削溝修正封裝基板之翹曲之故，即便是具有翹曲之封裝基板亦可以研磨裝置之保持台來吸引保持來執行研磨，而可製造薄型半導體裝置。
圖式簡單說明
第1圖係CSP基板之平面圖。
第2圖係第1圖所示之CSP基板的背面圖。
第3圖係BGA基板的平面圖。
第4圖係第3圖所示之BGA基板的背面圖。
第5圖係自電極面側切削之本發明之第1實施型態的流程圖。
第6圖係切削步驟的截面圖。
第7圖係表示保護構件配設步驟的分解透視圖。
第8圖係表示研磨步驟的側面圖。
第9圖係表示拾取步驟的截面圖。
第10圖係自樹脂面側切削之本發明之第2實施型態的流程圖。
第11圖係表示支持構件配設步驟的分解透視圖。
第12圖係表示切削步驟的截面圖。
第13圖係表示研磨步驟的側面圖。
第14圖係表示拾取步驟的截面圖。
用以實施發明之形態
以下，參照圖示來詳細地說明本發明之實施型態。參照第1圖，表示有作為本發明之加工方法的對象之封裝基板的一例之平面圖。封裝基板2係CSP基板，具有矩形的金屬框4。就由金屬框4之外周剩餘區域5與非晶片區域5a所圍繞之區域而言，在圖示之例中存在有3個晶片區域6a、6b及6c。
在各晶片區域6a、6b及6c中，由彼此垂直相交而設置成格子狀之第1及第2分割預定線8a及8b所劃分之各區域定義出晶片形成部10，且在各個晶片形成部10形成有複數之電極12。在晶片形成部10之背面側，半導體晶片係以DAF(晶粒黏著薄膜，Die Attach Film)黏貼。
各電極12彼此係藉由注塑到金屬框4之樹脂絕緣。藉由切削第1分割預定線8a及第2分割預定線8b，在其兩側顯出各半導體晶片的電極12。在金屬框4之四角落形成有圓孔18。參照第2圖，係表示第1圖所示之封裝基板2的背面圖。 各晶片區域6a、6b及6c的背面側係以成形樹脂16覆蓋。
參照第3圖，係表示封裝基板之其他例的平面圖。封裝基板20係BGA基板，係在樹脂基板22上安裝複數之半導體晶片而構成。
如第3圖之部分擴大圖所示，由彼此垂直相交而設置成格子狀之第1及第2分割預定線24a及24b所劃分之各區域定義出晶片形成部10。在各晶片形成部26的4邊突出有球狀電極28。參照第4圖，表示第3圖所示之封裝基板20的背面圖。搭載於樹脂基板22之各半導體晶片係以成形樹脂30覆蓋。
如第1圖及第2圖所示之封裝基板2以及如第3圖及第4圖所示之封裝基板20，在利用樹脂密封半導體時因熱的影響，一般會產生翹曲。針對可加工薄化這種產生有翹曲之封裝基板的本發明之實施型態的封裝基板加工方法，參照第5至14圖於以下進行說明。
參照第5圖，係表示自電極面側切削之本發明第1實施形態之加工方法的流程圖。首先以步驟S10，實施應當切削之封裝基板2的調正。即，使封裝基板2與切削刀片平行化，測得應當切削之分割預定線8a及8b。
調正實施後，進入步驟S11，如第6圖所示一邊以切削裝置之圖未示的保持台吸引保持成形樹脂16側，一邊自封裝基板2之電極面4a側使切削刀片32切入至預定厚度(裝置的完成厚度)t1以上之深度為止，沿著分割預定線8a及8b形成複數的切削溝34，而修正封裝基板2之翹曲(翹曲修正步驟)。
在第6圖所示之翹曲修正步驟中，係以切削裝置的保持台直接吸引保持成形樹脂16而形成切削溝34，然而在成形樹脂16側配設有切割膠帶(dicing tape)等黏著帶時，亦可實施將切削刀片32切入至黏著帶為止之全切割。
在實施翹曲修正步驟後，進入步驟S12而如第7圖所示，於封裝基板2之電極面4配設保護帶等的保護構件36。在將成形樹脂16側黏貼於黏著帶時，於步驟S12的前或後除去黏著帶。
接著，進入步驟S13，如第8圖所示以研磨裝置的保持台38隔著保護構件36吸引保持封裝基板2，研磨封裝基板2的樹脂面16a側而將封裝基板2薄化成為預定厚度t1。
亦即，將保持台38以例如300rpm旋轉，並一邊使固定有複數研磨石42之研磨輪40以例如6000rpm旋轉，一邊使其抵接於封裝基板2的樹脂面來研磨樹脂16，而將封裝基板2薄化成預定厚度t1。
此時，如第6圖所示，在沒有以切削刀片32將封裝基板2全切割時，藉由實施該研磨步驟使切削溝34露出於樹脂面16a表面，而將封裝基板2分割成各個半導體裝置44。
接著，進入步驟S14，將各半導體裝置44從保護構件36移除。亦即，如第9圖所示，以拾取裝置的拾取筒夾(pickup collet)46拾取經個別分割之半導體裝置44。
參照第10圖，係表示自樹脂面側切削之本發明第2實施形態之加工方法的流程圖。在本實施形態中，首先以步驟S20將支持構件配設於封裝基板2的電極面4a側。
亦即，如第11圖所示，將封裝基板2之電極面4a側黏貼於外周部黏貼於環狀框52之切割膠帶等的黏著帶50。藉此，封裝基板2係隔著黏著帶50而由環狀框52所支持之狀態。
接著，進入步驟S21來實施封裝基板2的調正步驟。即，使封裝基板2與切削刀片32平行化，並測得應當切削之分割預定線8a及8b。該調正係以形成於封裝基板2之四個角落的圓孔18為基準來實施。
接著，進入步驟S22，如第12圖所示一邊以切削裝置之圖未示的保持台吸引保持黏著帶50側，一邊使切削刀片32自樹脂面16a側切入至作為支持構件之黏著帶50，沿著分割預定線8a及8b形成複數切削溝54來修正封裝基板2的翹曲(翹曲修正步驟)。
翹曲修正步驟實施後，進入步驟S23而實施將封裝基板2薄化成預定厚度t1之研磨步驟。即，如第13圖所示，以永久磁石等的框固定構件56固定環狀框，以研磨裝置之保持台38隔著黏著帶50來吸引保持封裝基板2。
將保持台38朝箭頭A方向以例如300rpm旋轉，並使研磨石42抵接於封裝基板2之樹脂面16，使研磨輪40朝箭頭B方向以例如6000rpm旋轉來研磨封裝基板2的成形樹脂16，而將封裝基板2薄化成預定厚度t1。
研磨步驟實施後，進入步驟S24，將各半導體裝置44自支持構件移除。即，如第14圖所示，以拾取裝置的拾取筒夾46自黏著帶50拾取半導體裝置44。
2‧‧‧封裝基板(CSP基板)
4‧‧‧金屬框
4a‧‧‧電極面
5‧‧‧外周剩餘區域
5a‧‧‧非晶片區域
6a、6b、6c‧‧‧晶片領域
8a、8b‧‧‧分割預定線
10‧‧‧晶片形成部
12‧‧‧電極
14‧‧‧半導體晶片
15‧‧‧DAF
16‧‧‧成形樹脂
16a‧‧‧樹脂面
18‧‧‧圓孔
20‧‧‧封裝基板(BGA基板)
22‧‧‧樹脂基板
24a、24b‧‧‧分割預定線
26‧‧‧晶片形成部
28‧‧‧球狀電極
30‧‧‧成形樹脂
32‧‧‧切削刀片
34‧‧‧切削溝
36‧‧‧保護構件(保護帶)
38‧‧‧保持台
40‧‧‧研磨輪
42‧‧‧研磨石
44‧‧‧半導體裝置
46‧‧‧拾取筒夾
50‧‧‧黏著帶
52‧‧‧環狀框
54‧‧‧切削溝
S10-S14、S20-S24‧‧‧步驟
t1‧‧‧預定厚度(裝置的完成厚度)
第1圖係CSP基板之平面圖。
第2圖係第1圖所示之CSP基板的背面圖。
第3圖係BGA基板的平面圖。
第4圖係第3圖所示之BGA基板的背面圖。
第5圖係自電極面側切削之本發明之第1實施型態的流程圖。
第6圖係切削步驟的截面圖。
第7圖係表示保護構件配設步驟的分解透視圖。
第8圖係表示研磨步驟的側面圖。
第9圖係表示拾取步驟的截面圖。
第10圖係自樹脂面側切削之本發明之第2實施型態的流程圖。
第11圖係表示支持構件配設步驟的分解透視圖。
第12圖係表示切削步驟的截面圖。
第13圖係表示研磨步驟的側面圖。
第14圖係表示拾取步驟的截面圖。
S10、S11、S12、S13、S14‧‧‧步驟

Claims (1)

  1. 一種封裝基板之加工方法，該封裝基板係將半導體晶片固定於由形成格子狀之複數的分割預定線所劃分之基板上的各區域，並以樹脂密封，且具有樹脂面與該樹脂面之相反側的電極面；該封裝基板之加工方法的特徵在於具有：支持構件配設步驟，係將支持構件配設於前述封裝基板之前述電極面側；翹曲修正步驟，係在實施前述支持構件配設步驟後，自該樹脂面側沿著該分割預定線以切削刀片切入該封裝基板，形成達到該支持構件之切削溝，藉而修正該封裝基板的翹曲；以及研磨步驟，係在實施該翹曲修正步驟後，以保持台來保持該封裝基板的該電極面側，並研磨該樹脂面，將該封裝基板薄化成為預定之厚度。
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US10522452B2 (en) 2011-10-18 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates
JP2015085414A (ja) * 2013-10-29 2015-05-07 株式会社ディスコ パッケージ基板の加工方法
JP2015093338A (ja) * 2013-11-11 2015-05-18 株式会社ディスコ パッケージ基板の加工方法
JP6257291B2 (ja) * 2013-12-04 2018-01-10 株式会社ディスコ パッケージ基板の加工方法
JP6282194B2 (ja) * 2014-07-30 2018-02-21 株式会社ディスコ ウェーハの加工方法
JP2016082192A (ja) * 2014-10-22 2016-05-16 株式会社ディスコ パッケージ基板の分割方法
JP6448302B2 (ja) * 2014-10-22 2019-01-09 株式会社ディスコ パッケージ基板の研削方法
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JP6887722B2 (ja) * 2016-10-25 2021-06-16 株式会社ディスコ ウェーハの加工方法及び切削装置
JP6896326B2 (ja) * 2017-03-06 2021-06-30 株式会社ディスコ 加工装置
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JP2001094005A (ja) * 1999-09-22 2001-04-06 Oki Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
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JP2005209719A (ja) * 2004-01-20 2005-08-04 Disco Abrasive Syst Ltd 半導体ウエーハの加工方法
JP2007311378A (ja) * 2006-05-16 2007-11-29 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP5064102B2 (ja) 2007-04-27 2012-10-31 株式会社ディスコ 基板の研削加工方法および研削加工装置
JP2009070880A (ja) * 2007-09-11 2009-04-02 Nec Electronics Corp 半導体装置の製造方法
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