JP2019121722A - パッケージ基板の製造方法 - Google Patents
パッケージ基板の製造方法 Download PDFInfo
- Publication number
- JP2019121722A JP2019121722A JP2018001631A JP2018001631A JP2019121722A JP 2019121722 A JP2019121722 A JP 2019121722A JP 2018001631 A JP2018001631 A JP 2018001631A JP 2018001631 A JP2018001631 A JP 2018001631A JP 2019121722 A JP2019121722 A JP 2019121722A
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- Prior art keywords
- mold resin
- mold
- flat surface
- temperature
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 51
- 229920005989 resin Polymers 0.000 claims abstract description 51
- 238000000465 moulding Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 238000010304 firing Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 11
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 3
- 238000001354 calcination Methods 0.000 abstract 6
- 238000003825 pressing Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
8:デバイス
12:モールド金型
22:モールド樹脂
26:第一の基台
26a:第一の平坦面
28:第二の基台
28a:第二の平坦面
30:パッケージ基板
Claims (3)
- デバイスに対応した配線パターンが分割予定ラインによって区画されて複数形成された配線基板に複数のデバイスが配設されモールド樹脂で封止されたパッケージ基板の製造方法であって、
複数のデバイスが配設された配線基板をモールド金型で囲繞しモールド樹脂を供給するモールド樹脂供給工程と、
モールド樹脂を本焼成の温度に至らない比較的低い温度で仮焼成する仮焼成工程と、
該モールド金型から配線基板を外すモールド金型外し工程と、
第一の平坦面を備えた第一の基台に配線基板を載置し、該第一の平坦面と平行な第二の平坦面を備えた第二の基台で配線基板を押圧すると共に本焼成の温度で加熱し、仮焼成されたモールド樹脂の厚みを均一にして本焼成する本焼成工程と、
から少なくとも構成されるパッケージ基板の製造方法。 - 配線基板は、2以上のグループに分けて配線パターンが形成されている請求項1記載のパッケージ基板の製造方法。
- 該モールド樹脂は液状エポキシ樹脂であり、仮焼成の温度は160〜180℃であり、本焼成の温度は250〜270℃である請求項1記載のパッケージ基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018001631A JP2019121722A (ja) | 2018-01-10 | 2018-01-10 | パッケージ基板の製造方法 |
CN201910003750.7A CN110034024A (zh) | 2018-01-10 | 2019-01-03 | 封装基板的制造方法 |
US16/241,285 US11096287B2 (en) | 2018-01-10 | 2019-01-07 | Method of manufacturing packaged board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018001631A JP2019121722A (ja) | 2018-01-10 | 2018-01-10 | パッケージ基板の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2019121722A true JP2019121722A (ja) | 2019-07-22 |
Family
ID=67140281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018001631A Pending JP2019121722A (ja) | 2018-01-10 | 2018-01-10 | パッケージ基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11096287B2 (ja) |
JP (1) | JP2019121722A (ja) |
CN (1) | CN110034024A (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019121722A (ja) * | 2018-01-10 | 2019-07-22 | 株式会社ディスコ | パッケージ基板の製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0917816A (ja) * | 1995-06-29 | 1997-01-17 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JP2001024001A (ja) * | 1999-07-12 | 2001-01-26 | Matsushita Electronics Industry Corp | 樹脂封止型半導体装置の製造方法及びリードフレーム |
JP2003246838A (ja) * | 2002-02-27 | 2003-09-05 | Arakawa Chem Ind Co Ltd | エポキシ樹脂組成物、電子材料用樹脂組成物、電子材料用樹脂、コーティング剤およびコーティング剤硬化膜の製造方法 |
JP2005123456A (ja) * | 2003-10-17 | 2005-05-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2006032471A (ja) * | 2004-07-13 | 2006-02-02 | Disco Abrasive Syst Ltd | Csp基板の製造方法 |
JP2011054771A (ja) * | 2009-09-02 | 2011-03-17 | Elpida Memory Inc | 半導体装置製造用冶具及び半導体装置製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2890662B2 (ja) * | 1990-04-25 | 1999-05-17 | ソニー株式会社 | 樹脂封止型半導体装置の製造方法とそれに用いるリードフレーム |
JPH11121488A (ja) * | 1997-10-15 | 1999-04-30 | Toshiba Corp | 半導体装置の製造方法及び樹脂封止装置 |
JP3876109B2 (ja) * | 2000-03-29 | 2007-01-31 | 松下電器産業株式会社 | 電子回路形成品の製造方法 |
JP5465042B2 (ja) * | 2010-03-01 | 2014-04-09 | 株式会社ディスコ | パッケージ基板の加工方法 |
JP2019121722A (ja) * | 2018-01-10 | 2019-07-22 | 株式会社ディスコ | パッケージ基板の製造方法 |
FR3093230B1 (fr) * | 2019-02-27 | 2023-01-06 | St Microelectronics Tours Sas | Boîtier de puce électronique |
-
2018
- 2018-01-10 JP JP2018001631A patent/JP2019121722A/ja active Pending
-
2019
- 2019-01-03 CN CN201910003750.7A patent/CN110034024A/zh active Pending
- 2019-01-07 US US16/241,285 patent/US11096287B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0917816A (ja) * | 1995-06-29 | 1997-01-17 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JP2001024001A (ja) * | 1999-07-12 | 2001-01-26 | Matsushita Electronics Industry Corp | 樹脂封止型半導体装置の製造方法及びリードフレーム |
JP2003246838A (ja) * | 2002-02-27 | 2003-09-05 | Arakawa Chem Ind Co Ltd | エポキシ樹脂組成物、電子材料用樹脂組成物、電子材料用樹脂、コーティング剤およびコーティング剤硬化膜の製造方法 |
JP2005123456A (ja) * | 2003-10-17 | 2005-05-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2006032471A (ja) * | 2004-07-13 | 2006-02-02 | Disco Abrasive Syst Ltd | Csp基板の製造方法 |
JP2011054771A (ja) * | 2009-09-02 | 2011-03-17 | Elpida Memory Inc | 半導体装置製造用冶具及び半導体装置製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN110034024A (zh) | 2019-07-19 |
US20190215966A1 (en) | 2019-07-11 |
US11096287B2 (en) | 2021-08-17 |
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