TWI511263B - 堆疊式晶粒嵌入晶片增層之系統及方法 - Google Patents

堆疊式晶粒嵌入晶片增層之系統及方法 Download PDF

Info

Publication number
TWI511263B
TWI511263B TW099105354A TW99105354A TWI511263B TW I511263 B TWI511263 B TW I511263B TW 099105354 A TW099105354 A TW 099105354A TW 99105354 A TW99105354 A TW 99105354A TW I511263 B TWI511263 B TW I511263B
Authority
TW
Taiwan
Prior art keywords
wafer
redistribution layer
redistribution
layer
embedded
Prior art date
Application number
TW099105354A
Other languages
English (en)
Other versions
TW201041117A (en
Inventor
Paul Alan Mcconnelee
Kevin M Durocher
Donald Paul Cunningham
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of TW201041117A publication Critical patent/TW201041117A/zh
Application granted granted Critical
Publication of TWI511263B publication Critical patent/TWI511263B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

堆疊式晶粒嵌入晶片增層之系統及方法
本發明之實施例大致上係關於積體電路封裝，且更特定言之，本發明之實施例係關於使用直接與晶片焊墊或電組件連接墊連接之低阻抗金屬互連件，以容許更高裝置速度、更低電力損耗及更小尺寸的嵌入晶片增層。嵌入晶片封裝可被製造為具有以一堆疊式3D配置之複數個晶片或電子組件。該複數個晶片或電子組件係藉透過複數個層壓重新分佈層佈線之金屬互連件而電連接至一輸入/輸出系統。
隨著積體電路逐漸變小並產出更佳操作效能，積體電路(IC)封裝所用之封裝技術業已相應自引線封裝進化至層壓為基礎之球柵陣列(BGA)封裝、晶片尺寸封裝(CSP)，繼而至倒裝晶片封裝以及當前之嵌入晶片增層封裝。IC晶片封裝技術之進步係由對實現更佳效能、更小化及更高可靠性之需要加以推動。新封裝技術須要進一步為因大規模製造以容許擴大規模獲得之經濟節約之意圖而批量產製的可能性提供必要條件。
鑑於晶片尺寸封裝係合併多個、堆疊式晶片，該等晶片通常係以打線接合至基板，從而引致高電阻、電感及電容，導致降級之裝置速度及更高電力損耗。倒裝晶片晶粒可不合宜於被3D堆疊且多數受限於並排平面晶粒配置，該等配置使用較大封裝區域或封裝堆疊，藉此導致更高3D結構。因慮及複合裝置最終測試損耗及增加產製成本之組裝良率損耗，故經依序堆疊及打線接合之諸晶片係不可預測試為一單獨封裝晶片。
IC晶片封裝要求之進步亦引起對現存嵌入晶片增層處理之挑戰。亦即，期望在許多當前之嵌入晶片封裝中具有增加數目之重新分佈層，通常具有八個或更多個重新分佈層。標準嵌入晶片增層處理(其中一個或多個晶粒係初始置於IC基板上且重新分佈層係隨後以逐層方式施加)可引致重新佈線及互連系統中之翹曲，從而要求使用一經模製之環氧壓力平衡層或金屬補強板。
相應言之，存在一種對容許施加具有經改良電互連效能之以一堆疊式配置之多個晶粒的嵌入晶片製造方法的需要。進一步存在對提供一較短製造週期時間並容許在不使用補強板之情形下最小化該封裝之翹曲可施加多個重新分佈層的嵌入晶片製造之需要。
本發明之實施例係藉提供一種晶片製造方法來克服前述缺陷，在該方法中嵌入晶片封裝中之晶片或電組件係以一堆疊式配置而提供且藉一直接金屬連接而連接至一輸入/輸出(I/O)系統。複數個經圖案化之層壓層(其中具有金屬互連件)將每一晶片或電子組件直接連接至該I/O系統。
根據本發明之一態樣，一種嵌入晶片封裝包括於一垂直方向上結合在一起以形成一層壓堆疊之複數個重新分佈層，其中每一重新分佈層包含形成於其中之複數個介層孔。該嵌入晶片封裝亦包括嵌入於該層壓堆疊中並包括複數個晶片墊之一第一晶片；附接至該層壓堆疊且相對於該第一晶片而堆疊於垂直方向上之一第二晶片，該第二晶片包括複數個晶片墊；及定位於該層壓堆疊之一最外重新分佈層上之一輸入/輸出(I/O)系統。該嵌入晶片封裝進一步包括電耦合至該I/O系統且經組態以將該第一晶片及該第二晶片電連接至該I/O系統之複數個金屬互連件，其中該複數個金屬互連件之每一者係延伸穿過一各自介層孔以與一相鄰重新分佈層上之一金屬互連件及第一或第二晶片上之一晶片墊之一者形成一直接金屬連接。
根據本發明之另一態樣，一種形成一嵌入晶片封裝之方法包括提供一初始聚合物層壓層及固定至該初始聚合物層壓層之一第一晶片，該第一晶片之上具有數個晶片墊。該方法亦包括圖案化該初始聚合物層壓層以包括複數個介層孔及複數個金屬互連件，使得該複數個金屬互連件之一部分係向下延伸穿過各自介層孔並直接金屬連接至該第一晶片上之該等晶片墊；提供一額外晶片，並提供複數個額外聚合物層壓層，其中該複數個額外聚合物層壓層之一部分包括形成於其中用於第一晶片及額外晶片之一者之佈置的一晶片開口。該方法進一步包括將該額外晶片及該複數個額外聚合物層壓層之每一者選擇性耦合至初始聚合物層壓層，且在耦合該複數個額外聚合物層壓層之每一者之後，選擇性圖案化該額外聚合物層壓層以包括複數個介層孔及複數個金屬互連件，使得該複數個金屬互連件之每一者延伸穿過一各自介層孔並直接金屬連接至一相鄰聚合物層壓層上之一金屬互連件及額外晶片上之一晶片墊之一者。該方法亦包括將複數個輸入/輸出(I/O)連接電耦合至複數個額外聚合物層壓層之一最外聚合物層壓層上的金屬互連件，其中該等I/O連接係藉該複數個金屬互連件而電連接至第一晶片且電連接至額外晶片。
根據本發明之又一態樣，一種用於製造一晶圓級封裝之方法包括提供複數個晶片，該複數個晶片之每一者具有形成於其上之數個晶片墊；及提供複數個聚合物層壓層，其中該複數個聚合物層壓層之一部分包括形成於其中用於其中該複數個晶片之一者之佈置的一晶片開口。該方法亦包括使用該複數個晶片及該複數個聚合物層壓層來裝配一晶圓級封裝，其中裝配該晶圓級封裝包括將一第一晶片施加於一初始聚合物層壓層，並圖案化該初始聚合物層壓層以包括複數個介層孔及複數個金屬互連件，其中該複數個金屬互連件之每一者係向下延伸穿過一各自介層孔以將該初始聚合物層壓層電耦合至第一晶片。裝配該晶圓級封裝亦包括以一堆疊式配置而將額外聚合物層壓層級額外晶片選擇性施加於該初始聚合物層壓層及該第一晶片，且在施加每一額外聚合物層壓層之後，圖案化該額外聚合物層壓層以形成複數個介層孔及向下延伸穿過該等介層孔之複數個金屬互連件，使得每一額外聚合物層壓層中之金屬互連件將該聚合物層壓層電耦合至一先前所施加之額外聚合物層壓層或一先前所施加之額外晶片。
此等及其他優點及特徵將經由結合附圖而提供的本發明之諸較佳實施例之下文之詳述而更易於瞭解。
諸附圖繪示當前經考量用於執行本發明之諸實施例。
本發明提供一種形成一嵌入晶片封裝之方法。該嵌入晶片封裝係使用經圖案化之層壓重新分佈層及晶片或電組件相對於該等經圖案化層之佈置來製造。該嵌入晶片封裝中之晶片/電組件係以一堆疊式配置提供且藉在該等經圖案化之層壓重新分佈層中形成之金屬互連件所提供之一直接金屬連接而連接至一輸入/輸出(I/O)系統。
本發明之實施例係針對於一嵌入晶片封裝(ECP)之增層，該ECP之中包括嵌入於複數個經圖案化之層壓重新分佈層內並以一3D堆疊式配置加以配置的複數個晶片(即晶粒)及/或電組件。雖然嵌入該ECP中之晶片及/或電組件係在下文圖1至圖12之實施例中特定參照為晶片，但應瞭解其他電組件可替代ECP中之晶片，且因此本發明之實施例係不僅限於在一ECP中堆疊晶片/晶粒。即，使用下文所述之ECP實施例中之晶片亦應被瞭解為包含可以一堆疊式配置提供於ECP中之其他電組件，諸如電阻器、電容器、電感器或其他類似裝置。
參照圖1，其中根據本發明之一例示性實施例顯示複數個已製造之ECP 10或嵌入晶片模組。每一ECP 10包括與複數個重新分佈層14(即層壓層)連接並嵌入其中之一個或多個晶片12(即晶粒)。每一晶片12係由一半導體材料(諸如矽或GaAs)形成並經製備以使得在其表面上形成一積體電路(IC)佈局。該複數個重新分佈層14之每一者係具可相對於該/該等晶片12佈置之一預形成之層壓薄片或薄膜的形式。該等重新分佈層14可由Kapton、Ultem、聚四氟乙烯(PTFE)或另一聚合物薄膜，諸如液晶聚合物(LCP)或聚醯亞胺材料形成。如圖1所示，每一ECP 10係藉由在鄰接之諸ECP 10之間之一區域中將重新分佈層14切塊而形成。
參照圖2至圖10，其中闡述根據本發明之一實施例的一種用於製造複數個嵌入晶片封裝(ECP)10之技術。如圖2所示，嵌入晶片增層處理起始於一初始重新分佈層16之一完整框架，該完整框架係設置及安裝於一框架18上以容許在其上執行額外製造步驟。如上所述，初始重新分佈層16係具有一可撓性聚合物層壓層，諸如Kapton、Ultem、聚四氟乙烯(PTFE)或另一聚合物/聚醯亞胺薄膜之形式，且具有容許自其產製複數個ECP 10之一尺寸。該初始重新分佈層16包括其上預圖案化區域20及非圖案化區域22，其中該非圖案化區域22對應於晶片區域(其中將佈置一晶片)。
圖3A至圖3B顯示初始重新分佈層16之完整框架之一部分。根據本發明之一實施例，如圖3A所示，該初始重新分佈層16係提供為在該預圖案化區域20中具有形成於其上之複數個基本金屬互連件18之一「預圖案化」層。一黏合層24係施加於初始重新分佈層16之一側且一晶片26(即第一晶片)係佈置於非圖案化區域22中。在本發明之一例示性實施例中，晶片26具有一經減小之厚度，使得該晶片之總體厚度係大約為初始重新分佈層16及/或隨後施加之重新分佈層之總體厚度的1至3倍。將如後附圖形繪示，此「超薄」晶片26因此具有遠小於總體ECP 10之厚度的一厚度。
如圖3B所示，在施加晶片26之後，進一步圖案化初始重新分佈層16以形成複數個經鑽孔穿過形成此重新分佈層的聚合物材料之介層孔28。該等介層孔28係形成於對應於基本金屬互連件18之位置處，以便曝露該等基本金屬互連件18。額外介層孔28係向下鑽孔至晶片上之墊30，以便曝露此等墊。根據本發明之一例示性實施例，該等介層孔28係藉一雷射消融或雷射鑽孔而形成。或者，亦可認定介層孔28可藉包括下列之其他方法而形成：電漿蝕刻、定影(photo-definition)或機械鑽孔處理。一金屬層/材料32(例如催化金屬及/或銅)係接著藉由例如一濺鍍或電鍍處理而施加至重新分佈層16上，並接著形成於金屬互連件34中。根據本發明之一實施例，金屬層/材料32被圖案化及蝕刻，以使得金屬互連件34經形成以自初始重新分佈層16之一前/頂表面36延伸並向下延伸穿過介層孔28。金屬互連件34因此形成與基本金屬互連件18之一電連接以及對晶片墊30之一直接金屬及電連接。
現參照圖4，在該製造技術之一下一步驟中，額外重新分佈層38、40係層壓至初始重新分佈層16上。額外重新分佈層38、40包括分別施加於該初始重新分佈層16之前表面及後表面的一未切割重新分佈層38及一預切割重新分佈層40。一晶片開口42(或複數個晶片開口)係在將該預切割重新分佈層層壓至初始重新分佈層16之前穿過其而形成。該晶片開口42係具基本上匹配待佈置於其中之一晶片(即晶片26)之尺寸及形狀的一尺寸及形狀。如圖4所示，預切割重新分佈層40所形成之形狀係具一「窗框」建構。雖然預切割重新分佈層40係在圖4中顯示為具有匹配晶片26厚度之一厚度的一單一層，但亦可認定可施加具有匹配晶片26厚度之一總體厚度的多個(例如2個或3個)重新分佈層，而替代單一預切割重新分佈層40。
如圖4所示，一黏合層24係施加於未切割重新分佈層38及預切割重新分佈層40之每一者的一側上，以待諸如藉由一層壓、旋轉或噴濺處理而貼合至初始重新分佈層16。因此，根據本發明之一例示性實施例，該初始重新分佈層16形成一「中央」重新分佈層，且額外重新分佈層38、40係施加於初始重新分佈層16之前/頂表面36及後/底表面44兩者。此種雙側層壓處理係致力於減小給予該初始重新分佈層16之壓力並避免其發生翹曲。如圖4所示，預切割重新分佈層40相較於該初始重新分佈層16具有一增加之厚度。根據一實施例，預切割重新分佈層40具有等於晶片26厚度之一厚度，使得晶片26之一後/底表面46係與預切割重新分佈層40之一後/底表面48對準。
現參照圖5，複數個介層孔28係形成於額外重新分佈層38、40之每一者中。金屬互連件34亦經形成/圖案化以向下延伸穿過介層孔28並延伸穿過額外重新分佈層38、40之每一者，以便將額外重新分佈層38、40之每一者電連接至初始重新分佈層16。如圖5所示，對於未切割重新分佈層38(之介層孔28)，經由於一第一方向50上自初始重新分佈層16之前/頂表面36向外延伸，(另一)介層孔28係於與該第一方向50相反之一第二方向52上形成(即鑽孔、雷射消融)。即，未切割重新分佈層38中之介層孔28係以自頂至下之方式形成。相反，對於預切割重新分佈層40(之介層孔28)，經由於一第二方向52上自初始重新分佈層16之後/底表面44向外延伸，(另一)介層孔28係於第一方向50上鑽孔。即，預切割重新分佈層40中之介層孔28係以自底至上之方式形成。
如圖6所示，具一未經圖案化之預切割重新分佈層56及一未經圖案化之未切割重新分佈層58之形式的進一步重新分佈層56、58係增添至初始重新分佈層16並在該製造技術之一下一步驟中增添至重新分佈層38、40。一黏合層24係施加於預切割重新分佈層56及未切割重新分佈層58之每一者以提供一黏合材料。預切割重新分佈層56係施加/層壓至重新分佈層38上，從而於第一方向50上自初始重新分佈層16之前/頂表面36向外延伸。未切割重新分佈層58係施加/層壓至重新分佈層40上並施加/層壓至晶片26之後/底表面46上，從而於第二方向52上自初始重新分佈層16之後/底表面44向外延伸。在該製造處理/技術之一下一步驟中並如圖7所示，複數個介層孔28係形成於額外重新分佈層56、58之每一者中。金屬互連件34亦形成/圖案化以向下延伸穿過介層孔28並延伸穿過額外重新分佈層56、58之每一者，以便將額外重新分佈層56、58之每一者電連接至先前所施加之重新分佈層38、40且電連接至初始重新分佈層16。
現參照圖8，在本發明之一例示性實施例中，額外超薄晶片60、62係在ECBU處理之一下一步驟中予以增添。一頂晶片60及一底晶片62係分別經一黏合層24附接至額外重新分佈層64、66。如圖8所示，頂晶片60係施加於一表面68自身上之一未切割、未經圖案化之重新分佈層64上，並面向現存嵌入晶片總成70。可在黏合層24及重新分佈層64上佈置頂晶片60之後隨即執行一真空層壓及壓烘硬化處理以將晶片60固定至該處。一黏合層24係接著施加於頂晶片60之一底表面72及重新分佈層64之表面68以容許頂晶片/重新分佈層結構60、64在嵌入晶片總成70處之隨後佈置。
在頂晶片/重新分佈層結構60、64之製備及佈置之前、期間或之後，底晶片62係(經黏合層24)施加至一表面74自身上之未切割、未經圖案化之重新分佈層66，並背向嵌入晶片總成70。可在黏合層24及重新分佈層66上佈置之後底晶片62隨即執行一真空層壓及壓烘硬化處理以將晶片62固定至該處。在將底部晶片62固定至重新分佈層66之後，重新分佈層66經圖案化以形成於其中之複數個介層孔28及向下延伸穿過介層孔28至底部晶片62上之墊30的金屬互連件34。即，金屬互連件34向下延伸至墊30以形成對底晶片62之晶片墊30的一直接金屬及電連接。
一黏合層24係接著施加於重新分佈層66面向嵌入晶片總成70之一表面76，以容許底晶片/重新分佈層結構62、66在該嵌入晶片總成70處之隨後佈置。重新分佈層64、66之額外圖案化及進一步重新分佈層78之佈置係在如圖9所示之總成上加以執行。此額外圖案化中所包括的係重新分佈層64之一圖案化，其中金屬互連件34係圖案化/蝕刻以向下延伸穿過介層孔28，以便形成對頂晶片60之晶片墊30的一直接金屬及電連接。可認定任何數目之額外重新分佈層78係可隨後增添至總成70。因基於ECP 10之設計要求而決定，重新分佈層之額外圖案化及佈置容許在該總成中之進一步佈線。
現參照圖10，在ECBU處理之一下一步驟中，一焊接遮罩層80係施加於一最外重新分佈層82。該最外重新分佈層82上之焊接遮罩容許複數個輸入/輸出(I/O)互連84之連接。根據本發明之一實施例並如圖10所示，I/O互連件84係施加於一最頂重新分佈/層壓層82上之焊接遮罩以形成一I/O系統互連86。在一實施例中，I/O互連件84係形成為焊接至焊接遮罩之球狀物(即焊球)。然而亦可預期，可附接其他形式之I/O互連件84，諸如鍍層凸塊、柱凸塊、金凸塊、金屬充填聚合物凸塊或打線接合連接/墊，使得可在ECP 10與其欲附接之一母板(圖中未繪示)之間形成一可靠連接。
由複數個重新分佈層所提供之金屬互連件34之重新分佈係容許於ECP 10之一頂表面上形成增加數目之I/O互連件84。即，例如，焊接連接84可歸因於金屬互連件34之重新分佈而在ECP 10上更緻密地包裹。ECP 10上之焊接連接84係因此形成而具有相較於習知焊球減小之一節距及高度。舉例而言，焊接連接84可形成以具有一180微米之高度及80微米之節距。在一可撓性聚合物層壓/重新分佈層上以此一尺寸形成焊接連接84而減低ECP 10與其欲安裝之一母板(圖中未繪示)之間的連接應力，因此亦否定對一未填滿之環氧混合劑之需要，該混合劑係可在將ECP 10焊接至母板之後施加於焊接連接84、ECP 10與一母板之間(如先前技術中通常所執行)。
如圖10進一步所示並根據本發明之一實施例，表面安裝被動裝置88係附接至另一最外重新分佈層90(即最底重新分佈層)。該表面安裝裝置88可具電容器、電阻器或電感器之形式，該等裝置88例如係焊接至最外重新分佈層90上之金屬互連件34上。一散熱器92亦附接至最外重新分佈層90及底晶片62以耗散來自ECP 10之熱量。散熱器92係可例如由藉一導熱性黏合劑24而黏合至最外重新分佈層90及底晶片62之一後表面94的一單片或雙片銅板組成。或者，可認定額外重新分佈層係可就底晶片62而施加於最外重新分佈層90(即，一晶片開口形成於該等額外重新分佈層中以接納晶片62)，使得ECP 10具有一平整後/底表面，因此容許在該處之一額外I/O系統互連件之佈置/連接。
圖10中所示之所得ECP 10中因此包括以一堆疊式3D配置之複數個晶片26、60、62，其中每一晶片具有藉金屬互連件34而對I/O系統互連件86的一直接金屬及電連接。晶片26、60、62係以一垂直方向相對於彼此堆疊，以便在垂直方向上形成一堆疊式晶片配置。如上文所述應瞭解，其他電組件(電阻器、電容器、電感器等)可替代ECP 10中之晶片26、60、62，且以ECP 10中之一3D配置對此等電組件之堆疊被認為係處於本發明之範疇內。
現參照圖11，根據本發明之另一實施例，一ECP 96係顯示為具有彼此黏合並嵌入層壓重新分佈層102內之一第一晶片98及一第二晶片100。更明確言之，第一晶片98之一非主動表面104(即後表面)係黏合至第二晶片100之一非主動表面106。
如圖12所示，根據本發明之另一實施例，一ECP 106包括以一共同水平面配置/施加之一第一晶片108及一第二晶片110。根據圖12之實施例，第一晶片108及第二晶片110之每一者具有匹配一單一重新分佈層112厚度之一厚度，儘管亦可認定晶片108、110可具有等於具有匹配晶片108、110厚度之一總體厚度的多個(例如2個或3個)重新分佈層。第一晶片108及第二晶片110之每一者係單獨置於重新分佈層112中所形成之一晶片開口114內，以便以相同水平面加以配置。複數個介層孔28及向下延伸穿過介層孔28之金屬互連件34係在重新分佈層112中圖案化，使得金屬互連件延伸至第一晶片108及第二晶片110之每一者上之墊30。即，金屬互連件34向下延伸至墊30以形成對第一晶片108及第二晶片110之晶片墊30的一直接金屬及電連接。在相同平面(即重新分佈層112)上之第一晶片108及第二晶片110之並排嵌入容許ECP 106中之重新分佈層數量減小，因此助益於減小該ECP 106之總體厚度並減小相關產製成本。
根據本發明之額外實施例，可認定ECBU處理係可執行作為一單一成側增層，其中額外晶片及重新分佈層係以一方向自一初始重新分佈層級晶片加以增層。此外可認定，較圖10及圖12之ECP中之所示更多或更少之晶片可包括至ECP中。亦可預期進一步特徵，諸如ECP外表面與遍及該ECP之電力及接地面兩者上之I/O連接。
根據本發明之額外實施例，可進一步認定上文所述之ECP 10之諸實施例可組合倒裝晶片或打線接合晶片而使用。上文所述之3D堆疊式晶片配置之實施可與倒裝晶片或打線接合晶片加以組合，以改良在習知單獨倒裝晶片或打線接合晶片上之晶片封裝的效能、小型化及可靠性，以及倒裝晶片或打線接合晶片之堆疊能力。
因此，根據本發明之一實施例，一種嵌入晶片封裝包括於一垂直方向上結合在一起以形成一層壓堆疊之複數個重新分佈層，其中每一重新分佈層包括形成於其中之複數個介層孔。該嵌入晶片封裝亦包括嵌入於該層壓堆疊中並包括複數個晶片墊之一第一晶片；附接至該層壓堆疊並相對於該第一晶片而堆疊於垂直方向上之一第二晶片，該第二晶片包括複數個晶片墊；及定位於該層壓堆疊之一最外重新分佈層上之一輸入/輸出(I/O)系統。該嵌入晶片封裝進一步包括電耦合至該I/O系統且經組態以將該第一晶片及該第二晶片電連接至該I/O系統之複數個金屬互連件，其中該複數個金屬互連件之每一者係延伸穿過一各自介層孔以與一相鄰重新分佈層上之一金屬互連件及第一或第二晶片上之一晶片墊之一者形成一直接金屬連接。
根據本發明之另一實施例，一種形成一嵌入晶片封裝之方法包括提供一初始聚合物層壓層及固定至該初始聚合物層壓層之一第一晶片，該第一晶片之上具有數個晶片墊。該方法亦包括圖案化該初始聚合物層壓層以包括複數個介層孔及複數個金屬互連件，使得該複數個金屬互連件之一部分係向下延伸穿過各自介層孔並直接金屬連接至該第一晶片上之該等晶片墊；提供一額外晶片，並提供複數個額外聚合物層壓層，其中該複數個額外聚合物層壓層之一部分包括形成於其中用於第一晶片及額外晶片之一者之佈置的一晶片開口。該方法進一步包括將該額外晶片及該複數個額外聚合物層壓層之每一者選擇性耦合至初始聚合物層壓層，且在耦合該複數個額外聚合物層壓層之每一者之後，選擇性圖案化該額外聚合物層壓層以包括複數個介層孔及複數個金屬互連件，使得該複數個金屬互連件之每一者延伸穿過一各自介層孔並直接金屬連接至一相鄰聚合物層壓層上之一金屬互連件及額外晶片上之一晶片墊之一者。該方法亦包括將複數個輸入/輸出(I/O)連接電耦合至複數個額外聚合物層壓層之一最外聚合物層壓層上的金屬互連件，其中該等I/O連接係藉該複數個金屬互連件而電連接至第一晶片且電連接至額外晶片。
根據本發明之又一實施例，一種用於製造一晶圓級封裝之方法包括提供複數個晶片，該複數個晶片之每一者具有形成於其上之數個晶片墊；及提供複數個聚合物層壓層，其中該複數個聚合物層壓層之一部分包括形成於其中用於其中該複數個晶片之一者之佈置的一晶片開口。該方法亦包括使用該複數個晶片及該複數個聚合物層壓層來裝配一晶圓級封裝，其中裝配該晶圓級封裝包括將一第一晶片施加於一初始聚合物層壓層，並圖案化該初始聚合物層壓層上以包括複數個介層孔及複數個金屬互連件，其中該複數個金屬互連件之每一者係向下延伸穿過一各自介層孔以將該初始聚合物層壓層電耦合至第一晶片。裝配該晶圓級封裝亦包括以一堆疊式配置而將額外聚合物層壓層級額外晶片選擇性施加於該初始聚合物層壓層及該第一晶片，且在施加每一額外聚合物層壓層之後，圖案化該額外聚合物層壓層以形成複數個介層孔及向下延伸穿過該等介層孔之複數個金屬互連件，使得每一額外聚合物層壓層中之金屬互連件將該聚合物層壓層電耦合至一先前所施加之額外聚合物層壓層或一先前所施加之額外晶片。
雖然本發明已僅結合有限數目之實施例而予以詳儘描述，但應可輕易瞭解的是，本發明並非受限於此等所揭示之實施例。況且，本發明不僅可經修改以合併迄今為止仍未加以描述之任何數目之變動、變化、替代或等效配置，而且該等變動、變化、替代或等效配置係與本發明之精神及範疇相符。此外，雖然已描述本發明之多種實施例，但仍將瞭解，本發明之諸態樣可僅包括某些所述之實施例。相應言之，本發明不應被視為受限於先前所述，而僅受限於後附請求項之範疇。
10．．．嵌入晶片封裝
12．．．晶片/晶粒
14．．．重新分佈層
16．．．初始重新分佈層
18．．．框架
20．．．預圖案化區域
22．．．非圖案化區域
24．．．黏合層
26．．．晶片
28．．．介層孔
30．．．晶片墊
32．．．金屬層/材料
34．．．金屬互連件
36．．．初始重新分佈層之前/頂表面
38．．．未切割重新分佈層
40．．．預切割重新分佈層
42．．．晶片開口
44．．．初始重新分佈層之後/底表面
46．．．晶片後/底表面
48．．．預切割重新分佈層之後/底表面
50．．．第一方向
52．．．第二方向
56．．．未圖案化之預切割重新分佈層
58．．．未圖案化之未切割重新分佈層
60．．．額外晶片
62．．．額外晶片
64．．．重新分佈層
66．．．重新分佈層
68．．．重新分佈層表面
70．．．嵌入晶片縂成
72．．．晶片底表面
74．．．表面
76．．．表面
78．．．重新分佈層
80．．．焊接遮罩表面
82．．．最外重新分佈層
84．．．輸入/輸出(I/O)互連
86．．．I/O系統互連
88．．．表面安裝被動裝置
90．．．最外重新分佈層
92．．．散熱器
94．．．後表面
96．．．嵌入晶片安裝(ECP)
98．．．第一晶片
100．．．第二晶片
102．．．重新分佈層
104．．．非主動表面
106．．．非主動表面
108．．．第一晶片
110．．．第二晶片
112．．．單一重新分佈層
114．．．晶片開口
圖1係根據本發明之一實施例的複數個嵌入晶片封裝之一俯視圖；
圖2至圖10係根據本發明之一實施例之在一製造/增層處理之不同階段期間的一嵌入晶片封裝之示意性側截面圖；
圖11係根據本發明之另一實施例的一嵌入晶片封裝之一示意性側截面圖；及
圖12係根據本發明之另一實施例的一嵌入晶片封裝之一示意性側截面圖。
16．．．初始重新分佈層
24．．．黏合層
26．．．晶片
28．．．介層孔
34．．．金屬互連件
36．．．初始重新分佈層之前/頂表面
38．．．未切割重新分佈層
40．．．預切割重新分佈層
44．．．初始重新分佈層之後/底表面
50．．．第一方向
52．．．第二方向

Claims (10)

  1. 一種嵌入晶片封裝(10)，其包括：複數個聚合物層壓重新分佈層(14)，其等係於一垂直方向上結合在一起以形成一層壓堆疊，其中每一聚合物層壓重新分佈層(14)包含形成於其中之複數個介層孔(28)；一第一晶片(26)，其嵌入於該層壓堆疊中且包括複數個晶片墊(30)；一第二晶片(62)，其附接至該層壓堆疊且相對於該第一晶片(26)而堆疊於該垂直方向上，該第二晶片(62)包括複數個晶片墊(30)；一輸入/輸出(I/O)系統(86)，其係定位於該層壓堆疊之一最外重新分佈層(82)上；及複數個金屬互連件(34)，其等係電耦合至該I/O系統(86)且經組態以將該第一晶片及該第二晶片電連接至該I/O系統(86)，其中該複數個金屬互連件(34)之每一者延伸穿過一各自介層孔(28)且該複數個金屬互連件(34)之每一者直接經金屬化至一相鄰聚合物層壓重新分佈層(14)上之一金屬互連件(34)及該第一晶片(26)或該第二晶片(62)上之一晶片墊(30)之一者。
  2. 如請求項1之嵌入晶片封裝(10)，其進一步包括沈積於該複數個聚合物層壓重新分佈層(14)之每一者之間的一黏合層(24)。
  3. 如請求項1之嵌入晶片封裝(10)，其中該複數個金屬互連 件(34)之一部分延伸至該最外聚合物層壓重新分佈層(82)之一外表面上。
  4. 如請求項3之嵌入晶片封裝(10)，其中該最外重新分佈層(82)包括一最頂聚合物層壓重新分佈層及一最底重新分佈層之至少一者；及其中該I/O系統(86)係定位於該複數個金屬互連件(34)之該部分上。
  5. 如請求項1之嵌入晶片封裝(10)，其進一步包括附接至該層壓堆疊之另一最外聚合物層壓重新分佈層(90)上之該複數個金屬互連件(34)之一部分的一電容器、一電感器及一電阻器(88)之至少一者。
  6. 如請求項5之嵌入晶片封裝(10)，其進一步包括附接至該層壓堆疊之該另一最外聚合物層壓重新分佈層(90)的一散熱器(92)。
  7. 如請求項1之嵌入晶片封裝(10)，其中該複數個聚合物層壓重新分佈層(14)包括：一中央重新分佈層(16)，其具有面向一第一方向之一第一表面及面向與該第一方向相反之一第二方向的一第二表面；至少一第一額外重新分佈層(38)，其係黏合至該中央重新分佈層(16)之該第一表面且於該第一方向上向外延伸；至少一第二額外重新分佈層(40)，其係黏合至該中央重新分佈層(16)之該第二表面且於該第二方向上向外延 伸；其中黏合至該中央重新分佈層(16)之該第一表面的該至少一第一額外重新分佈層(38)之每一者包括複數個介層孔(28)及延伸穿過該等介層孔(28)且延伸至背向該中央重新分佈層(16)之該第一額外重新分佈層(38)之一表面上的複數個金屬互連件(34)；及其中黏合至該中央重新分佈層(16)之該第二表面的該至少一第二額外重新分佈層(40)之每一者包括複數個介層孔(28)及延伸穿過該等介層孔(28)且延伸至背向該中央重新分佈層(16)之該第二額外重新分佈層(40)之一表面上的複數個金屬互連件(34)。
  8. 如請求項1之嵌入晶片封裝(10)，其中該複數個聚合物層壓重新分佈層(14)之一部分包含形成於其中之一晶片開口(42)，該複數個聚合物層壓重新分佈層之該部分中之一各自聚合物層壓重新分佈層中之該晶片開口(42)經設定尺寸以接納該第一晶片(26)及該第二晶片(62)之一者於其中。
  9. 如請求項8之嵌入晶片封裝(10)，其中於其內形成有該晶片開口(42)之該等聚合物層壓重新分佈層(14)之每一者係具有大約等於定位於其晶片開口中之該晶片之一厚度的一厚度。
  10. 如請求項1之嵌入晶片封裝(10)，其中該第一晶片(98)之一非主動表面係黏合至該第二晶片(100)之一非主動表面。
TW099105354A 2009-03-06 2010-02-24 堆疊式晶粒嵌入晶片增層之系統及方法 TWI511263B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/399,083 US8008125B2 (en) 2009-03-06 2009-03-06 System and method for stacked die embedded chip build-up

Publications (2)

Publication Number Publication Date
TW201041117A TW201041117A (en) 2010-11-16
TWI511263B true TWI511263B (zh) 2015-12-01

Family

ID=42315448

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099105354A TWI511263B (zh) 2009-03-06 2010-02-24 堆疊式晶粒嵌入晶片增層之系統及方法

Country Status (6)

Country Link
US (1) US8008125B2 (zh)
EP (1) EP2228824A1 (zh)
JP (1) JP5639368B2 (zh)
KR (1) KR101690549B1 (zh)
CN (1) CN101877348B (zh)
TW (1) TWI511263B (zh)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
JP5578797B2 (ja) * 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置
US9225379B2 (en) 2009-12-18 2015-12-29 Intel Corporation Apparatus and method for embedding components in small-form-factor, system-on-packages
US8217272B2 (en) * 2009-12-18 2012-07-10 Intel Corporation Apparatus and method for embedding components in small-form-factor, system-on-packages
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8174108B2 (en) * 2010-03-24 2012-05-08 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Method for facilitating the stacking of integrated circuits having different areas and an integrated circuit package constructed by the method
US20120161319A1 (en) * 2010-12-23 2012-06-28 Stmicroelectronics Pte Ltd. Ball grid array method and structure
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
TWI462201B (zh) * 2011-03-04 2014-11-21 Adl Engineering Inc 半導體封裝結構及其製造方法
US8786080B2 (en) * 2011-03-11 2014-07-22 Altera Corporation Systems including an I/O stack and methods for fabricating such systems
US8841763B2 (en) * 2011-04-29 2014-09-23 Tessera, Inc. Three-dimensional system-in-a-package
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US20130040423A1 (en) * 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8431444B2 (en) 2011-08-16 2013-04-30 General Electric Company Epoxy encapsulating and lamination adhesive and method of making same
US20130070437A1 (en) * 2011-09-20 2013-03-21 Invensas Corp. Hybrid interposer
US20130154106A1 (en) * 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
CN103187312A (zh) * 2011-12-28 2013-07-03 中国科学院上海微***与信息技术研究所 圆片级封装结构中的重布线层的制备方法及形成的结构
US9548251B2 (en) * 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US9888568B2 (en) * 2012-02-08 2018-02-06 Crane Electronics, Inc. Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
US8587132B2 (en) 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US9275976B2 (en) 2012-02-24 2016-03-01 Broadcom Corporation System-in-package with integrated socket
US8749072B2 (en) 2012-02-24 2014-06-10 Broadcom Corporation Semiconductor package with integrated selectively conductive film interposer
US8928128B2 (en) 2012-02-27 2015-01-06 Broadcom Corporation Semiconductor package with integrated electromagnetic shielding
TWI517274B (zh) * 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
US8658473B2 (en) * 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
US9117813B2 (en) 2012-06-15 2015-08-25 General Electric Company Integrated circuit package and method of making same
US20140048951A1 (en) * 2012-08-14 2014-02-20 Bridge Semiconductor Corporation Semiconductor assembly with dual connecting channels between interposer and coreless substrate
US9867277B2 (en) 2012-10-18 2018-01-09 Infineon Technologies Austria Ag High performance vertical interconnection
US9202782B2 (en) * 2013-01-07 2015-12-01 Intel Corporation Embedded package in PCB build up
JP5427305B1 (ja) * 2013-02-19 2014-02-26 株式会社フジクラ 部品内蔵基板及びその製造方法並びに実装体
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
CN205093051U (zh) * 2013-05-14 2016-03-16 株式会社村田制作所 部件内置基板以及通信模块
US9807890B2 (en) * 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US9018040B2 (en) 2013-09-30 2015-04-28 International Business Machines Corporation Power distribution for 3D semiconductor package
DE102013114907A1 (de) * 2013-12-27 2015-07-02 Pac Tech-Packaging Technologies Gmbh Verfahren zur Herstellung eines Chipmoduls
US9165885B2 (en) * 2013-12-30 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Staggered via redistribution layer (RDL) for a package and a method for forming the same
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
US9653438B2 (en) 2014-08-21 2017-05-16 General Electric Company Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
CN206908962U (zh) * 2014-09-04 2018-01-19 株式会社村田制作所 部件内置基板
CN105514080B (zh) 2014-10-11 2018-12-04 意法半导体有限公司 具有再分布层和加强件的电子器件及相关方法
US20160155723A1 (en) * 2014-11-27 2016-06-02 Chengwei Wu Semiconductor package
US9230726B1 (en) 2015-02-20 2016-01-05 Crane Electronics, Inc. Transformer-based power converters with 3D printed microchannel heat sink
CN106158823B (zh) * 2015-04-10 2018-09-07 稳懋半导体股份有限公司 金属化穿透孔结构及其制造方法
DE102015106151B4 (de) * 2015-04-22 2019-07-11 Infineon Technologies Ag Leiterplatte mit eingebettetem Leistungshalbleiterchip
KR102609142B1 (ko) * 2015-06-08 2023-12-05 삼성전기주식회사 회로 기판 및 이를 포함하는 전자 기기
US9786618B2 (en) * 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
JP6313804B2 (ja) * 2016-04-12 2018-04-18 株式会社フジクラ 部品内蔵基板
CN105870024B (zh) * 2016-06-15 2018-07-27 通富微电子股份有限公司 ***级封装方法
CN105957844B (zh) * 2016-06-15 2018-07-27 通富微电子股份有限公司 封装结构
US10109617B2 (en) * 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
US11158595B2 (en) * 2017-07-07 2021-10-26 Texas Instruments Incorporated Embedded die package multichip module
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10276537B2 (en) * 2017-09-25 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10211141B1 (en) 2017-11-17 2019-02-19 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10276523B1 (en) 2017-11-17 2019-04-30 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US10580715B2 (en) * 2018-06-14 2020-03-03 Texas Instruments Incorporated Stress buffer layer in embedded package
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US10756058B2 (en) * 2018-08-29 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
CN111741601B (zh) * 2020-07-09 2021-07-30 复旦大学 一种通用的可配置的有源基板电路结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159767A (en) * 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP2002246745A (ja) * 2001-02-14 2002-08-30 Ibiden Co Ltd 三次元実装パッケージ及びその製造方法、三次元実装パッケージ製造用接着材
US20050047094A1 (en) * 2003-08-28 2005-03-03 Shih-Ping Hsu Heat sink structure with embedded electronic components for semiconductor package
US7282390B2 (en) * 2002-01-09 2007-10-16 Micron Technology, Inc. Stacked die-in-die BGA package with die having a recess

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
JP3051700B2 (ja) 1997-07-28 2000-06-12 京セラ株式会社 素子内蔵多層配線基板の製造方法
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
AU2001283257A1 (en) * 2000-08-16 2002-02-25 Intel Corporation Direct build-up layer on an encapsulated die package
JP4694007B2 (ja) 2001-02-14 2011-06-01 イビデン株式会社 三次元実装パッケージの製造方法
US20030116860A1 (en) * 2001-12-21 2003-06-26 Biju Chandran Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
JP2003234432A (ja) 2002-02-08 2003-08-22 Ibiden Co Ltd 半導体チップ実装回路基板および多層化回路基板
CN1463038A (zh) * 2002-05-31 2003-12-24 富士通株式会社 半导体器件及其制造方法
EP2866258B1 (en) 2002-05-31 2019-04-17 Socionext Inc. Semiconductor device and manufacturing method thereof
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2005317903A (ja) 2004-03-31 2005-11-10 Alps Electric Co Ltd 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法
US20050218491A1 (en) * 2004-03-31 2005-10-06 Alps Electric Co., Ltd. Circuit component module and method of manufacturing the same
DE102004041889B4 (de) * 2004-08-30 2006-06-29 Infineon Technologies Ag Halbleitervorrichtung mit gestapelten Halbleiterbauelementen und Verfahren zu deren Herstellung
JP2006165320A (ja) * 2004-12-08 2006-06-22 Matsushita Electric Ind Co Ltd 半導体積層モジュールとその製造方法
TWI261329B (en) * 2005-03-09 2006-09-01 Phoenix Prec Technology Corp Conductive bump structure of circuit board and method for fabricating the same
US7640655B2 (en) 2005-09-13 2010-01-05 Shinko Electric Industries Co., Ltd. Electronic component embedded board and its manufacturing method
JP4673207B2 (ja) * 2005-12-16 2011-04-20 イビデン株式会社 多層プリント配線板およびその製造方法
JP2008130824A (ja) * 2006-11-21 2008-06-05 Kyocera Chemical Corp ビルドアップ型多層プリント配線板用接着シート及びビルドアップ型多層プリント配線板
US20100103634A1 (en) * 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
US20080318413A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and interconnect component recovery process
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR100885924B1 (ko) * 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
US7919868B2 (en) * 2007-08-15 2011-04-05 Qimonda Ag Carrier substrate and integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159767A (en) * 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP2002246745A (ja) * 2001-02-14 2002-08-30 Ibiden Co Ltd 三次元実装パッケージ及びその製造方法、三次元実装パッケージ製造用接着材
US7282390B2 (en) * 2002-01-09 2007-10-16 Micron Technology, Inc. Stacked die-in-die BGA package with die having a recess
US20050047094A1 (en) * 2003-08-28 2005-03-03 Shih-Ping Hsu Heat sink structure with embedded electronic components for semiconductor package

Also Published As

Publication number Publication date
KR20100100684A (ko) 2010-09-15
CN101877348A (zh) 2010-11-03
JP2010212683A (ja) 2010-09-24
EP2228824A1 (en) 2010-09-15
CN101877348B (zh) 2013-12-11
JP5639368B2 (ja) 2014-12-10
US8008125B2 (en) 2011-08-30
TW201041117A (en) 2010-11-16
US20100224992A1 (en) 2010-09-09
KR101690549B1 (ko) 2016-12-28

Similar Documents

Publication Publication Date Title
TWI511263B (zh) 堆疊式晶粒嵌入晶片增層之系統及方法
US9236348B2 (en) Ultrathin buried die module and method of manufacturing thereof
US9985005B2 (en) Chip package-in-package
US8114708B2 (en) System and method for pre-patterned embedded chip build-up
US8236608B2 (en) Stacking package structure with chip embedded inside and die having through silicon via and method of the same
TWI408795B (zh) Semiconductor device and manufacturing method thereof
US7829987B2 (en) Carrier structure embedded with semiconductor chips and method for manufacturing the same
US7768119B2 (en) Carrier structure embedded with semiconductor chip
KR20190003403A (ko) 반도체 패키지 및 방법
JP2013243345A5 (zh)
JP5588620B2 (ja) ウェーハ・レベル・パッケージ及びその形成方法
TWI754839B (zh) 封裝結構及其形成方法
TWI536526B (zh) 用於一積體電路封裝之電氣互連及其製造方法
TW201110309A (en) Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US9299661B2 (en) Integrated circuit package and method of making same
JP2001168269A (ja) 半導体素子の実装構造および積層型回路モジュールならびに半導体素子の実装構造の製造方法
JP5853759B2 (ja) 半導体ベアチップ、半導体ベアチップ接合体、３次元積層半導体装置及びその製造方法
JP4528018B2 (ja) 半導体装置及びその製造方法