JP2010212683A - スタック式ダイ埋め込み型チップビルドアップのためのシステム及び方法 - Google Patents
スタック式ダイ埋め込み型チップビルドアップのためのシステム及び方法 Download PDFInfo
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- JP2010212683A JP2010212683A JP2010044835A JP2010044835A JP2010212683A JP 2010212683 A JP2010212683 A JP 2010212683A JP 2010044835 A JP2010044835 A JP 2010044835A JP 2010044835 A JP2010044835 A JP 2010044835A JP 2010212683 A JP2010212683 A JP 2010212683A
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Abstract
【解決手段】埋め込み型チップパッケージ(ECP)10の各々のラミネーションスタックがビア28をその内部に有する複数の再分配層14を含む。ECP10はラミネーションスタック内に埋め込まれた複数のチップパッド30と、該ラミネーションスタックに取り付けられ、第1のチップ26を基準として垂直方向に積み重ねられている、各々が複数のチップパッド30を有する第2のチップ62と、ラミネーションスタックの最外側再分配層82上に位置決めされた入力/出力(I/O)システム86と、第1及び第2のチップをI/Oシステムに接続し、隣接する再分配層14上の金属相互接続34あるいは第1または第2のチップ上のチップパッド30とで直接の金属接続を形成するビア28を通過して延びる複数の金属相互接続34を含む。
【選択図】図5
Description
12 チップ/ダイ
14 再分配層
16 当初再分配層
18 フレーム
20 事前パターン形成エリア
22 パターン未形成エリア
24 接着剤層
26 チップ
28 ビア
30 チップパッド
32 金属層/材料
34 金属相互接続
36 当初再分配層の前面/上面
38 未切断の再分配層
40 事前切断の再分配層
42 チップ開口部
44 当初再分配層の背面/底面
46 チップ背面/底面
48 事前切断再分配層の背面/底面
50 第1の方向
52 第2の方向
56 パターン未形成の事前切断再分配層
58 パターン未形成の未切断再分配層
60 追加のチップ
62 追加のチップ
64 再分配層
66 再分配層
68 再分配層表面
70 埋め込み型チップアセンブリ
72 チップ底面
74 表面
76 表面
78 再分配層
80 はんだマスク層
82 最外側再分配層
84 入力/出力(I/O)相互接続
86 I/Oシステム相互接続
88 表面装着受動型デバイス
90 最外側再分配層
92 ヒートスプレッダ
94 背面
96 埋め込み型チップパッケージ(ECP)
98 第1のチップ
100 第2のチップ
102 再分配層
104 非作用面
106 非作用面
108 第1のチップ
110 第2のチップ
112 単一再分配層
114 チップ開口部
Claims (10)
- ラミネーションスタックを形成するように垂直方向に互いに接合させている、その各々が複数のビア(28)をその内部に形成させて含む複数の再分配層(14)と、
前記ラミネーションスタック内に埋め込まれた複数のチップパッド(30)を備えている第1のチップ(26)と、
前記ラミネーションスタックに取り付けられると共に第1のチップ(26)を基準として垂直方向に積み重ねられている、複数のチップパッド(30)を備えた第2のチップ(62)と、
前記ラミネーションスタックの最外側再分配層(82)上に位置決めされた入力/出力(I/O)システム(86)と、
前記I/Oシステム(86)に電気的に結合されると共に前記第1のチップ及び第2のチップを該I/Oシステム(86)に電気的に接続するように構成された複数の金属相互接続(34)であって、該複数の金属相互接続(34)の各々は隣接する再分配層(14)上の金属相互接続(34)と第1のチップ(26)または第2のチップ(62)上のチップパッド(30)のうちの一方とで直接の金属接続を形成するように対応するビア(28)を通過して延びている複数の金属相互接続(34)と、
を備える埋め込み型チップパッケージ(10)。 - 前記複数の再分配層(14)のそれぞれの間に付着させた接着剤層(24)をさらに備える請求項1に記載の埋め込みチップパッケージ(10)。
- 前記複数の金属相互接続(34)の一部分は最外側再分配層(82)の外側表面上まで延びている、請求項1に記載の埋め込みチップパッケージ(10)。
- 前記最外側再分配層(82)は最上部再分配層と最底部再分配層のうちの少なくとも一方を備えており、かつ前記I/Oシステム(86)は複数の金属相互接続(34)の前記部分上に位置決めされている、請求項3に記載の埋め込みチップパッケージ(10)。
- 前記ラミネーションスタックの別の最外側再分配層(90)上で前記複数の金属相互接続(34)の一部分に取り付けられたコンデンサ、インダクタ及び抵抗器(88)のうちの少なくとも1つをさらに備える請求項1に記載の埋め込みチップパッケージ(10)。
- 前記ラミネーションスタックの前記別の最外側再分配層(90)に取り付けられたヒートスプレッダ(92)をさらに備える請求項5に記載の埋め込みチップパッケージ(10)。
- 前記複数の再分配層(14)は、
第1の方向を向いた第1の表面と該第1の方向と反対の第2の方向を向いた第2の表面とを有する中央再分配層(16)と、
前記中央再分配層(16)の第1の表面に接着されると共に第1の方向に延び出している少なくとも1つの第1の追加的な再分配層(38)と、
前記中央再分配層(16)の第2の表面に接着されると共に第2の方向に延び出している少なくとも1つの第2の追加的な再分配層(40)と、を備えており、
中央再分配層(16)の第1の表面に接着された前記少なくとも1つの第1の追加的な再分配層(38)の各々は複数のビア(28)と該ビア(28)を通過すると共に中央再分配層(16)の反対方向を向いた第1の追加的な再分配層(38)の表面上まで延びている複数の金属相互接続(34)を備えており、
中央再分配層(16)の第2の表面に接着された前記少なくとも1つの第2の追加的な再分配層(40)の各々は複数のビア(28)と該ビア(28)を通過すると共に中央再分配層(16)の反対方向を向いた第2の追加的な再分配層(40)の表面上まで延びている複数の金属相互接続(34)を備えている、請求項1に記載の埋め込みチップパッケージ(10)。 - 前記複数の再分配層(14)の一部分はその内部に形成されたチップ開口部(42)を含んでおり、複数の再分配層の該部分の対応する再分配層内のチップ開口部(42)はその内部に第1のチップ(26)と第2のチップ(62)のうちの一方を受け容れるようなサイズとなっている、請求項1に記載の埋め込みチップパッケージ(10)。
- チップ開口部(42)をその内部に形成させて有する再分配層(14)の各々は、そのチップ開口部内に位置決めされるチップの厚さと概ね等しい厚さを有している、請求項8に記載の埋め込みチップパッケージ(10)。
- 前記第1のチップ(98)の非作用面は第2のチップ(100)の非作用面に接着されている、請求項1に記載の埋め込みチップパッケージ(10)。
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