TWI509809B - 帶有自對準有源接觸的基於高密度溝槽的功率ｍｏｓｆｅｔ及其制備方法 - Google Patents

帶有自對準有源接觸的基於高密度溝槽的功率ｍｏｓｆｅｔ及其制備方法 Download PDF

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TWI509809B
TWI509809B TW102145738A TW102145738A TWI509809B TW I509809 B TWI509809 B TW I509809B TW 102145738 A TW102145738 A TW 102145738A TW 102145738 A TW102145738 A TW 102145738A TW I509809 B TWI509809 B TW I509809B
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Taiwan
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insulating
layer
gate
trench
insulating layer
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TW102145738A
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TW201427022A (zh
Inventor
Yeeheng Lee
Hong Chang
Jongoh Kim
Sik Lui
Hamza Yilmaz
Madhur Bobde
Daniel Calafut
John Chen
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Alpha & Omega Semiconductor
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Description

帶有自對準有源接觸的基於高密度溝槽的功率MOSFET及其制備方法
本發明涉及金屬氧化物半導體場效應晶體管(MOSFET)，更確切地說是基於高密度溝槽的功率MOSFET。
低壓功率MOSFET通常用於負載開關器件。在負載開關器件中，要求降低器件的導通電阻(Rds )。確切地說，應該是器件的RdsA 最小，其中RdsA 就是器件的導通電阻與器件的有源區面積的乘積。另外，低壓功率MOSFET常用於高頻直流-直流器件。在這些應用中，通常要求器件的開關速度達到最大。優化開關速度最關鍵的三個因素為：1)Rds ×Qg ；2)Rds ×Qoss ；以及3)Qgd /Qgs 之比。首先，Rds 和閘極電荷(Qg )的乘積可測試器件傳導和開關的共同損耗。Qg 為閘汲電荷(Qgd )和閘源電荷(Qgs )之和。在第二個參數中，輸出電荷Qoss用於測量當器件接通或斷開時，需要充電和放電的電容。最後，使Qgd /Qgs 的比值最小，當器件斷開時，可以減少由很大的dV/dt導致器件接通的可能性。
如圖4A所示，設計基於溝槽的MOSFET的目的之一是降低器件的RdsA 。基於溝槽的MOSFET可以除去平面型MOSFET中原有的JFET結構。通過除去JFET，可以降低晶胞間距。然而，基本的基於溝槽的MOSFET在本體區中不具備任何電荷平衡，從而增大了RdsA 。而且，閘極氧化物比較薄，在溝槽下方產生很高的電場，致使擊穿電壓較低。為了承載電壓，漂流區中的摻雜濃度必須很低，從而對於帶有較薄閘極氧化物的結構來說， 增大了RdsA 。另外，由於很難進一步減小閘極氧化物的厚度，所以隨著晶胞間距持續減小，基於溝槽的MOSFET並非是一個理想的選擇。
人們一直利用各種方法，試圖解決上述問題。圖4B表示Baliga在美國專利號5,998,833中提出的第一種示例一一屏蔽閘MOSFET。利用一個連接到源極電勢的基於溝槽的屏蔽電極，代替較大的閘極電極，降低了MOSFET的閘汲電容(Cgd)，在高頻操作時，通過減少閘極放電和充電的電量，提高了開關速度。然而，由於源極電勢通過屏蔽電極電容耦合到汲極，因此Baliga提出的MOSFET器件具有很高的輸出電容。而且，為了承載閉鎖電壓，需要很厚的氧化物。最後，為了在同一個溝槽中，制備兩個電氣性分隔的多晶矽電極，需要進行複雜的工藝。當器件的間距縮至很深的亞微米級別時，制備的複雜性將進一步增大。
最後，Temple在美國專利申請號4,941,026中提出的圖4C所示的MOSFET設計圖，具有有利於優化器件開關特性的某些特點。Temple提出的器件利用二階閘極氧化物，在閘極頂部附近具有薄氧化層，在閘極底部具有厚氧化層，以便制成低通道電阻和低漂流電阻的器件。閘極頂部的薄氧化物可以在閘極和本體區之間提供良好的耦合，在薄氧化物附近的溝槽中，產生很強的反轉以及低導通電阻。閘極底部較厚的閘極氧化物產生電荷平衡效果，使得漂流區的摻雜濃度增高。漂流區中較高的摻雜濃度降低了它的電阻。
然而，由於圖4C所示器件對本體接觸區的失準誤差高度敏感，並不能輕鬆地減小它的尺寸。例如，如果器件的間距尺寸降至深亞微米級別(例如0.5-0.6μm)，那麼接觸掩膜的失準就相當於閘極的失準，可能會對器件的性能造成很大的影響。為了形成到本體區良好的歐姆接觸，在使用接觸掩膜之後，注入歐姆接觸區，其中歐姆接觸區用導電類型與本體區相同的摻雜物重摻雜。如果接觸掩膜中的開口對準得太靠近閘極，也就是說不是準確地位於矽臺面結構的中心，那麼使用摻雜層注入，形成同本體產生歐姆接觸的接觸區之後，注入的重摻雜物會終止在通道中。如果 重摻雜歐姆接觸區處於通道中，那麼器件的閾值電壓和導通電阻將受到影響。而且，如果接觸掩膜對準得離閘極過遠，那麼雙極結型晶體管(BJT)的接通將成為一個問題。因為如果接觸區離溝槽較遠的話，本體區的長度及其電阻都會增大。隨著本體區電阻的增大，施加在本體區的電壓也會增大。本體區上較大的壓降將更容易地接通寄生BJT，對器件造成損壞。
因此，為了制備深亞微米級間距的功率MOSFET器件，優化後作為負載開關和高頻直流-直流器件，必須使用將接觸自對準到閘極的器件和方法，以避免上述不良效果。
正是在這一前提下，提出了本發明的實施例。
本發明提供了一種MOSFET器件的制備方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中半導體襯底包括一個輕摻雜的漂流區，形成在襯底頂部，其中硬掩膜包括第一、第二和第三絕緣層，其中第二絕緣層夾在第一和第三絕緣層之間，其中第三絕緣層位於第二絕緣層和半導體襯底頂面之間，其中第二絕緣層可以抵抗刻蝕第一和第三絕緣層材料的刻蝕工藝，其中第一和第三絕緣層可以抵抗刻蝕第二絕緣層材料的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在絕緣閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平面處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，向下刻蝕硬掩膜的第一絕緣層到硬掩膜第二絕緣層的水平面處，利用第二次刻蝕工藝，除去硬掩膜的第二絕 緣層，保留與溝槽對準的絕緣閘極蓋突出至硬掩膜第三絕緣層的水平面上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)在本體層頂部，制備一個第一導電類型的源極層；i)在絕緣閘極蓋和硬掩膜第三絕緣層的裸露部分上方，制備一個第一絕緣墊片層，並且各向異性地刻蝕第一絕緣墊片層，保留沿著絕緣閘極蓋側壁的那部分第一絕緣墊片層，作為第一絕緣墊片；j)在硬掩膜第三絕緣層的裸露部分、絕緣閘極蓋和第一絕緣墊片上方，制備一個第二絕緣墊片層，各向異性地刻蝕第二絕緣墊片層，保留沿著第一絕緣墊片裸露側壁的那部分第二絕緣墊片層，作為第二絕緣墊片；並且k)利用第一和第二絕緣墊片作為自對準掩膜，在半導體襯底中制備用於源極接觸的接觸開口。
上述的方法，其中制備多個溝槽包括穿過硬掩膜中的開口刻蝕襯底，形成溝槽頂部；沿溝槽頂部的側壁和底面生長一個犧牲絕緣層，並且沿側壁在犧牲絕緣層上制備墊片；將所述的墊片作為掩膜，通過刻蝕沉積在溝槽頂部底面上的犧牲絕緣層，以及溝槽頂部下方的襯底，形成溝槽底部；沿溝槽底部的側壁和底面，生長底部絕緣層；除去墊片和犧牲絕緣層；並且沿溝槽頂部的側壁，生長頂部絕緣層。
上述的方法，其中硬掩膜為氧化物-氮化物-氧化物硬掩膜，其中第一和第三絕緣層由氧化物材料制成，第二絕緣層由氮化物材料制成。
上述的方法，其中通過CVD工藝，將第一絕緣墊片層沉積在表面上方，其中第一絕緣墊片層包括由四乙基原矽酸鹽(TEOS)氣制成的氧化物。
上述的方法，其中用於制備第一絕緣墊片層的材料與絕緣閘極蓋的制備材料相同。
上述的方法，其中各向異性刻蝕第一絕緣墊片層還包括通過對刻蝕掉的那部分第一絕緣墊片層下方的那部分硬掩膜第三絕緣層的刻蝕，使得半導體襯底的一部分頂面裸露出來。
上述的方法，還包括：在裸露的那部分半導體襯底的頂面上方，生長一個襯墊絕緣層。
上述的方法，其中第一絕緣墊片和第二絕緣墊片由相同的材料制成。
上述的方法，其中第一絕緣墊片層由氧化物制成，第二絕緣墊片層由氮化物制成。
上述的方法，其中通過CVD工藝，在表面上方沉積第二絕緣墊片層。
上述的方法，其中第二絕緣墊片層的厚度約為300Å。
上述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極拾取溝槽中沉積導電材料，以制備閘極拾取電極。
上述的方法，還包括：在氮化層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜之前，在硬掩膜第二絕緣層的上方，制備一個靜電放電(ESD)保護電極。
上述的方法，還包括除去硬掩膜的第二絕緣層之前，氧化ESD保護電極的表面。
上述的方法，還包括：除去硬掩膜的第二絕緣層之後，制備一個或多個本體鉗位(BCL)結構，其中BCL結構是通過兩次或多次摻雜物注入工藝制成的。
上述的方法，還包括，制備帶有BCL結構的肖特基接觸金屬。
本發明還提供了一種MOSFET器件，包括： 一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜漂流區，位於襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反；由半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都包括一個用閘極氧化物絕緣的閘極電極，其中閘極氧化物的頂部厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個或多個第一導電類型的源極區，形成在閘極電極附近的本體區頂部；形成在每個閘極電極上方的絕緣閘極蓋，其中第一絕緣墊片形成在絕緣閘極蓋的側壁上，第二絕緣墊片形成在第一絕緣墊片的裸露側壁上；一個在本體區頂面上方的絕緣層；一個形成在絕緣層上方的導電源極電極層；將源極電極層連接到一個或多個源極區上的一個或多個電連接結構，其中通過第一和第二絕緣墊片，將一個或多個電連接結構與絕緣閘極蓋分隔開。
上述的MOSFET器件，其中第一絕緣墊片和第二絕緣墊片都是由氮化物材料制成的。
上述的MOSFET器件，其中第二絕緣墊片可以抵抗第一次刻蝕工藝，第一次刻蝕工藝用於選擇性刻蝕制備第一絕緣墊片的材料，其中第一絕緣墊片可以抵抗第二次刻蝕工藝，第二次刻蝕工藝用於選擇性刻蝕制備第二絕緣墊片的材料。
上述的MOSFET器件，其中第一絕緣墊片為氧化物材料，第二絕緣墊片為氮化物材料。
上述的MOSFET器件，還包括：一個或多個靜電放電(ESD)保護ESD結構，形成在絕緣層上方。
上述的MOSFET器件，還包括一個或多個閘極拾取結構，形成在半導體襯底中。
上述的MOSFET器件，還包括一個本體鉗位(BCL)結構。
118‧‧‧閘極氧化物
107‧‧‧外延層
100‧‧‧器件
191‧‧‧積累區
101‧‧‧襯底
102‧‧‧汲極區
102’‧‧‧汲極電極
103‧‧‧本體層
104‧‧‧源極區
195‧‧‧ESD結構
171‧‧‧頂部
172‧‧‧底部
109‧‧‧閘極電極
108‧‧‧絕緣閘極蓋
117‧‧‧源極金屬
157‧‧‧絕緣層
111‧‧‧第一絕緣墊片
105‧‧‧絕緣層
177‧‧‧連接結構
165‧‧‧勢壘金屬
110‧‧‧第二絕緣墊片
156‧‧‧氮化層
123‧‧‧ESD電極
114‧‧‧ESD絕緣蓋
106‧‧‧第二氮化層
116‧‧‧外部絕緣物
128‧‧‧ESD金屬
112‧‧‧垂直連接結構
126‧‧‧閘極拾取區
127‧‧‧肖特基區
122‧‧‧閘極拾取電極
124‧‧‧閘極金屬
120‧‧‧閘極接觸結構
121‧‧‧BCL區
129‧‧‧金屬接觸區
125‧‧‧肖特基接觸金屬
119‧‧‧閘極滑道
300‧‧‧器件結構
326‧‧‧閘極拾取區
327‧‧‧肖特基區
301‧‧‧襯底
307‧‧‧漂流區
302‧‧‧汲極接觸區
357‧‧‧氧化層
356‧‧‧氮化層
355‧‧‧氧化層
348、349‧‧‧溝槽
357、356、355‧‧‧ONO硬掩膜層
371‧‧‧頂部
318‧‧‧襯墊氧化物
318a ‧‧‧襯墊氧化物
346‧‧‧氮化層
372‧‧‧溝槽底部
318b ‧‧‧襯裏氧化物
318c ‧‧‧閘極氧化物
309‧‧‧閘極電極
322‧‧‧閘極拾取電極
308‧‧‧絕緣蓋
395‧‧‧ESD結構
323‧‧‧ESD電極
314‧‧‧ESD絕緣蓋
303‧‧‧本體區
304‧‧‧源極區
321‧‧‧BCL區
311’‧‧‧犧牲絕緣層
311‧‧‧第一絕緣墊片
305‧‧‧襯墊氧化物
306‧‧‧氮化層
316‧‧‧BPSG層
361‧‧‧光致抗蝕劑層
310‧‧‧第二絕緣墊片材料
347‧‧‧接觸溝槽
365‧‧‧勢壘金屬
377‧‧‧連接結構
312‧‧‧ESD連接結構
320‧‧‧閘極連接結構
329‧‧‧鎢
328‧‧‧ESD金屬
317‧‧‧源極金屬
324‧‧‧閘極金屬
325‧‧‧肖特基接觸金屬
圖1A表示依據本發明的一個方面，器件有源區的剖面圖。
圖1B表示依據本發明的一個方面，閘極拾取區和肖特基區的剖面圖。
圖1C表示基於圖1A的實施例，但源極連接結構不是直接穿過ONO中最下方的一層絕緣層而是穿過襯底上方一個重新生長的氧化絕緣層。
圖2表示依據本發明的一個方面，器件布局的俯視圖。
圖3A-3O表示依據本發明的一個方面，制備有源區、閘極拾取區和肖特基區的工藝流程的剖面圖。
圖4A-4C表示原有技術的基於溝槽的功率MOSFET的剖面圖。
圖5A-5C表示依據本發明的各個方面，用於解釋MOSFET器件電學性能的圖表及圖形。
盡管為了解釋說明，以下詳細說明包含了許多具體細節，但是本領域的技術人員應明確以下細節的各種變化和修正都屬於本發明的範圍。因此，提出以下本發明的典型實施例，並沒有使所聲明的方面損失任何普遍性，也沒有提出任何局限。在下文中，N型器件用於解釋說明。利用相同的工藝，相反的導電類型，就可以制備P型器件。
依據本發明的各個方面，可以通過自對準的源極和本體接觸，制備基於高密度溝槽的功率MOSFET。源極/本體接觸與第一絕緣墊片、第二絕緣墊片自對準。作為示例，第一墊片可以抵抗刻蝕工藝，刻蝕工藝將選擇性地除去制備第二墊片的材料，或還可選擇制備第一墊片的材料與第二墊片的材料相同。作為示例，可以用氮化物材料制備墊片。另外，有源器件具有二階閘極氧化物，其中閘極氧化物的底部厚度為T2 ，閘極氧化物的頂部厚度為T1 ，T2 大於T1 。二階閘極氧化物與自對準源極/本體接觸相結合，用於制備尺寸可大幅度縮減的器件，有源器件間距在深亞微米級別(例如0.5-0.6微米)。
二階閘極氧化物使得閘極氧化物118的底部承載絕大部分的電壓，從而減少外延層107必須承載的電壓。圖5A表示有源器件的剖面圖，顯示出電場強度，其中陰影越暗表示電場強度越大。如圖中沿溝槽底部的深色陰影所示，閘極氧化物118的底部承載了電場的絕大部分。圖5B表示器件100閉鎖的電壓與襯底中深度的關系圖。器件100在0.5微米左右的深度上開始閉鎖電壓。該深度與閘極氧化物118的底部開始厚度為T2 處的深度是一致的。在溝槽底部和氧化物118附近(約1.0微米)，器件總共閉鎖了18V左右，大幅減少了外延層107的電壓閉鎖負擔。因此，可以增大外延漂流層107的摻雜濃度，以降低器件的RdsA 。外延層107摻雜濃度的增大，以及較小的晶胞間距導致較低的通道電阻，使得當該器件承載與圖4A所示相同的電壓時，與原有技術基於溝槽的MOSFET相比，RdsA 下降約90%或更多，當該器件承載與圖4B所示相同的電壓時，與原有技術的***閘極MOSFET相比，RdsA 下降約37%或更多。
器件的RdsA 會因積累區191的位置進一步降低。如圖5C所示，當閘極接通時，一個很窄的積累區191形成在溝槽側壁附近的外延層107頂部。作為示例，積累區191的寬度約為300-400Å。沿積累區的電荷載流子濃度降低了外延層107頂部的電阻。此外，由於積累區191很薄，只要晶胞間距大於積累區191的寬度，那麼減小晶胞間距就不會影響電阻。參見圖4B，上述***閘極MOSFET器件並不具備這種特性。在***閘極MOSFET器件中，溝槽底部的導體保持在源極電勢，防止沿側壁附近的狹窄路徑形成積累區。因此，將***閘極MOSFET的間距縮減至深亞微米級別並不現實。
圖1A表示依據本發明的各個方面，器件結構100的有源區剖面圖。器件結構100位於半導體襯底101上。形成在襯底101上的多個器件結構構成MOSFET器件，器件結構100就是這多個器件結構中的一個。此外，如同半導體制備中常見的那樣，多個這樣的器件可以形成在同一個襯底上。襯底101可以適當摻雜為N-型或P-型襯底。作為示例，但不作為局限，半導體襯底101可以是N-型矽襯底。半導體襯底具有一個重摻雜的N+ 汲極區102。作為示例，汲極區102的摻雜濃度約為1019 cm-3 或更大。汲極 區102電連接到汲極電極102’，汲極電極102’形成在半導體襯底的底面上。汲極區102上面可以是一個輕摻雜的N- 漂流區107或稱漂移區。作為示例，漂流區107的摻雜濃度約在1015 cm-3 和1017 cm-3 之間。在第一導電類型的半導體襯底101頂部，制備一個第二導電類型的適當摻雜的本體層103，第二導電類型與半導體襯底101的第一導電類型相反。第一導電類型的源極區104形成在本體層103的頂部。作為示例，以及本發明中其餘部分所使用的那樣，半導體襯底101可以是一個N-型半導體，本體區103可以是P-型，源極區104可以是N-型。
依據本發明的各個方面，器件結構100的有源區包括多個基於溝槽的MOSFET。本發明的某些方面還可選擇包括一個或多個靜電放電(ESD)保護可選件的ESD結構195。通過制備穿過P-本體區103延伸到半導體襯底101中的溝槽，制備基於溝槽的功率MOSFET。每個溝槽都有一個頂部171和底部172。電介質材料118內襯溝槽壁。電介質材料118在溝槽底部172的厚度為T2 ，電介質材料118在溝槽頂部171的厚度為T1 。依據本發明的各個方面，厚度T1 小於厚度T2 。作為示例，電介質材料118可以是氧化物。用適當的材料填充溝槽的剩餘部分，構成一個閘極電極109。作為示例，閘極電極109可以用多晶矽制備。通過設置在溝槽上方的絕緣閘極蓋108，閘極電極109與源極金屬117電絕緣。絕緣層157還可以形成在源極區104上方。第一絕緣墊片111可以沿絕緣閘極蓋108的每個垂直邊緣設置。作為示例，但不作為局限，第一絕緣墊片111的材料與絕緣閘極蓋108相同。作為示例，但不作為局限，絕緣閘極蓋108、絕緣層157以及第一絕緣墊片111可以是氧化物。
雖然圖1A沒有表示出來，閘極電極109可以連接到閘極墊，並且保持在閘極電勢。源極區104電連接到源極金屬117。雖然圖1A沒有表示出來，作為示例，但不作為局限，利用穿過絕緣層105延伸的垂直連接結構177形成源極連接結構，如圖1C所示。作為示例，但不作為局限，使用鎢等導電材料制備垂直連接結構177。本發明的另外一些方面還包括內襯於設置有該垂直連接結構177的溝槽或接觸孔的側壁或底部的勢壘金屬165。勢壘材料有利於防止不必要的擴散。作為示例，但不作為局限，勢壘 金屬165的材料可以是鈦或氮化鈦。
圖1C與圖1A的區別在於，在圖1A中源極區104上方的絕緣層157被保留而未被刻蝕，連接結構177穿過絕緣層157並延伸至源極區104下方的本體區103中，但在圖1C中，絕緣層157除了位於ESD結構195下方和位於每個第一絕緣墊片111下方的部分被保留之外，其他的部分都在後續的步驟(例如圖3J)中被刻蝕掉，並且因絕緣層157被刻蝕掉而裸露的襯底表面區域又重新生長了另一絕緣層105，則以自對準方式所制備的連接結構177不再穿過原先的絕緣層157，而是穿過有源區閘極溝槽附近的另一絕緣層105來接觸本體區103和源極區104。
另外，第二絕緣墊片110可以將垂直連接結構177與第一絕緣墊片111隔開。作為示例，但不作為局限，第一絕緣墊片111可以由抵抗蝕刻劑的材料制成，蝕刻劑選擇性地除去制成第二絕緣墊片110的材料。作為示例，第一絕緣墊片111可以是氧化物，第二絕緣墊片110可以是氮化物。氧化物能夠抵抗熱磷酸，而氮化物將通過熱磷酸刻蝕選擇性地除去。另外，第一和第二絕緣墊片110、111可以由相同的絕緣材料(例如氮化物)制成。第一和第二絕緣墊片111、110使得垂直連接結構177自對準。使用器件100上的現有結構，代替接觸掩膜，以制備源極接觸的垂直連接結構177，使得失準可能造成的誤差降至最低。
ESD保護可選件ESD結構195可以形成在絕緣層157上方。氮化層156沉積在絕緣層157的頂面上。在氮化層156上方，制備ESD電極123。作為示例，但不作為局限，可以用多晶矽制備ESD電極123。ESD電極123除了底面之外，其他的表面都由ESD絕緣蓋114覆蓋屏蔽。作為示例，ESD絕緣蓋114可以是氧化物。第一絕緣墊片111還可以沿ESD絕緣蓋114的邊緣以及氮化層156的邊緣構成。第二氮化層106形成在第一絕緣墊片111周圍和ESD絕緣蓋114的頂面上方。外部絕緣物116形成在第二氮化層106附近例如其上方。作為示例，但不作為局限，外部絕緣物116可以是含有硼酸的矽玻璃(BPSG)。ESD電極123電連接到ESD金屬128。作為示例，但不作為局限，利用穿過外部絕緣物116、第二氮化層106以及ESD絕緣蓋114延伸的垂直連接結構112，制備ESD連接結構。作為示例， 但不作為局限，可以用鎢等導電材料制備垂直連接結構112。依據本發明的一些方面，可以用鈦或氮化鈦等勢壘金屬165內襯設置有該垂直連接結構112的溝槽或接觸孔的側壁和底部。
依據本發明的一些方面，有源區可以選擇與相伴隨的非有源區一起制備。圖1B表示伴隨器件結構100的非有源區剖面圖。虛線左側的區域是閘極拾取區126，虛線右側的區域是肖特基區127。閘極拾取區126和肖特基區127都形成在半導體襯底101上。然而，圖1B的半導體襯底101缺少本體區103和源極區104，它們位於有源區中。
利用穿過半導體襯底101頂部延伸的溝槽，制備閘極拾取結構。電介質材料118內襯溝槽壁。電介質材料118在溝槽頂部的厚度為T1 ，在溝槽底部的厚度為T2 。厚度T1 和T2 與有源器件溝槽基本類似。用適當的材料填充溝槽的剩餘部分，制成閘極拾取電極122。作為示例，但不作為局限，用多晶矽制備閘極拾取電極122。絕緣閘極蓋108設置在溝槽上方。絕緣層157也可以設置在半導體襯底101的頂面上方。第一絕緣墊片111沿絕緣閘極蓋108的每個垂直邊緣形成。作為示例，但不作為局限，第一絕緣墊片111的材料與絕緣閘極蓋108相同。作為示例，但不作為局限，絕緣閘極蓋108、絕緣層157和第一絕緣墊片111都可以是氧化物。氮化層106形成在絕緣閘極蓋108頂面上方，沿第一絕緣墊片111的頂面，以及沿第一墊片111的裸露側面。外部絕緣物116形成在氮化層106附近例如覆蓋在其上。作為示例，但不作為局限，外部絕緣物116可以是BPSG。
閘極拾取電極122電連接到閘極金屬124。作為示例，但不作為局限，利用穿過外部絕緣物116、氮化層106和絕緣蓋108的垂直閘極接觸結構120，制備閘極連接結構。作為示例，但不作為局限，可以用鎢等導電材料制備垂直的閘極接觸結構120。依據本發明的一些方面，可以用鈦或氮化鈦等勢壘金屬165內襯設置有該垂直閘極接觸結構120的溝槽或接觸孔的側壁和/或底部。
肖特基區127包括一個或多個本體箝位(Body clamp，簡稱BCL)區121，用於防止有源器件在高於它們擊穿電壓的情況下運行。因此，必須設計BCL區121的深度，使該區域的肖特基擊穿電壓高於有源器件擊 穿電壓。在N-型半導體襯底101中，P-型摻雜物注入到襯底101中，形成BCL區121。作為示例，但不作為局限，利用離子注入系統，通過一次或多次注入工藝引入摻雜物。在10keV至500keV之間的能量範圍內，注入摻雜物。本發明的一些方面包括金屬接觸區129，金屬接觸區129是制備閘極接觸結構120和ESD連接結構112的原有工藝步驟的殘留物。作為示例，但不作為局限，金屬接觸區可以是鎢。肖特基接觸金屬125沉積在金屬接觸區129上方以及半導體襯底101上方。依據本發明的一些方面，肖特基接觸金屬125和半導體襯底之間可以內襯鈦或氮化鈦等勢壘材料如勢壘金屬165。另外，閘極金屬124和肖特基接觸金屬125相互電絕緣。
圖2表示器件結構100的布局圖。布局表示閘極電極109與器件區中的源極連接結構177相互相鄰交替分布。源極連接結構177垂直於圖平面延伸，與源極金屬117電接觸。閘極滑道119電連接到閘極電極109，連接到閘極拾取電極122。閘極電極、閘極滑道和閘極拾取電極可以由同種材料(例如多晶矽)制成，在一個共同的過程中這種材料形成在相應的溝槽中。閘極接觸結構120垂直於圖平面延伸，以便與閘極金屬124電接觸(圖中沒有表示出)。閘極金屬124最初作為與源極金屬117部分相同的金屬層形成。例如通過常用的掩膜、刻蝕、電介質填充等工藝，閘極金屬124與源極金屬117電絕緣。
BCL區121位於有源器件區外部，這可以從圖2所示肖特基接觸金屬125的位置看出。另外，ESD結構195可以形成在有源器件區外部。ESD結構195形成在絕緣層105等絕緣物上方。
圖3A-3O表示在制備過程的不同階段中器件結構300的剖面圖。垂直虛線用於區分有源區、閘極拾取區326以及肖特基區327。圖3A-3O從左至右表示這三個區域，但是要注意的是，多個可能的方向中只有一個可能的方向。另外，雖然表示出了全部三個區域，但是要注意的是依據本發明的各個方面，這三個區域並不一定全部需要。
圖3A表示半導體襯底301。襯底301可以適當摻雜成N-型或P-型襯底。作為示例，但不作為局限，半導體襯底可以是N-型矽襯底。半導體襯底301包括一個輕摻雜漂流區307，形成在襯底301的頂部，以及 一個重摻雜汲極接觸區302，形成在半導體襯底301的底部。氧化物-氮化物-氧化物(ONO)硬掩膜層形成在半導體襯底301的頂面上。作為示例，但不作為局限，底部氧化層357約為200Å，氮化層356約為3500Å，上方的頂部氧化層355約為1400Å。圖3B表示多個初始工藝步驟之後的器件結構300。首先，利用溝槽掩膜刻蝕襯底301中的溝槽348和349。溝槽348形成在器件結構300的有源區中，溝槽349形成在器件結構300的閘極拾取區326中。第一次刻蝕工藝包括利用蝕刻劑除去ONO硬掩膜層357、356、355，以便使襯底301的頂面裸露出來，再通過第二次刻蝕工藝，制備溝槽348和349的頂部371。作為示例，但不作為局限，溝槽348和349的頂部371約為0.5μm深。一旦形成溝槽之後，要在每個溝槽348、349中熱生長大約100Å的襯墊氧化物318a 。生長襯墊氧化物318a 之後，可以在襯墊氧化物318上方沉積一個氮化層346。作為示例，但不作為局限，氮化層346的厚度約為500Å。
圖3C表示溝槽底部372的形成過程。首先，通過一次或多個刻蝕工藝，除去溝槽底面上的氮化層346和氧化層318a 。此後，可以刻蝕溝槽371頂部下方的襯底301，以增加溝槽348、349的深度。作為示例，但不作為局限，溝槽348、349的頂部和底部的總深度約為1μm。此後，在溝槽底部372的裸露矽中熱生長襯裏氧化物318b 。作為示例，溝槽底部中襯裏氧化物318b的厚度T2 可以生長至600Å左右。沿溝槽頂部側壁的氮化層346作為一個掩膜，減小了溝槽底部372的寬度。然後，通過濕法刻蝕，除去溝槽頂部371側壁上的氮化物346和襯墊氧化物318a 。在溝槽頂部側壁處的裸露矽上生長一個閘極氧化物318c ，生長至所需厚度T1 。作為示例，但不作為局限，對於12V的器件來說，閘極氧化物318c 的厚度T1 約為265Å。因此，溝槽372底部的閘極氧化物318的厚度T2 大於溝槽371頂部的厚度T1 。在圖3D中，用導電材料填充溝槽348、349，以便形成閘極電極309和閘極拾取電極322。作為示例，但不作為局限，導電材料可以是N+ -摻雜多晶矽，通過化學氣相沉積(CVD)沉積多晶矽。利用化學機械拋光(CMP)除去多餘的多晶矽，並且使閘極電極309和閘極拾取電極322與硬掩膜的表面相平。然後，如圖3E所示，將閘極電極309、閘極拾取電極322回刻至 半導體襯底301的表面。通過幹刻蝕工藝，回刻閘極電極309、閘極拾取電極322。
在圖3F中，利用ONO硬掩膜作為自對準掩膜，在每個閘極電極309、閘極拾取電極322上方形成絕緣蓋308。當有源器件間距降至深亞微米級別時，為絕緣蓋308使用自對準掩膜，可以降低失準的可能性。作為示例，但不作為局限，絕緣蓋308可以是氧化物。一旦形成絕緣蓋308之後，可以通過CMP除去ONO硬掩膜的頂部氧化層355。通過CMP還可以使絕緣蓋308與氮化層356相平。依據本發明的某些方面，可以選擇將靜電放電(ESD)保護可選件引入到器件的有源區中。為了制備ESD保護可選件ESD結構395，可以在氮化層356的表面上形成一個多晶矽層。然後，利用ESD掩膜，選擇性地刻蝕多晶矽層並留下部分多晶矽形成ESD電極323。在圖3G中，氧化ESD電極323，形成ESD絕緣蓋314，以便在後續的工藝步驟中，保護表面。作為示例，但不作為局限，絕緣蓋314的厚度約為300Å。形成ESD絕緣蓋314之後，除去氮化層356。作為示例，通過熱磷酸濕法腐蝕，除去氮化層356。ESD電極323和絕緣蓋314下方的那部分氮化層356被保護起來，不被濕法刻蝕除去。
在圖3H中，制備本體區303。作為示例，但不作為局限，利用本體掩膜和全面注入，或者通過離子注入系統選擇性地注入離子，制備本體區303。圖3H還表示制備源極區304。作為示例，但不作為局限，利用源極掩膜和全面注入，或者通過離子注入系統選擇性地注入離子，制備源極區304。屏蔽閘極拾取區326和肖特基區327，不接受本體注入和源極注入。此外，圖3H還表示出了本體鉗位(BCL)區321的注入。利用BCL掩膜，通過一次或多次注入工藝，注入BCL區321。作為示例，但不作為局限，第一次注入是在大約40keV下注入BF2 形成的淺P+ 注入。同時，第二次注入工藝，是在大約100keV下利用硼注入，改變了BCL區321注入的深度和成分。在大約300keV下，利用硼注入，深注入可以改變BCL區321注入的深度和成分。
圖3I表示沉積一個很厚的犧牲絕緣層311’。作為示例，犧牲絕緣層的厚度可以是1,100Å。而且，作為示例，絕緣層311’可以是通過 帶有四乙基原矽酸鹽(TEOS)等氣源氣體的化學氣相沉積法CVD所沉積的氧化物。還可選擇，絕緣層311’可以是通過使用SiH4 和NH3 氣體混合物的CVD工藝所沉積的氮化物材料。然後，在圖3J中，利用各向異性刻蝕(例如幹刻蝕工藝)，刻蝕厚絕緣層311’，從而在每個絕緣蓋308的一側以及沿ESD結構395側邊，形成第一絕緣墊片311。作為示例，第一絕緣墊片311的厚度可以是1000Å。當絕緣層311’是氧化物時，刻蝕工藝可以在矽襯底的表面終止，從而除去ONO硬掩膜上不在第一絕緣墊片311下方的那部分底部氧化層357。然後，在襯底301的表面上方，生長襯墊氧化物305。作為示例，但不作為局限，襯墊氧化物305的厚度可以是100Å。
圖3J’表示當絕緣層311’為氮化物材料時，制備可以用在器件中的第一絕緣墊片311的可選工藝。可以通過各向異性刻蝕工藝，選擇性地刻蝕掉氮化物材料，在適當的位置保留ONO硬掩膜的底部氧化層357。因此，無需生長襯墊氧化物305。一旦形成第一絕緣墊片311之後，具有由氮化物材料制成的第一絕緣墊片311的器件工藝，可以繼續用上述由氧化物制成的第一絕緣墊片311的制備工藝相同的方式進行。
制成第一絕緣墊片311之後，如圖3K所示，可以在表面上方沉積一個犧牲氮化層306。作為示例，氮化層306的厚度可以是300Å。可以利用SiH4 和NH3 氣體混合物的CVD工藝，沉積氮化層306。如圖3L所示，通過CVD工藝，在氮化層306上方，沉積一個厚的含有硼酸的矽玻璃(BPSG)層316。
在圖3M中，利用接觸掩膜，提供到ESD電極323、閘極拾取電極322和BCL區321(或稱BCL結構)的垂直接觸的接口。刻蝕工藝可以利用三個單獨的刻蝕步驟。首先，利用刻蝕除去BPSG層316，但並不除去BPSG下方的氮化層306。由於作為刻蝕終止層的氮化物層306的存在，不可能發生過度刻蝕，因此對BPSG層316可以使用快速刻蝕。第二次刻蝕是通過對氮化層306進行選擇性刻蝕。然後，利用對氧化物具有高選擇性的第三次刻蝕，為閘極拾取電極322穿透絕緣蓋308，為ESD電極穿透ESD絕緣蓋314，為肖特基區327穿透氧化層305。
在圖3N中，沉積一個光致抗蝕劑層361，利用第二接觸掩 膜使有源晶胞區即晶體管單元區裸露出來。此後，進行第一次刻蝕工藝，選擇性地除去有源區上方的BPSG層316。第二次各向異性刻蝕工藝，例如幹刻蝕工藝，可以選擇性地除去犧牲氮化層306。由於各向異性刻蝕的方向選擇性，刻蝕後仍然留下一部分犧牲氮化層306。剩餘的犧牲氮化層306成為第二絕緣墊片材料310。第二絕緣墊片材料310自對準接觸溝槽347。如上所述，由於自對準的源極接觸減少了失準的幾率，從而增強了可擴展性。接下來的刻蝕工藝除去擴孔氧化層305，最後刻蝕半導體襯底301，例如大約035Å的深度，以便通過自對準接觸溝槽347，連接到源極和本體區。
圖3O表示器件結構300最終的工藝步驟。首先，在整個表面上方沉積一個勢壘金屬365，它可以防止擴散到源極區304中。作為示例，但不作為局限，勢壘金屬可以是通過物理氣相沉積(PVD)所沉積的鈦，或者通過CVD或PVD沉積的TiN等合金。沉積勢壘金屬365之後，可以沉積導電材料，以形成垂直源極連接結構377、ESD連接結構312和閘極連接結構320。作為示例，但不作為局限，通過CVD所沉積的鎢制備垂直連接結構。一旦沉積一層鎢之後，回刻這層鎢，保留最初在垂直接觸孔中的鎢。另外，肖特基區中可能會殘留多餘的鎢329。然後，在整個表面上方沉積金屬，形成到垂直源極連接結構377、ESD連接結構312和閘極連接結構320以及BCL區321的適當接觸。作為示例，但不作為局限，沉積的金屬可以是濺射的鋁。最後，利用金屬掩膜，刻蝕掉一部分沉積的金屬，從而使ESD金屬328、源極金屬317、閘極金屬324以及肖特基接觸金屬325中的接觸區電絕緣。
盡管以上是本發明的較佳實施例的完整說明，但是也有可能使用各種可選、修正和等效方案。因此，本發明的範圍不應局限於以上說明，而應由所附的申請專利範圍書及其全部等效內容決定。本方法中所述步驟的順序並不用於局限進行相關步驟的特定順序的要求。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種” 都指下文內容中的一個或多個項目的數量。除非在指定的申請專利範圍中用“意思是”特別指出，否則所附的申請專利範圍書應認為是包括意義及功能的限 制。
118‧‧‧閘極氧化物
107‧‧‧外延層
100‧‧‧器件
101‧‧‧襯底
102‧‧‧汲極區
102’‧‧‧汲極電極
103‧‧‧本體層
104‧‧‧源極區
195‧‧‧ESD結構
171‧‧‧頂部
172‧‧‧底部
109‧‧‧閘極電極
108‧‧‧絕緣閘極蓋
117‧‧‧源極金屬
177‧‧‧連接結構
111‧‧‧第一絕緣墊片
110‧‧‧第二絕緣墊片
116‧‧‧外部絕緣物
112‧‧‧垂直連接結構
123‧‧‧ESD電極
128‧‧‧ESD金屬
106‧‧‧第二氮化層
114‧‧‧ESD絕緣蓋
156‧‧‧氮化層
165‧‧‧勢壘金屬
157‧‧‧絕緣層

Claims (23)

  1. 一種MOSFET器件的制備方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中半導體襯底包括一個輕摻雜的漂流區，形成在襯底頂部，其中硬掩膜包括第一、第二和第三絕緣層，其中第二絕緣層夾在第一和第三絕緣層之間，其中第三絕緣層位於第二絕緣層和半導體襯底頂面之間，其中第二絕緣層可以抵抗刻蝕第一和第三絕緣層材料的刻蝕工藝，其中第一和第三絕緣層可以抵抗刻蝕第二絕緣層材料的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在絕緣閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平面處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，向下刻蝕硬掩膜的第一絕緣層到硬掩膜第二絕緣層的水平面處，利用第二次刻蝕工藝，除去硬掩膜的第二絕緣層，保留與溝槽對準的絕緣閘極蓋突出至硬掩膜第三絕緣層的水平面上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)在本體層頂部，制備一個第一導電類型的源極層；i)在絕緣閘極蓋和硬掩膜第三絕緣層的裸露部分上方，制備一個第一絕緣墊片層，並且各向異性地刻蝕第一絕緣墊片層，保留沿著絕緣閘極蓋側壁的那部分第一絕緣墊片層，作為第一絕緣墊片； j)在硬掩膜第三絕緣層的裸露部分、絕緣閘極蓋和第一絕緣墊片上方，制備一個第二絕緣墊片層，各向異性地刻蝕第二絕緣墊片層，保留沿著第一絕緣墊片裸露側壁的那部分第二絕緣墊片層，作為第二絕緣墊片；並且k)利用第一和第二絕緣墊片作為自對準掩膜，在半導體襯底中制備用於源極接觸的接觸開口。
  2. 如申請專利範圍第1項所述的方法，其中制備多個溝槽包括穿過硬掩膜中的開口刻蝕襯底，形成溝槽頂部；沿溝槽頂部的側壁和底面生長一個犧牲絕緣層，並且沿側壁在犧牲絕緣層上制備墊片；將所述的墊片作為掩膜，通過刻蝕沉積在溝槽頂部底面上的犧牲絕緣層，以及溝槽頂部下方的襯底，形成溝槽底部；沿溝槽底部的側壁和底面，生長底部絕緣層；除去墊片和犧牲絕緣層；並且沿溝槽頂部的側壁，生長頂部絕緣層。
  3. 如申請專利範圍第1項所述的方法，其中硬掩膜為氧化物-氮化物-氧化物硬掩膜，其中第一和第三絕緣層由氧化物材料制成，第二絕緣層由氮化物材料制成。
  4. 如申請專利範圍第1項所述的方法，其中通過CVD工藝，將第一絕緣墊片層沉積在表面上方，其中第一絕緣墊片層包括由四乙基原矽酸鹽(TEOS)氣制成的氧化物。
  5. 如申請專利範圍第1項所述的方法，其中用於制備第一絕緣墊片層的材料與絕緣閘極蓋的制備材料相同。
  6. 如申請專利範圍第5項所述的方法，其中各向異性刻蝕第一絕緣墊片層還包括通過對刻蝕掉的那部分第一絕緣墊片層下方的那部分硬掩膜第三絕緣層的刻蝕，使得半導體襯底的一部分頂面裸露出來。
  7. 如申請專利範圍第6項所述的方法，還包括：在裸露的那部分半導體襯底的頂面上方，生長一個襯墊絕緣層。
  8. 如申請專利範圍第1項所述的方法，其中第一絕緣墊片和第二絕緣墊片由相同的材料制成。
  9. 如申請專利範圍第1項所述的方法，其中第一絕緣墊片層由氧化物制成，第二絕緣墊片層由氮化物制成。
  10. 如申請專利範圍第9項所述的方法，其中通過CVD工藝，在表面上方沉積第二絕緣墊片層。
  11. 如申請專利範圍第10項所述的方法，其中第二絕緣墊片層的厚度約為300Å。
  12. 如申請專利範圍第1項所述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極拾取溝槽中沉積導電材料，以制備閘極拾取電極。
  13. 如申請專利範圍第1項所述的方法，還包括：在氮化層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜之前，在硬掩膜第二絕緣層的上方，制備一個靜電放電(ESD)保護電極。
  14. 如申請專利範圍第13項所述的方法，還包括除去硬掩膜的第二絕緣層之前，氧化ESD保護電極的表面。
  15. 如申請專利範圍第1項所述的方法，還包括：除去硬掩膜的第二絕緣層之後，制備一個或多個本體鉗位(BCL)結構，其中BCL結構是通過兩次或多次摻雜物注入工藝制成的。
  16. 如申請專利範圍第15項所述的方法，還包括，制備帶有BCL結構的肖特基接觸金屬。
  17. 一種MOSFET器件，包括：一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜漂流區，位於襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反；由半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都包括一個用閘極氧化物絕緣的閘極電極，其中閘極氧化物的頂部厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個或多個第一導電類型的源極區，形成在閘極電極附近的本體區頂部；形成在每個閘極電極上方的絕緣閘極蓋，其中第一絕緣墊片形成在絕緣閘極蓋的側壁上，第二絕緣墊片形成在第一絕緣墊片的裸露側壁上；一個在本體區頂面上方的絕緣層；一個形成在絕緣層上方的導電源極電極層；將源極電極層連接到一個或多個源極區上的一個或多個電連接結構，其中通過第一和第二絕緣墊片，將一個或多個電連接結構與絕緣閘極蓋分隔開。
  18. 如申請專利範圍第17項所述的MOSFET器件，其中第一絕緣墊片和第二絕緣墊片都是由氮化物材料制成的。
  19. 如申請專利範圍第17項所述的MOSFET器件，其中第二絕緣墊片可以抵抗第一次刻蝕工藝，第一次刻蝕工藝用於選擇性刻蝕制備第一絕緣 墊片的材料，其中第一絕緣墊片可以抵抗第二次刻蝕工藝，第二次刻蝕工藝用於選擇性刻蝕制備第二絕緣墊片的材料。
  20. 如申請專利範圍第19項所述的MOSFET器件，其中第一絕緣墊片為氧化物材料，第二絕緣墊片為氮化物材料。
  21. 如申請專利範圍第17項所述的MOSFET器件，還包括：一個或多個靜電放電(ESD)保護ESD結構，形成在絕緣層上方。
  22. 如申請專利範圍第17項所述的MOSFET器件，還包括一個或多個閘極拾取結構，形成在半導體襯底中。
  23. 如申請專利範圍第17項所述的MOSFET器件，還包括一個本體鉗位(BCL)結構。
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