TWI502723B - 多晶粒堆疊封裝結構 - Google Patents

多晶粒堆疊封裝結構 Download PDF

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Publication number
TWI502723B
TWI502723B TW099119781A TW99119781A TWI502723B TW I502723 B TWI502723 B TW I502723B TW 099119781 A TW099119781 A TW 099119781A TW 99119781 A TW99119781 A TW 99119781A TW I502723 B TWI502723 B TW I502723B
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Taiwan
Prior art keywords
die
bumps
active surface
substrate
back surface
Prior art date
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TW099119781A
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English (en)
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TW201201347A (en
Inventor
David Wei Wang
An Hong Liu
Hsiang Ming Huang
Jar Dar Yang
Yi Chang Lee
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Chipmos Technologies Inc
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=45327931&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TWI502723(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW099119781A priority Critical patent/TWI502723B/zh
Priority to US13/004,946 priority patent/US8269352B2/en
Priority to US13/004,960 priority patent/US8264068B2/en
Priority to US13/004,936 priority patent/US8269351B2/en
Publication of TW201201347A publication Critical patent/TW201201347A/zh
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Publication of TWI502723B publication Critical patent/TWI502723B/zh

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Description

多晶粒堆疊封裝結構
本發明係關於一種多晶粒堆疊封裝結構；特別是有關於一種使用金屬導線連接凸塊之晶圓級堆疊封裝結構。
在現今的資訊社會中，隨著可攜式產品的成功開發，使用者均是追求高速度、高品質、多功能性的可攜式電子產品，例如：筆記型電腦(Note Book)、3G手機、個人數位助理(PDA)以及遊戲機(Video Game)等。就產品外觀而言，可攜式電子產品的設計是朝向輕、薄、短、小的趨勢邁進。為了達到上述目的，發展出多晶粒堆疊結構是必須的趨勢，而多晶粒堆疊結構即是在相同的封裝體尺寸之下，將多個晶粒以堆疊的方式相接合並電性連接，以增加記憶體的容量或增加更多的功能。
隨著製程的進步，可攜式系統中的每一個晶粒間的匯流排(Bus)所需要的操作速度及頻寬越來越大，而系統的匯流排的速度及頻寬則是取決於封裝(Package)的技術，特別是在將多種不同功能的晶粒封裝在一起的系統級封裝(System in Package；SiP)。因此，在設計多晶粒堆疊結構時，具有更快的傳輸速度、更短的傳輸路徑以及更佳的電氣特性，並進一步縮小晶粒封裝結構的尺寸及面積，因而使得晶粒堆疊結構已經普遍應用於各種電子產品之中，並成為未來的主流產品。
而在實施的製造過程中，多晶粒堆疊結構的封裝卻面臨著挑戰。首先，隨著各種消費性產品的性能提升，對於記憶體的容量需求也愈大，因此，當要製造大容量的動態記憶體(DRAM)時，例如：4Gb容量的DRAM；就需要將四顆1Gb DRAM封裝在一起， 如第13A圖所示；若要製造8Gb容量的DRAM；就需要將八顆1Gb DRAM封裝在一起。隨著晶粒數的增加，使用傳統的金屬導線來作為晶粒間的連接導線(trace)時，除了會因為連接路徑的增加，或是在製造過程中使得連接導線的長度不一致，而會造成訊號傳遞速度降低或產生時間延遲等效應，進而造成系統無法運作或是造成系統存取資料錯誤等問題外；使用傳統的金屬導線來作為多個晶粒堆疊的連接導線時，還面臨到另一個問題，就是封裝尺寸的問題，也就是說，一個多個晶粒堆疊結構的高度與面積是受限制的，而這也是使用傳統的金屬導線來作為晶粒間的多個晶粒堆疊的另一問題。
而為了解決此一問題，使用線路重分配層(RDL)可以達到縮短多晶粒堆疊間的連接路徑，同時也可以有效地克服多個晶粒堆疊高度的問題，如第13B圖所示。然而，線路重分配層(RDL)的高製造成本讓許多高性能之產品聞之卻步。
因此，在多晶粒堆疊結構中，保持良好的電氣特性以及最適尺寸的前題下，如何以最低的製造成本來完成，已是一個重要且需解決的議題。
為了解決先前技術中，有關多晶粒堆疊結構中之晶粒與晶粒間的連接導線過長及連接導線的長度不一致等問題，本發明提供一種使用金屬導線連接凸塊之晶圓級堆疊封裝結構，其主要目的在提供多晶粒堆疊封裝，其能夠以堆疊結構來控制晶粒與晶粒間連接導線等長的需求，使得完成封裝後的多晶粒堆疊結構能具有較佳得電氣特性及可靠度。
本發明之另一主要目的，在提供一種使用傳統金屬導線與凸塊的連接來作為多晶粒堆疊結構之連接方式，用來取代線路重分配層(RDL)，以降低多晶粒堆疊結構之製造成本。
本發明之另一主要目的，在提供一種使用傳統金屬導線與矽貫通孔技術(Trough-Silicon-Vias,TSVs)的連接來作為多晶粒堆疊結構之連接方式，可以有效地降低封裝高度以增加堆疊之集成度，並同時增加操作速度及頻寬。
本發明之還有一主要目的，在提供一種使用傳統金屬導線與凸塊的連接來作為多晶粒堆疊結構之連接方式或是使用傳統金屬導線與矽貫通孔技術的連接來作為多晶粒堆疊結構之連接方式，以形成系統級之封裝結構。
依據上述之目的，本發明首先提供一種多晶粒堆疊封裝結構，包括一基板，具有一上表面及一下表面，其上表面上定義一晶粒設置區及配置有複數個接點，而接點位於晶粒設置區之外；一第一晶粒，具有一主動面及相對主動面之一背面，第一晶粒係以背面設置於晶粒設置區，其主動面上配置有複數個第一銲墊且第一銲墊上形成一第一凸塊；複數條金屬導線，用以連接第一凸塊至接點；一第二晶粒，具有一主動面及相對主動面之一背面，其主動面上配置有複數個第二銲墊，第二銲墊上形成一第二凸塊，第二晶粒係以主動面面對第一晶粒之主動面接合第一晶粒，使第二凸塊分別對應連接金屬導線及第一凸塊；一封膠體，用以覆蓋基板、第一晶粒、第二晶粒及金屬導線。
本發明接著提供一種多晶粒堆疊封裝結構，包括一基板，具有一上表面及一下表面，其上表面上定義一晶粒設置區及配置有複數個接點，接點位於晶粒設置區之外；一第一晶粒，具有一主動面及相對主動面之一背面，第一晶粒係以背面設置於晶粒設置 區，其主動面上配置有複數個第一銲墊且第一銲墊上形成一第一凸塊；一第二晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，直通矽晶栓塞係貫穿第二晶粒以使主動面與背面間相互電性連接，其主動面上形成複數個第二凸塊分別連接直通矽晶栓塞，其中第二晶粒係以背面面對第一晶粒之主動面接合第一晶粒，使直通矽晶栓塞分別對應連接第一凸塊；複數條金屬導線，用以連接第二凸塊至接點；一第三晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，直通矽晶栓塞係貫穿第三晶粒以使主動面與背面間相互電性連接，其主動面上形成複數個第三凸塊分別連接直通矽晶栓塞，其中第三晶粒係以主動面面對第二晶粒之主動面以接合第二晶粒，使第三凸塊分別對應連接金屬導線及第二凸塊；一第四晶粒，具有一主動面及相對主動面之一背面，其主動面上配置有複數個第二銲墊，且第二銲墊上形成一第四凸塊，第四晶粒係以主動面面對第三晶粒之背面接合第三晶粒，使第四凸塊分別對應連接第三晶粒之直通矽晶栓塞；一封膠體，用以覆蓋基板、第一晶粒、第二晶粒、第三晶粒、第四晶粒及金屬導線。
本發明再提供一種多晶粒堆疊封裝結構，包括一基板，具有一上表面及一下表面，其上表面上定義一晶粒設置區及配置有複數個接點，晶粒設置區內形成一凹槽，而接點位於晶粒設置區之外；一第一晶粒，具有一主動面及相對主動面之一背面，第一晶粒係以背面設置於凹槽中，其主動面上配置有複數個第一銲墊且第一銲墊上形成一第一凸塊；複數條金屬導線，用以連接第一凸塊至接點；一第二晶粒，具有一主動面及相對主動面之一背面，其主動面上配置有複數個第二銲墊，第二銲墊上形成一第二凸塊，第二晶粒係以主動面面對第一晶粒之主動面接合第一晶粒， 使第二凸塊分別對應連接金屬導線及第一凸塊；一封膠體，用以覆蓋基板、第一晶粒、第二晶粒及金屬導線。
本發明再接著提供一種多晶粒堆疊封裝結構，包括一基板，具有一上表面及一下表面，其上表面上定義一晶粒設置區及配置有複數個接點，晶粒設置區內形成一凹槽，接點位於晶粒設置區之外；一第一晶粒，具有一主動面及相對主動面之一背面，第一晶粒係以背面設置於凹槽中，其主動面上配置有複數個第一銲墊且第一銲墊上形成一第一凸塊；一第二晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，直通矽晶栓塞係貫穿第二晶粒以使主動面與背面間相互電性連接，其主動面上形成複數個第二凸塊分別連接直通矽晶栓塞，其中第二晶粒係以背面面對第一晶粒之主動面接合第一晶粒，使直通矽晶栓塞分別對應連接第一凸塊；複數條金屬導線，用以連接該等第二凸塊至接點；一第三晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，直通矽晶栓塞係貫穿第三晶粒以使主動面與背面間相互電性連接，其主動面上形成複數個第三凸塊分別連接直通矽晶栓塞，其中第三晶粒係以主動面面對第二晶粒之主動面接合第二晶粒，使第三凸塊分別對應連接金屬導線及第二凸塊；一第四晶粒，具有一主動面及相對主動面之一背面，其主動面上配置有複數個第二銲墊，且第二銲墊上形成一第四凸塊，第四晶粒係以主動面面對第三晶粒之背面接合第三晶粒，使第四凸塊分別對應連接第三晶粒之直通矽晶栓塞；一封膠體，用以覆蓋基板、第一晶粒、第二晶粒、第三晶粒、第四晶粒及金屬導線。
本發明再接著提供一種多晶粒堆疊封裝結構，包括一基板，具有一上表面及一下表面，其上表面上定義一晶粒設置區及配置有複數個接點，接點位於晶粒設置區之外；一第一晶粒，具有一 主動面及相對主動面之一背面，第一晶粒係以背面設置於晶粒設置區，其主動面之週邊區域上配置有複數個第一銲墊且第一銲墊上形成一第一凸塊；複數條金屬導線，用以連接該等第一凸塊至接點；一第二晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，每一直通矽晶栓塞係貫穿第二晶粒以使主動面與背面間相互電性連接，且每一直通矽晶栓塞於主動面形成一第一端並於背面形成一第二端，而於至少部份直通矽晶栓塞之第二端上分別形成一第二凸塊，其中第二晶粒係以背面面對第一晶粒之主動面接合第一晶粒，使第二凸塊分別對應連接金屬導線及第一凸塊；一第三晶粒，具有一主動面及相對主動面之一背面以及複數個直通矽晶栓塞，每一直通矽晶栓塞係貫穿第三晶粒以使主動面與背面間相互電性連接，且每一直通矽晶栓塞於主動面形成一第一端並於背面形成一第二端，而於至少部份直通矽晶栓塞之第二端上分別形成一第三凸塊，其中第三晶粒係以背面面對第二晶粒之主動面接合第二晶粒，使第三晶粒之第三凸塊分別對應連接第二晶粒之直通矽晶栓塞之第一端；一封膠體，用以覆蓋基板、第一晶粒、第二晶粒、第三晶粒及金屬導線。
本發明在此所探討的方向為一種使用金屬導線連接凸塊之晶圓級堆疊封裝結構，其主要目的在提供多晶粒堆疊封裝能夠以堆疊結構來控制連接導線等長的需求，使得完成封裝後的多晶粒堆疊結構能具有較佳得電氣特性及可靠度。為了能徹底地瞭解本發明，將在下列的描述中提出詳盡的步驟及其組成。顯然地，一方面，本發明的施行並未限定晶粒堆疊的方式，特別是一些此技藝領域者所熟習的各種晶粒堆疊方式。另一方面，眾所周知的晶粒形成方式以及晶粒薄化等後段製程之詳細步驟並未描述於細節 中，以避免造成本發明不必要之限制。然而，對於本發明的較佳實施例，則會詳細描述如下，然而除了這些詳細描述之外，本發明還可以廣泛地施行在其他的實施例中，且本發明的範圍不受限定，其以之後的專利範圍為準。
首先，請參考第1圖，在現代的半導體封裝製程中，均是將一個已經完成前段製程(Front End Process)之晶圓10(wafer)進行切割製程(sawing process)以形成一顆顆的晶粒100，其中每一晶粒之主動面上均配置有複數個銲墊110；而在本發明之實施例中，每一晶粒之主動面上所配置的複數個銲墊110係位於主動面的中央區域，如第1圖所示。
接著，請參考第2A~2H圖，係本發明之形成多晶粒堆疊結構過程之一實施例的剖面示意圖。首先，如第2A圖所示，晶粒100具有主動面101及相對之背面103，而主動面101上配置有複數個銲墊110，此複數個銲墊110係位於晶粒100主動面101之中央區域。接著，請參考第2B圖，在銲墊110上形成一個凸塊20，特別是一種結線凸塊(STUD BUMP)，且此結線凸塊係以打線技術燒結形成一凸塊於銲墊110上。在此要強調，凸塊20可以是一種電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊，對此，本發明並不加以限制。而凸塊20之材料可以選自下列群組：銅、金、銀、銦、鎳/金、鎳/鈀/金、銅/鎳/金、銅/金、鋁、導電高分子材料及其組合等。此時，已形成複數顆完成凸塊20製程的晶粒100。再接著，請參考第2C圖，係將一個如第2B圖的第一晶粒100a的背面103以黏著層120黏貼於基板200之上表面210上，其中，本發明之基板200的上表面210上定義有一晶粒設置區(圖未顯示)並配置有複數個接點240，這些接點240係位於晶粒設置區之外，而第一晶粒100a即是以黏著層120黏貼於基板200 之晶粒設置區內。此外，在基板200的下表面220上，則配置有複數個外部接點230，而外部接點230上可進一步配置電性連接元件，例如：錫球(顯示於第4圖中)，以作為對外之電性連接之用。再者，請參考第2D圖，係將第2C圖中的第一晶粒100a上的第一凸塊20a藉由複數條金屬導線30電性連接至基板200上的接點240上，如第2D及2E圖所示(其中，第2D圖係第2E圖之上視圖)。而形成此金屬導線30之方式，可以選擇逆打線製程來執行。然後，請參考第2F圖，係將一個如第2B圖的第二晶粒100b以覆晶(flip chip)方式接合第2E圖的第一晶粒100a，使第二凸塊20b分別對應連接至金屬導線30及第一晶粒100a的第一凸塊20a。因此，第一晶粒100a及第二晶粒100b形成電性連接，並進一步藉由金屬導線30電性連接至基板200。
此外，要特別說明的是當前述之實施例中的凸塊20為一種軟性金屬材料，例如金時，即可藉由軟性金屬之低硬度、高韌性及良好的順應共平面特性(compliancy)，使得在進行多晶粒垂直堆疊時，可以在電極(即凸塊)的接合界面上去吸收因為金屬電極材料間熱膨脹係數不匹配，而在橫向與縱向所產生的變形(Deformation)，也可以有效去克服金屬電極材料間粗糙度的問題，故可有效地增加多晶粒垂直堆疊之製程及產品的可靠度。
再請參考第2G圖，選擇性地進行一個高分子材料之充填製程，使得高分子材料充填於兩個晶粒100a、100b的主動面101之間的空間，以形成一密封層80，以穩固堆疊結構並提供電性接點保護作用。此充填製程可在完成第2F圖後使用高壓方式將高分子材料充填於晶粒100a、100b間的空隙中，也可以在覆晶接合第二晶粒100b之前，先塗佈或貼設於第2E圖的第一晶粒100a上。而此密封層80可以選自下列群組：非導電膠(non-conductive paste； NCP)、非導電膜(non-conductive film；NCF)、異方性導電膠(anisotropic conductive paste；ACP)、異方性導電膜(anisotropic conductive film；ACF)、底部填充膠(underfill)、非流動底部填充膠(non-flow underfill)、B階膠(B-stage resin)、模塑化合物、FOW(film-over-wire)薄膜等。
最後，再進行一封膠製程，以形成一封膠體90，用以覆蓋基板200、第一晶粒100a、第二晶粒100b及金屬導線30。至此，即完成本實施例之多晶粒堆疊封裝結構，如第2H圖所示。
在本實施例的多晶粒堆疊封裝結構中，多個晶粒100間係使用覆晶方式將每一晶粒100之主動面101上的複數個銲墊110對應地連接在一起，並藉由金屬導線30連接至基板200上表面210上的接點240。很明顯地，本實施例中，連接每一晶粒100之主動面101上的每一個銲墊110到基板200上表面210上所對應的每一個接點240所使用的金屬導線30之長度均相同，因此可以克服第13A圖中，不同晶粒使用不同長度的金屬導線來電性連接而造成訊號傳遞產生時間延遲等效應，進而造成系統無法運作或是造成系統存取資料錯誤等問題。也因此，本實施例具有較佳的電氣特性及可靠度。
接著，請參考第2I圖所示，係於基板200之結構中嵌埋入一個控制晶粒500，並將控制晶粒500與基板200形成電性連接，使控制晶粒500之主動面透過基板200內之線路與配置於基板200下表面220的複數個外部接點230電性連接；此外，控制晶粒500嵌埋之方式可以是在多層電路板形成過程中，即將此控制晶粒500配置於基板200中，由於將控制晶粒500嵌埋入基板200中係利用習知技術形成，故不再詳細說明。很明顯地，第2I圖與第2H圖之差異在：於第2H圖中進一步配置一嵌埋於基板200中的控制 晶粒500，其餘形成第一晶粒100a及第二晶粒100b之連接過程均與第2C圖至第2H圖相同，因此不再贅述之。
請參考第3圖，其係本發明之多晶粒堆疊結構之另一實施例之剖面示意圖。於本實施例中，在完成前述之第2E圖之結構後，係進一步形成另一個結線凸塊40於每一條金屬導線30與第一凸塊20a電性連接的接觸點上，結線凸塊40係以打線技術燒結形成一凸塊並壓銲在金屬導線30與第一凸塊20a的連接點上，用以增強金屬導線30的接合強度並提供後續覆晶接合緩衝效果；接著，再將一個如第2B圖的第二晶粒100b以覆晶方式接合第一晶粒100a，使第二晶粒100b之第二凸塊20b分別對應連接至結線凸塊40，因此，第一晶粒100a及第二晶粒100b形成電性連接，並進一步藉由金屬導線30電性連接至基板200。本實施例並不限制設置於每一金屬導線30與第一凸塊20a連接點上的結線凸塊40之數量，其數量可視電性及高度需求作調整。與前述實施例相同，選擇性地進行一個高分子材料之充填製程，以形成一密封層80於兩個晶粒100a、100b的主動面101之間的空間。此密封層80之形成方法與材料係與前述實施例相同，故不再重複說明。最後，進行封膠製程，以形成一封膠體90用以覆蓋基板200、第一晶粒100a、第二晶粒100b及金屬導線30。
在本實施例的晶粒堆疊封裝結構中，多個晶粒100間係使用覆晶方式將每一晶粒100主動面101上的複數個銲墊110對應地連接在一起，並藉由金屬導線30連接至基板200上表面210上的接點240。很明顯地，本實施例中，連接每一晶粒100之主動面101上的每一個銲墊110到基板200上表面210上所對應的每一個接點240所使用的金屬導線30之長度均相同，因此可以克服不同晶粒使用不同長度的金屬導線來電性連接而造成訊號傳遞產生時 間延遲等效應，進而造成系統無法運作或是造成系統存取資料錯誤等問題。也因此，本實施例具有較佳的電氣特性及可靠度。
再接著，請參考第4圖，其係本發明之多晶粒堆疊封裝結構之再一實施例之剖面示意圖。相同地，本實施例的基板200的上表面210上定義有一晶粒設置區(圖未顯示)並配置有複數個接點240，晶粒設置區內係形成一凹槽250(cavity)，而這些接點240係位於晶粒設置區之外，其中，此凹槽250的長度及寬度大於晶粒100的長度及寬度，故可使用機械設備將一個如第2B圖之第一晶粒100a以其背面103並藉由黏著層120黏貼於凹槽250中。接著，可以選擇逆打線製程，以複數條金屬導線30將第一晶粒100a主動面101上的第一凸塊20a電性連接至基板200上的接點240。很明顯地，當基板200之凹槽250經過適當的設計，例如：將凹槽250之深度設計成與第一晶粒100a的厚度相近，因此，當第一晶粒100a以其背面103黏貼於凹槽250時，基板200上表面210上的接點240與第一晶粒100a上的第一凸塊20a有相近的高度，故使得複數條金屬導線30可以以最小的弧度及最短的長度來將基板200上的接點240與第一晶粒100a上的第一凸塊20a電性連接在一起，故可以使得此多晶粒堆疊結構具有最佳之電氣特性。再接著，將一個與第2B圖相同的第二晶粒100b，以覆晶方式將第二凸塊20b分別對應連接至固定在凹槽250中的第一晶粒100a上的金屬導線30以及第一凸塊20a，以形成一個多晶粒堆疊結構。同樣地，也可以選擇地進行一個高分子材料之充填製程，以形成一密封層80於兩個晶粒100a、100b的主動面101之間的空間，以穩固堆疊結構。再者，進行一封膠製程，以形成一封膠體90用以覆蓋基板200、第一晶粒100a、第二晶粒100b及金屬導線30，而第一晶粒100a與凹槽250間的空隙亦同時被封膠體90填滿。 由於，密封層充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可以進行一植球製程，在基板200之下表面220上的複數個外部接點230上配置錫球260，以作為對外之電性連接元件。故當此堆疊結構中的每一個晶粒100均為一個1Gb DRAM時，則此多晶粒堆疊之封裝結構即成為一個2Gb DRAM之產品，可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
很明顯地，在第4圖的實施例中，可以使用最佳的金屬導線30長度來連接兩個晶粒100a、100b上的凸塊20a、20b至基板200的接點240，使得本實施例具有較佳的電氣特性及可靠度。再者，經由基板200上凹槽250的配置，使得整個多晶粒堆疊封裝結構的高度可以明顯地降低。更有進者，本實施例也可以類似第3圖，於金屬導線30連接第一晶粒100a上的凸塊20a後，另形成結線凸塊40於每一條金屬導線30與第一凸塊20a的連接點上，用以增強金屬導線30的接合強度並提供後續覆晶接合緩衝效果。如此，可以使得多晶粒堆疊封裝結構在電極處具有較佳的熱膨脹係數的匹配，可以增加封裝體的可靠度。
請再接著參考第5A圖至第5E圖，係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構實施例之剖面示意圖。首先，如第5A圖所示，係本發明之具有直通矽晶栓塞的晶粒300之剖面示意圖。晶粒300具主動面301以及相對於主動面301的背面303，晶粒300上形成有複數個貫穿晶粒300的垂直貫穿孔。而形成貫穿孔的方式可以選擇雷射鑽孔(laser drilling)、乾蝕刻(dry etching)或濕式蝕刻(wet etching)等方式形成，其中貫穿孔的寬度可以介於1微米(um)至50微米(um)之間，而一較佳之寬度為10微米(um)至20微米(um)。於貫穿孔內進一步形成直通矽晶栓塞330(TSV) 以使主動面301與背面303間相互電性連接。這些直通矽晶栓塞330的第一端331係鄰近晶粒300之主動面301，而相對之第二端333係鄰近晶粒300之背面303。直通矽晶栓塞330之材料係可選自下列群組：銅、鎢、鎳、鋁、金、多晶矽(poly-silicon)及其組合。而於本實施例中，直通矽晶栓塞330係設置於晶粒300的中央區域。
接著，請參考第5B圖，係將一個如第5A圖之具有複數個直通矽晶栓塞330之第二晶粒300a與第2C圖之第一晶粒100a接合，以形成第一堆疊結構，其中，此第一堆疊結構是將第二晶粒300a的複數個直通矽晶栓塞330之第二端333與第一晶粒100a的第一凸塊20a分別對應電性連接在一起；而在一較佳實施例中，同樣地，可以在第一晶粒100a與第二晶粒300a之間形成一密封層140，以使得第一堆疊結構更穩固。密封層140可在第二晶粒300a接合第一晶粒100a之前，先佈設於第一晶粒100a之主動面101上，或於整個多晶粒堆疊結構完成後再進行密封層填充製程，而此密封層140充填製程與其材料與前述密封層80相同，故不再重複說明。
再接著，請參考第5C圖，係於第二晶粒300a的複數個直通矽晶栓塞330的第一端331上形成複數個第二凸塊50a，此第二凸塊50a之型式及材料與前述凸塊20相同。再接著，將第5C圖中的第二晶粒300a上的第二凸塊50a藉由複數條金屬導線30電性連接至基板200上的接點240，如第5D圖所示。而形成此金屬導線30之方式，可以選擇逆打線製程來執行。
此外，以同樣的製程方式，另外將一個如第5A圖之第三晶粒300b與一個如第2B圖之第四晶粒100b電性連接在一起，以形成一個第二堆疊結構，其中，此第二堆疊結構是將第三晶粒300b的 複數個直通矽晶栓塞330之第二端333與第四晶粒100b的第四凸塊20b分別對應電性連接在一起；同樣地，可以在第三晶粒300b與第四晶粒100b之間形成一密封層140，以得到穩固的第二堆疊結構。隨後，於第二堆疊結構之第三晶粒300b的複數個直通矽晶栓塞330的第一端331上形成複數個第二凸塊50b。接著，再將此第二堆疊結構以覆晶方式，將第二堆疊結構之第三晶粒300b上的第三凸塊50b分別對應連接至第一堆疊結構之第二晶粒300a的第二凸塊50a以及金屬導線30，以形成一個由四個晶粒100a、100b、300a、300b所堆疊而成的多晶粒堆疊結構，如第5E圖所示。此外，本實施例還可以在第三晶粒300b形成第三凸塊50b後，先將第三晶粒300b與第二晶粒300a電性連接，使第三凸塊50b分別對應連接至金屬導線30以及第二晶粒300a的第二凸塊50a；接著，再將第四晶粒100b以覆晶方式接合第三晶粒300b，使第四晶粒100b上的第四凸塊20b分別對應連接第三晶粒300b的直通矽晶栓塞330之第二端333，以形成如第5E圖之多晶粒堆疊結構。
同樣地，也可以選擇地進行一個高分子材料之充填製程，以形成密封層80於第一堆疊結構與第二堆疊結構之間的空間以及形成密封層140於第一晶粒100a與第二晶粒300a之間和第三晶粒300b與第四晶粒100b之間，以穩固此多晶粒堆疊結構。接著，再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、第一晶粒100a、第二晶粒300a、第三晶粒300b、第四晶粒100b及金屬導線30。由於，密封層80/140充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可在基板200之下表面220上的複數個外部接點230上配置錫球(未顯示於第5E圖中)，以作為對外之電性連接元件。很明顯地，當此堆疊結構中的每一個晶粒100、300均為一個1Gb DRAM時，則此多晶粒堆 疊封裝結構即成為一個4Gb DRAM之產品，可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
接著，請參考第5F圖所示，係於基板200之結構中嵌埋入一個控制晶粒500，並將控制晶粒500與基板200形成電性連接，使控制晶粒500之主動面透過基板200內之線路與配置於基板200下表面220的複數個外部接點230電性連接；此外，控制晶粒500嵌埋之方式可以是在多層電路板形成過程中，即將此控制晶粒500配置於基板200中，其係利用習知技術形成此嵌埋結構，故不再詳細說明。很明顯地，第5F圖與第5E圖之差異在：於第5E圖中進一步配置一嵌埋入基板200中的控制晶粒500，其餘形成第一晶粒100a、第二晶粒300a、第三晶粒300b及第四晶粒100b之連接過程均與第5B圖至第5E圖相同，因此不再贅述之。
再接著，請參考第6圖，係本發明之多晶粒堆疊結構形成於具有凹槽之基板之實施例的剖面示意圖。由第6圖所示，其多晶粒堆疊結構與第5E圖中的多晶粒堆疊結構相同，其中差異在於基板200。在本實施例中的基板200與第4圖中的基板200結構相同，其上表面210上定義有一晶粒設置區(圖未顯示)並配置有複數個接點240，晶粒設置區內係形成一凹槽250，這些接點240係位於晶粒設置區之外，其中，此凹槽250的長度及寬度大於晶粒100的長度及寬度。當如第5C圖中的第一堆疊結構形成於基板200之凹槽250之後，係藉由例如逆打線製程所形成之複數條金屬導線30來將第二晶粒300a上的第二凸塊50a電性連接至基板200上的接點240。很明顯地，當基板200之凹槽250經過適當的設計，例如：將凹槽250之深度設計成與包含晶粒100a及300a的第一堆疊結構的厚度相近，因此，當第一堆疊結構以第一晶粒100a之背 面103並藉由黏著層120黏貼於基板200之凹槽250內後，基板200上表面210上的接點240與第二晶粒300a上的第二凸塊50a有相近的高度，故使得複數條金屬導線30可以以最小的弧度及最短的長度來將基板200上的接點240與第二晶粒300a上的第二凸塊50a電性連接在一起，故可以使得此多晶粒堆疊結構具有最佳之電氣特性。由於多晶粒堆疊結構形成之過程與前述實施例之過程相同，故不再重複說明。同樣地，本實施例也可以選擇地進行一個高分子材料之充填製程，以形成密封層80/140於每一個晶粒100a、300a、300b、100b之間的空間，以穩固堆疊結構。同時，也可以再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、第一晶粒100a、第二晶粒300a、第三晶粒300b、第四晶粒100b及金屬導線30，而第一晶粒100a及第二晶粒300a與凹槽250間的空隙亦同時被封膠體90填滿。由於，密封層充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可以在基板200之下表面220上的複數個外部接點230上配置錫球260，以作為對外之電性連接元件。
很明顯地，在第6圖的實施例中，可以使用最佳的金屬導線30長度來連接晶粒300a/300b上的凸塊50a/50b至基板200上的接點240，使得本實施例具有較佳的電氣特性及可靠度。再者，經由基板200上的凹槽250的配置，使得整個多晶粒堆疊封裝結構的高度可以明顯地降低。更有進者，本實施例也可以類似第3圖，於金屬導線30連接第二晶粒300a上的第二凸塊50a後，另形成結線凸塊40於每一條金屬導線30與第二凸塊50a的連接點上，用以增強金屬導線30的接合強度並提供後續覆晶接合緩衝效果。如此，可以使得多晶粒堆疊結構在電極處具有較佳的熱膨脹係數的匹配，可以增加封裝體的可靠度。
再接著，請參考第7圖，係本發明之多晶粒堆疊封裝結構之再一實施例之剖面示意圖。如第7圖所示，首先，係將三個第5A圖之具有複數個直通矽晶栓塞330之晶粒300垂直堆疊成一體，其堆疊方式係在第5A圖之晶粒300之每一個直通矽晶栓塞330之第一端331上分別對應地形成一個凸塊50；然後再將一個晶粒300之凸塊50與另一個晶粒300之直通矽晶栓塞330第二端333分別對應電性連接，之後再將此三個晶粒300之堆疊結構與第2C圖之晶粒100形成電性連接，以形成第一堆疊結構，其中，此第一堆疊結構是將晶粒300上的直通矽晶栓塞330之第二端333與晶粒100的凸塊20對應連接在一起。再接著，將第一堆疊結構中位於最上面的晶粒300上的凸塊50藉由複數條金屬導線30電性連接至基板200上的接點240，而形成此金屬導線30之方式，可以選擇逆打線製程來執行。
此外，以同樣的製程方式，另外將三個第5A圖之具有複數個直通矽晶栓塞330之晶粒300垂直堆疊成一體，然後再將此三個晶粒300之堆疊結構與第2B圖之晶粒100電性連接，以形成一個第二堆疊結構；由於其形成此第二堆疊結構過程與形成第一堆疊結構之過程是相同的，故不再重複說明。接著，再將此第二堆疊結構以覆晶方式，將第二堆疊結構上所曝露的複數個凸塊50分別對應連接至金屬導線30以及第一堆疊結構上所曝露的複數個凸塊50，以形成一個由八個晶粒100/300所堆疊而成的多晶粒堆疊結構，如第7圖所示。同樣地，也可以選擇地進行一個高分子材料之充填製程，以形成密封層80/140於第一堆疊結構與第二堆疊結構之間的空間以及每個晶粒100/300之間，以穩固此多晶粒堆疊結構。接著，再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、八個晶粒100/300及金屬導線30。由於，密封層充填製程及 封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可以在基板200之下表面220上的複數個外部接點230上配置錫球(未顯示於第7圖中)，以作為對外之電性連接元件。很明顯地，當此堆疊結構中的每一個晶粒100/300均為1Gb DRAM時，則此多晶粒堆疊封裝結構即成為一個8Gb DRAM之產品，可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
此外，要特別說明的是當前述之實施例中的凸塊20、50使用一種軟性金屬作為材料時，例如金，即可藉由軟性金屬之低硬度、高韌性及良好的順應共平面特性，使得在進行多晶粒垂直堆疊時，可以在電極(即凸塊)的接合界面上去吸收因為金屬電極材料間熱膨脹係數不匹配，而在橫向與縱向所產生的變形，也可以有效去克服金屬電極材料間粗糙度的問題，故可有效地增加多晶粒垂直堆疊之製程及產品的可靠度。
接著，請參考第8A圖，係本發明之多晶粒堆疊封裝結構形成系統級封裝結構之剖面示意圖。首先，如第8A圖所示，其基板200之結構與第4圖中的基板200相同，其上表面210上定義有一晶粒設置區(圖未顯示)並配置有複數個接點240，晶粒設置區內係形成一凹槽250，而這些接點240係位於晶粒設置區之外，其中，此凹槽250的長度及寬度大於晶粒100的長度及寬度。在本實施例中，係先將一個控制晶粒500設置於凹槽250內，並將控制晶粒500與基板200形成電性連接，控制晶粒500與基板200電性連接的方式可以用覆晶方式，將控制晶粒500之主動面面對基板200並與基板200設置於凹槽250底部的複數個端點(未顯示於圖中)電性連接。也可以選擇將控制晶粒500以背面黏貼於凹槽250內，並以打線方式形成導線來電性連接控制晶粒500主動面上的 銲墊至基板200設置於凹槽250底部的端點(未顯示於圖中)，然後，在控制晶粒500主動面上鋪設FOW(Film-over-wire)薄膜以包覆導線(未顯示於圖中)。接著，將一個第2B圖之第一晶粒100a，以其背面103並藉由黏著層120黏貼於控制晶粒500之背面或直接以其背面103黏貼於FOW薄膜上。接著，可以選擇逆打線製程，以複數條金屬導線30來將第一晶粒100a上的凸塊20a電性連接至基板200上的接點240。很明顯地，當基板200之凹槽250經過適當的設計，例如：當第一晶粒100a黏貼於控制晶粒500之背面或FOW薄膜上後，基板200上表面210上的接點240與第一晶粒100a上的凸塊20a有相近的高度，故使得複數條金屬導線30可以以最小的弧度及最短的長度來將基板200上的接點240與第一晶粒100a上的凸塊20a電性連接在一起，故可以使得此多晶粒堆疊結構具有最佳之電氣特性。再接著，將一個與第2B圖相同的第二晶粒100b，以覆晶方式將其上之凸塊20b對應連接至金屬導線30以及固定在凹槽250中的第一晶粒100a上的凸塊20a，以形成一個多晶粒堆疊結構。同樣地，也可以選擇地進行一個高分子材料之充填製程，以形成密封層80於兩個晶粒100a、100b之間，以穩固堆疊結構。接著，再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、第一晶粒100a、第二晶粒100b及金屬導線30，而控制晶粒500及第一晶粒100a與凹槽250間的空隙亦同時被封膠體90填滿。由於，密封層充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可以在基板200之下表面220上的複數個外部接點230上配置錫球260，以作為對外之電性連接元件。很明顯地，藉由控制晶粒500的配置，使得本實施例之多晶粒堆疊封裝結構形成一個系統級封裝(SiP)，而當每一個晶粒100均為一個1Gb DRAM時，本實施例的多晶粒堆疊 封裝結構即可藉由控制晶粒500來控制2Gb DRAM之存取，以達到較大容量及較高操作速度與較大頻寬之特性。故可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
再接著，請參考第8B圖，本發明之多晶粒堆疊封裝結構形成系統級封裝結構之另一實施例之剖面示意圖。很明顯地，第8B圖與第8A圖間的差異僅在於：第8B圖係在控制晶粒500設置於基板200之凹槽250內，並與基板200形成電性連接後，再與四個堆疊成一體的晶粒100/300固接成一體；其中控制晶粒500與基板200電性連接的方式以及與晶粒100固接之方式與第8A圖相同；此外，堆疊成一體的四個晶粒100/300之堆疊過程及結構與第5E圖相同，故不再贅述。很明顯地，藉由控制晶粒500的配置，使得本實施例之多晶粒堆疊封裝結構形成一個系統級封裝(SiP)，而當每一個晶粒均為一個1Gb DRAM時，本實施例的多晶粒堆疊封裝結構即可藉由控制晶粒500來控制4Gb DRAM之存取，以達到較大容量及較高操作速度與較大頻寬之特性。故可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
再接著，請參考第8C圖，本發明之多晶粒堆疊封裝結構形成系統級封裝結構之另一實施例之剖面示意圖。第8C圖與第8A圖相同地，於基板200之晶粒設置區內係形成一凹槽250，並且將一個控制晶粒500設置於凹槽250內，且控制晶粒500與基板200形成電性連接，控制晶粒500與基板200電性連接的方式與前述第8A圖相同；然後，先使用一充填材料部份充填於凹槽250中，以形成一覆蓋層280將控制晶粒500覆蓋並充填控制晶粒500與凹槽250間的空隙。之後，再於覆蓋層280上形成如第8A圖中的 多晶粒堆疊結構。由於多晶粒堆疊結構形成之過程與前述實施例之過程相同，故不再重複說明。
再接著，請參考第8D圖，本發明之多晶粒堆疊封裝結構形成系統級封裝結構之再一實施例之剖面示意圖。很明顯地，第8D圖與第8C圖的結構相同，控制晶粒500設置於凹槽250內；然後，使用一充填材料部份充填於凹槽250中，以形成一覆蓋層280將控制晶粒500覆蓋並充填控制晶粒500與凹槽250間的空隙；而後，再於覆蓋層280上形成與第8B圖相同之四個晶粒100/300之堆疊結構。由於控制晶粒500與基板200電性連接的方式與前述第8A圖相同，且多晶粒堆疊結構形成之過程與前述實施例之過程亦相同，故不再重覆說明。
很明顯地，藉由控制晶粒500的配置，使得本實施例之多晶粒堆疊封裝結構形成一個系統級封裝(SiP)，而當每一個晶粒均為一個1Gb DRAM時，本實施例的多晶粒堆疊封裝結構即可藉由控制晶粒500來控制2Gb DRAM(如第8C圖的結構)或是4Gb DRAM(第8D圖的結構)之存取，以達到較大容量及較高操作速度與較大頻寬之特性。故可以將其應用在可攜式電子產品中，例如：筆記型電腦、3G手機、個人數位助理以及遊戲機。
再接著，請參考第9圖，本發明之多晶粒堆疊封裝結構形成系統級封裝結構之再一實施例之剖面示意圖。如第9圖所示，其係在第5E圖之多晶粒堆疊結構之最上層晶粒100(第四晶粒100b)之背面103上，再黏貼上一個控制晶粒500，然後，再以另一打線製程將控制晶粒500上的複數個銲墊510電性連接至基板200之上表面210的接點240。因此，本實施例也係形成一種系統級封裝，故可藉由控制晶粒500來控制2Gb DRAM之存取，以達到較大容量及較高操作速度與較大頻寬之特性。
接著，請參考第10A圖至第10D圖，係本發明之具有複數個直通矽晶栓塞之多晶粒堆疊結構之再一實施例之剖面示意圖。首先，如第10A圖所示，為本發明之一具有複數個直通矽晶栓塞之晶粒400的剖面示意圖。晶粒400具有主動面401以及相對於主動面401的背面403，並且於晶粒400上形成複數個貫穿主動面401及背面403的垂直貫穿孔，於每一垂直貫穿孔中進一步形成直通矽晶栓塞450以使主動面401與背面403間相互電性連接，而形成貫穿孔的方式及直通矽晶栓塞450之材料與第5A圖相同。在本實施例中，此複數個直通矽晶栓塞450於主動面401形成第一端451並於背面403形成第二端453，而於部份這些直通矽晶栓塞450的第二端453上形成凸出晶粒400背面403的凸塊457，而部份這些直通矽晶栓塞450的第一端451也形成凸出晶粒400主動面401的凸塊455。而這些凸塊455及凸塊457可以為直通矽晶栓塞450之一部分，即與直通矽晶栓塞450相同材料一體成型，也可以另外以其他導電材料分別形成於直通矽晶栓塞450之第一端451及第二端453上。然後，將複數個與第10A圖相同結構的晶粒400進行垂直堆疊，以形成一堆疊結構400A，如第10B圖所示。而第10B圖之堆疊方式，係將每一個上層晶粒400之複數個直通矽晶栓塞450第二端453上的凸塊457與下層晶粒400之複數個直通矽晶栓塞450第一端451上的凸塊455分別對應地電性連接在一起。在本實施例中是將四個晶粒400堆疊形成一多晶粒之堆疊結構400A。此外，在另一實施例中，晶粒400之複數個直通矽晶栓塞450的第一端451上可以不形成凸塊455；因此，在此實施例中，第10B圖之堆疊方式，則是將每一個上層晶粒400之複數個直通矽晶栓塞450第二端453上的凸塊457直接與下層晶粒400之複數個直通矽晶栓塞450之第一端451分別對應連接。
接著，將第10B圖之堆疊結構400A與另一固接於基板200之主動面210上的晶粒600電性連接，如第10C圖所示；其中，晶粒600具有一主動面及相對之一背面，並且以其背面固接於基板200之晶粒設置區(圖未顯示)內，複數個銲墊610配置於晶粒600主動面之週邊區域上，且每一銲墊610上形成凸塊70；然後藉由金屬導線30將形成在銲墊610上的凸塊70與基板200之主動面210上的複數個接點240電性連接；接著，將堆疊結構400A與晶粒600形成電性連接，其電性連接方式是將堆疊結構400A的最下層晶粒400的直通矽晶栓塞450第二端453上的凸塊457分別對應連接金屬導線30及晶粒600上之凸塊70，即可形成第10C圖之多晶粒之堆疊結構。要特別說明的是在本實施例中，晶粒400中位於中間區域之複數個直通矽晶栓塞450係可透過晶粒400內部之線路(圖未顯示)電性連接至位於週邊區域之直通矽晶栓塞450，接著再藉由形成於週邊區域之直通矽晶栓塞450上的凸塊457對應連接金屬導線30及晶粒600上之凸塊70。在本實施例中，晶粒600可以是與晶粒100/300具有相同功能之晶粒，例如：DRAM；而晶粒600也可以是與晶粒100/300具有不相同功能之晶粒，例如：快閃記載體(Flash Memory)或是一個無功能之虛晶粒(dummy die)，另外晶粒600也可以是控制晶片或其他特殊用途晶片(ASIC)，如數位訊號處理器(DSP)、中央處理器(CPU)、微處理機控制單元(MCU)等，對此，本發明並不加以限制。
接著，本實施例也可以選擇地進行一個高分子材料之充填製程，以形成密封層140於堆疊結構400A的晶粒400之間，以及密封層80於堆疊結構400A與晶粒600之間，以穩固此多晶粒之堆疊結構。接著，也可以再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、堆疊結構400A、晶粒600與金屬導線30。由於， 密封層充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，還可以在基板200之下表面220上的複數個外部接點230上配置錫球260，以作為對外之電性連接元件，如第10C圖所示。
此外，本發明還可以在第10C圖之基板200中，進一步嵌入一個控制晶粒500，如第10D圖所示，其中將控制晶粒500形成於基板200中的方式與第2I圖相同，故不再重覆說明。
請再參考第11圖，係本發明之具有複數個直通矽晶栓塞之多晶粒堆疊結構之再一實施例的剖面示意圖。如第11圖所示，其與第10C圖兩者在堆疊結構400A、晶粒600與複數條金屬導線30的結合相同，而其間之差異在於基板200。在本實施例中的基板200與第4圖中的基板200結構相同，其上表面210上定義有一晶粒設置區(圖未顯示)並配置有複數個接點240，晶粒設置區內形成一凹槽250，而這些接點240係位於晶粒設置區之外，其中，此凹槽250的長度及寬度大於晶粒600的長度及寬度。很明顯地，當第11圖中的晶粒600以其背面並藉由黏著層120固接於基板200之凹槽250中之後，係藉由例如逆打線製程所形成之複數條金屬導線30來將晶粒600之銲墊610上的凸塊70電性連接至基板200上的接點240。很明顯地，當基板200之凹槽250經過適當的設計，例如：將凹槽250之深度設計成與晶粒600的厚度相近，因此，當晶粒600固接於基板200之凹槽250後，基板200上表面210上的接點240與晶粒600上的凸塊70有相近的高度，故使得複數條金屬導線30可以以最小的弧度及最短的長度來將基板200上的接點240與晶粒600上的凸塊70電性連接在一起，故可以使得此多晶粒堆疊結構具有最佳之電氣特性。由於多晶粒堆疊結構形成之過程與前述實施例之過程相同，故不再重複說明。同樣地，本 實施例也可以選擇地進行一個高分子材料之充填製程，以形成密封層140、80於堆疊結構400A的晶粒400之間以及堆疊結構400A與晶粒600之間，以穩固多晶粒之堆疊結構。接著，也可以再進行一封膠製程，以形成一封膠體90用以覆蓋基板200、堆疊結構400A、晶粒600及金屬導線30，而晶粒600與凹槽250間的空隙亦同時被封膠體90填滿。由於，密封層充填製程及封膠製程及其材料均與前述之實施例相同，故不再重複說明。最後，再將基板200之下表面220上的複數個外部接點230上配置錫球260，以作為對外之電性連接元件。
再者，請參考第12圖，係本發明之多晶粒堆疊封裝結構形成系統級封裝結構之再一實施例之剖面示意圖。如第12圖所示，其晶粒堆疊結構與第11圖相同，兩者間之差異在於，本實施例中進一步設置一個控制晶粒500於基板200之凹槽250中，且此控制晶粒500是與基板200形成電性連接。此控制晶粒500與基板200電性連接的方式可以以覆晶方式將控制晶粒500之主動面與配置於基板200之凹槽250底部的複數個端點(未顯示於圖中)電性連接，或者將控制晶粒500以背面黏貼於凹槽250內，並以打線方式形成導線來電性連接控制晶粒500主動面上的銲墊至基板200設置於凹槽250底部的端點(未顯示於圖中)；然後，可以選擇性地使用一充填材料部份充填於凹槽250中，以形成一覆蓋層280將控制晶粒500覆蓋並充填控制晶粒500與凹槽250間的空隙；接著，再於覆蓋層280上形成如第12圖之多晶粒堆疊封裝結構，以形成一個系統級封裝結構。
以上所述僅為本發明之具體實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。
10‧‧‧晶圓
100、100a、100b‧‧‧晶粒
101‧‧‧晶粒主動面
103‧‧‧晶粒背面
110‧‧‧銲墊
120‧‧‧黏著層
140‧‧‧密封層
20、20a、20b‧‧‧凸塊
200‧‧‧基板
210‧‧‧基板上表面
220‧‧‧基板下表面
230‧‧‧基板下表面之外部接點
240‧‧‧基板上表面接點
250‧‧‧基板上凹槽
260‧‧‧錫球
280‧‧‧覆蓋層
30‧‧‧金屬導線
300、300a、300b‧‧‧具有直通矽晶栓塞的晶粒
301‧‧‧具有直通矽晶栓塞的晶粒之主動面
303‧‧‧具有直通矽晶栓塞的晶粒之背面
330‧‧‧直通矽晶栓塞
331‧‧‧直通矽晶栓塞之第一端
333‧‧‧直通矽晶栓塞之第二端
40‧‧‧結線凸塊
400A‧‧‧堆疊結構
400‧‧‧具有直通矽晶栓塞的晶粒
401‧‧‧具有直通矽晶栓塞的晶粒之主動面
403‧‧‧具有直通矽晶栓塞的晶粒之背面
450‧‧‧直通矽晶栓塞
451‧‧‧直通矽晶栓塞之第一端
453‧‧‧直通矽晶栓塞之第二端
455、457‧‧‧凸塊
50、50a、50b‧‧‧凸塊
80‧‧‧密封層
90‧‧‧封膠體
500‧‧‧控制晶粒
510‧‧‧控制晶粒之銲墊
600‧‧‧晶粒
610‧‧‧銲墊
70‧‧‧凸塊
第1圖 係一完成前段製程之晶圓示意圖；第2A圖至第2I圖 係本發明之多晶粒堆疊封裝結構之一實施例之剖面示意圖；第3圖 係本發明之多晶粒堆疊封裝結構之另一實施例之剖面示意圖；第4圖 係本發明之多晶粒堆疊封裝結構之再一實施例之剖面示意圖；第5A圖至第5F圖 係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構之一實施例之剖面示意圖；第6圖 係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構之另一實施例的剖面示意圖；第7圖 係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構之再一實施例之剖面示意圖；第8A圖及第8D圖 本發明之多晶粒堆疊封裝結構形成系統級封裝結構之剖面示意圖；第9圖 本發明之多晶粒堆疊封裝結構形成系統級封裝結構之再一實施例之剖面示意圖；第10A圖至第10D圖，係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構之再一實施例之剖面示意圖；第11圖 係本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構之又一實施例之剖面示意圖；第12圖 本發明之具有直通矽晶栓塞之多晶粒堆疊封裝結構形成系統級封裝結構之再一實施例之剖面示意圖；及第13A圖及第13B圖 係顯示多晶粒堆疊封裝結構之先前技術之剖面示意圖。
100a、100b‧‧‧晶粒
110‧‧‧銲墊
120‧‧‧黏著層
80‧‧‧密封層
20a、20b‧‧‧凸塊
200‧‧‧基板
210‧‧‧基板上表面
220‧‧‧基板下表面
230‧‧‧基板下表面之外部接點
240‧‧‧基板上表面接點
90‧‧‧封膠體
30‧‧‧金屬導線

Claims (26)

  1. 一種多晶粒堆疊封裝結構，包括：一基板，具有一上表面及一下表面，該上表面上定義一晶粒設置區及配置有複數個接點，該等接點位於該晶粒設置區之外；一第一晶粒，具有一主動面及相對該主動面之一背面，該第一晶粒係以該背面設置於該晶粒設置區，該主動面上配置有複數個第一銲墊且該等第一銲墊上形成一第一凸塊；複數條金屬導線，用以連接該等第一凸塊至該等接點；一第二晶粒，具有一主動面及相對該主動面之一背面，該主動面上配置有複數個第二銲墊，該等第二銲墊上形成一第二凸塊，該第二晶粒係以該主動面面對該第一晶粒之該主動面接合該第一晶粒，使該等第二凸塊分別對應連接該等金屬導線及該等第一凸塊；至少一第三凸塊，配置於各該等金屬導線與各該等第二凸塊之間；及一封膠體，用以覆蓋該基板、該第一晶粒、該第二晶粒及該等金屬導線。
  2. 如申請專利範圍第1項所述之封裝結構，其中該等第一銲墊係位於該第一晶粒之該主動面之中央區域及該等第二銲墊係位於該第二晶粒之該主動面之中央區域。
  3. 如申請專利範圍第1項所述之封裝結構，其進一步包含一控制晶粒，該控制晶粒係嵌埋於該基板之中並與該基板形成電性連接。
  4. 如申請專利範圍第1項所述之封裝結構，其中該等第一凸塊、第二凸塊及第三凸塊係為電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊。
  5. 如申請專利範圍第1項所述之封裝結構，其中該第一晶粒與該 第二晶粒之間形成有一密封層。
  6. 一種多晶粒堆疊封裝結構，包括：一基板，具有一上表面及一下表面，該上表面上定義一晶粒設置區及配置有複數個接點，該等接點位於該晶粒設置區之外；一第一晶粒，具有一主動面及相對該主動面之一背面，該第一晶粒係以該背面設置於該晶粒設置區，該主動面上配置有複數個第一銲墊且該等第一銲墊上形成一第一凸塊；一第二晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，該等直通矽晶栓塞係貫穿該第二晶粒以使該主動面與該背面間相互電性連接，該主動面上形成複數個第二凸塊分別連接該等直通矽晶栓塞，其中該第二晶粒係以該背面面對該第一晶粒之該主動面接合該第一晶粒，使該等直通矽晶栓塞分別對應連接該等第一凸塊；複數條金屬導線，用以連接該等第二凸塊至該等接點；一第三晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，該等直通矽晶栓塞係貫穿該第三晶粒以使該主動面與該背面間相互電性連接，該主動面上形成複數個第三凸塊分別連接該等直通矽晶栓塞，其中該第三晶粒係以該主動面面對該第二晶粒之該主動面接合該第二晶粒，使該等第三凸塊分別對應連接該等金屬導線及該等第二凸塊；至少一第五凸塊，係配置於該等金屬導線與該等第三凸塊之間；一第四晶粒，具有一主動面及相對該主動面之一背面，該主動面上配置有複數個第二銲墊，且該等第二銲墊上形成一第四凸塊，該第四晶粒係以該主動面面對該第三晶粒之該背面接合該第三晶粒，使該等第四凸塊分別對應連接該第三晶粒之該等直通矽晶栓塞；及 一封膠體，用以覆蓋該基板、該第一晶粒、該第二晶粒、該第三晶粒、該第四晶粒及該等金屬導線。
  7. 如申請專利範圍第6項所述之封裝結構，其中該等第一銲墊係位於該第一晶粒之該主動面之中央區域及該等第二銲墊係位於該第四晶粒之該主動面之中央區域，該等直通矽晶栓塞係分別設置於該第二晶粒及該第三晶粒的中央區域。
  8. 如申請專利範圍第6項所述之封裝結構，其進一步包含一控制晶粒，該控制晶粒係嵌埋於該基板之中並與該基板形成電性連接。
  9. 如申請專利範圍第6項所述之封裝結構，其中該等凸塊係為電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊。
  10. 如申請專利範圍第6項所述之封裝結構，其中該等晶粒之間分別形成有一密封層。
  11. 一種多晶粒堆疊封裝結構，包括：一基板，具有一上表面及一下表面，該上表面上定義一晶粒設置區及配置有複數個接點，該晶粒設置區內形成一凹槽，該等接點位於該晶粒設置區之外；一第一晶粒，具有一主動面及相對該主動面之一背面，該第一晶粒係以該背面設置於該凹槽中，該主動面上配置有複數個第一銲墊且該等第一銲墊上形成一第一凸塊；複數條金屬導線，用以連接該等第一凸塊至該等接點；一第二晶粒，具有一主動面及相對該主動面之一背面，該主動面上配置有複數個第二銲墊，該等第二銲墊上形成一第二凸塊，該第二晶粒係以該主動面面對該第一晶粒之該主動面接合該第一晶粒，使該等第二凸塊分別對應連接該等金屬導線及該 等第一凸塊；至少一第三凸塊，配置於各該等金屬導線與各該等第二凸塊之間；及一封膠體，用以覆蓋該基板、該第一晶粒、該第二晶粒及該等金屬導線。
  12. 如申請專利範圍第11項所述之封裝結構，其中該等第一銲墊係位於該第一晶粒之該主動面之中央區域，及該等第二銲墊係位於該第二晶粒之該主動面之中央區域。
  13. 一種多晶粒堆疊封裝結構，包括：一基板，具有一上表面及一下表面，該上表面上定義一晶粒設置區及配置有複數個接點，該晶粒設置區內形成一凹槽，該等第一端接點位於該晶粒設置區之外；一第一晶粒，具有一主動面及相對該主動面之一背面，該第一晶粒係以該背面設置於該凹槽中，該主動面上配置有複數個第一銲墊且該等第一銲墊上形成一第一凸塊；一第二晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，該等直通矽晶栓塞係貫穿該第二晶粒以使該主動面與該背面間相互電性連接，該主動面上形成複數個第二凸塊分別連接該等直通矽晶栓塞，其中該第二晶粒係以該背面面對該第一晶粒之該主動面接合該第一晶粒，使該等直通矽晶栓塞分別對應連接該等第一凸塊；複數條金屬導線，用以連接該等第二凸塊至該等接點；一第三晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，該等直通矽晶栓塞係貫穿該第三晶粒以使該主動面與該背面間相互電性連接，該主動面上形成複數個第三凸塊分別連接該等直通矽晶栓塞，其中該第三晶粒係以該主動 面面對該第二晶粒之該主動面接合該第二晶粒，使該等第三凸塊分別對應連接該等金屬導線及該等第二凸塊；至少一第五凸塊，係配置於該等金屬導線與該等第三凸塊之間；一第四晶粒，具有一主動面及相對該主動面之一背面，該主動面上配置有複數個第二銲墊，該等第二銲墊上形成一第四凸塊，該第四晶粒係以該主動面面對該第三晶粒之該背面接合該第三晶粒，使該等第四凸塊分別對應連接該第三晶粒之該等直通矽晶栓塞；及一封膠體，用以覆蓋該基板、該第一晶粒、該第二晶粒、該第三晶粒、該第四晶粒及該等金屬導線。
  14. 如申請專利範圍第13項所述之封裝結構，其中該等第一銲墊係位於該第一晶粒之該主動面之中央區域，該等第二銲墊係位於該第四晶粒之該主動面之中央區域，以及該等直通矽晶栓塞係分別設置於該第二晶粒及該第三晶粒的中央區域。
  15. 如申請專利範圍第11或13項所述之封裝結構，其更進一步包含一控制晶粒設置於該凹槽內並位於該第一晶粒與該基板之間，該第一晶粒係以該背面直接固接於該控制晶粒上，該控制晶粒係與該基板電性連接。
  16. 如申請專利範圍第11或13項所述之封裝結構，其更進一步包含一控制晶粒設置於該凹槽內並位於該第一晶粒與該基板之間，該控制晶粒被一覆蓋層所包覆，該第一晶粒係固接於該覆蓋層上，該控制晶粒係與該基板電性連接。
  17. 如申請專利範圍第11或13項所述之封裝結構，其中該等凸塊係為電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊。
  18. 如申請專利範圍第11或13項所述之封裝結構，其中該等晶粒 之間分別形成有一密封層。
  19. 一種多晶粒堆疊封裝結構，包括：一基板，具有一上表面及一下表面，該上表面上定義一晶粒設置區及配置有複數個接點，該等接點位於該晶粒設置區之外；一第一晶粒，具有一主動面及相對該主動面之一背面，該第一晶粒係以該背面設置於該晶粒設置區，該主動面之週邊區域上配置有複數個第一銲墊且該等第一銲墊上形成一凸塊；複數條金屬導線，用以連接該第一晶粒之該等凸塊至該等接點；一第二晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，每一該直通矽晶栓塞係貫穿該第二晶粒以使該主動面與該背面間相互電性連接，且每一該直通矽晶栓塞於該主動面形成一第一端並於該背面形成一第二端，而於至少部份該等直通矽晶栓塞之第二端上分別形成一凸塊，其中該第二晶粒係以該背面面對該第一晶粒之該主動面接合該第一晶粒，使該第二晶粒之該等凸塊分別對應連接該等金屬導線及該第一晶粒之該等凸塊；一第三晶粒，具有一主動面及相對該主動面之一背面以及複數個直通矽晶栓塞，每一該直通矽晶栓塞係貫穿該第三晶粒以使該主動面與該背面間相互電性連接，且每一該直通矽晶栓塞於該主動面形成一第一端並於該背面形成一第二端，而於至少部份該等直通矽晶栓塞之第二端上分別形成一凸塊，其中該第三晶粒係以該背面面對該第二晶粒之該主動面接合該第二晶粒，使該第三晶粒之該等凸塊分別對應連接該第二晶粒之該等直通矽晶栓塞之第一端；至少一凸塊，配置於各該等金屬導線與該第二晶粒之各該等凸塊之間；及 一封膠體，用以覆蓋該基板、該第一晶粒、該第二晶粒、該第三晶粒及該等金屬導線。
  20. 如申請專利範圍第19項所述之封裝結構，其中該第二晶粒之該等直通矽晶栓塞之第一端上分別形成一凸塊，其中該第三晶粒之該等凸塊係分別電性連接該第二晶粒之該等直通矽晶栓塞之第一端上的該等凸塊。
  21. 如申請專利範圍第20項所述之封裝結構，其中該第二晶粒之該等直通矽晶栓塞之第一端及第二端上之該等凸塊以及該第三晶粒之該等凸塊係為該等直通矽晶栓塞之一部分。
  22. 如申請專利範圍第19或20項所述之封裝結構，其中該等凸塊係為電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊。
  23. 如申請專利範圍第19項所述之封裝結構，其中該晶粒設置區內進一步形成一凹槽，該第一晶粒係設置於該凹槽內。
  24. 如申請專利範圍第23項所述之封裝結構，其更進一步包含一控制晶粒設置於該凹槽內並位於該第一晶粒與該基板之間，該第一晶粒係以該背面直接固接於該控制晶粒上，該控制晶粒係與該基板電性連接。
  25. 如申請專利範圍第23項所述之封裝結構，其更進一步包含一控制晶粒設置於該凹槽內並位於該第一晶粒與該基板之間，該控制晶粒被一覆蓋層所包覆，該第一晶粒係固接於該覆蓋層上，該控制晶粒係與該基板電性連接。
  26. 如申請專利範圍第19項所述之封裝結構，其中該等晶粒之間分別形成有一密封層。
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