JP6989426B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6989426B2 JP6989426B2 JP2018055029A JP2018055029A JP6989426B2 JP 6989426 B2 JP6989426 B2 JP 6989426B2 JP 2018055029 A JP2018055029 A JP 2018055029A JP 2018055029 A JP2018055029 A JP 2018055029A JP 6989426 B2 JP6989426 B2 JP 6989426B2
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- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims description 162
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000002346 layers by function Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 28
- 239000010410 layer Substances 0.000 claims description 23
- 238000005304 joining Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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Description
Claims (7)
- ベース部材と、
前記ベース部材の表面と交差する第1方向に交互に積層された第1半導体チップと第2半導体チップとを含む第1積層体と、
前記ベース部材の前記表面に沿った第2方向に、前記第1積層体と並べて配置され、前記第1方向に交互に積層された別の第1半導体チップと別の第2半導体チップとを含む第2積層体と、
を備え、
前記第1積層体は、前記ベース部材に接続された最下層の第1半導体チップを含み、
前記第2積層体は、前記ベース部材に接続された最下層の第2半導体チップを含み、
前記第1半導体チップおよび前記第2半導体チップは、それぞれ、半導体基板と、前記半導体基板上に設けられた機能層と、前記機能層上に設けられた接合パッドと、前記半導体基板の前記機能層とは反対側の裏面側に設けられた接続パッドと、を有し、
前記第1積層体および前記第2積層体は、前記第1半導体チップの機能層と、前記第2半導体チップの機能層と、を向き合わせて接合した第1接合部と、前記第1半導体チップの半導体基板と、前記第2半導体チップの半導体基板と、を向き合わせて接合した第2接合部と、を含み、
前記第1接合部は、前記第1半導体チップの接合パッドと、前記第2半導体チップの接合パッドと、を直接接続した部分を含み、
前記第2接合部は、前記第1半導体チップの接続パッドと、前記第2半導体チップの接続パッドとを、接続部材を介して接続した部分を含む半導体装置。 - ベース部材と、
前記ベース部材の表面と交差する第1方向に交互に積層された第1半導体チップと第2半導体チップとを含む第1積層体と、
前記ベース部材の前記表面に沿った第2方向に、前記第1積層体と並べて配置され、前記第1方向に交互に積層された別の第1半導体チップと別の第2半導体チップとを含む第2積層体と、
前記第1積層体および前記第2積層体に電気的に接続された第3半導体チップと、
を備え、
前記第1積層体は、前記ベース部材に接続された最下層の第1半導体チップを含み、
前記第2積層体は、前記ベース部材に接続された最下層の第2半導体チップを含み、
前記第3半導体チップは、コマンド端子とデータ端子とを有し、
前記第1積層体および前記第2積層体は、それぞれ、前記コマンド端子に接続される第1端子と、前記データ端子に接続される第2端子と、を有し、
前記第1積層体の第1端子と前記第2積層体の第1端子は、前記第2方向に並べて配置され、
前記第1積層体の第2端子と前記第2積層体の第2端子は、前記第2方向に並べて配置される半導体装置。 - 前記第1半導体チップおよび前記第2半導体チップは、それぞれ、半導体基板と、前記半導体基板上に設けられた機能層と、を有し、
前記第1積層体および前記第2積層体は、前記第1半導体チップの機能層と、前記第2半導体チップの機能層と、を向き合わせて接合した第1接合部と、前記第1半導体チップの半導体基板と、前記第2半導体チップの半導体基板と、を向き合わせて接合した第2接合部と、を含む請求項2記載の半導体装置。 - 前記第1半導体チップおよび前記第2半導体チップは、それぞれ、前記機能層上に設けられた接合パッドと、前記半導体基板の前記機能層とは反対側の裏面側に設けられた接続パッドと、を有し、
前記第1接合部は、前記第1半導体チップの接合パッドと、前記第2半導体チップの接合パッドと、を直接接続した部分を含み、
前記第2接合部は、前記第1半導体チップの接続パッドと、前記第2半導体チップの接続パッドとを、接続部材を介して接続した部分を含む請求項3記載の半導体装置。 - 第1機能層と、前記第1機能層と交互に並べて配置された第2機能層と、を含む第1面と、前記第1面とは反対側の第2面を有する第1ウェーハを形成し、
第1機能層と、前記第1機能層と交互に並べて配置された第2機能層と、を含む第1面と、前記第1面とは反対側の第2面を有する第2ウェーハを形成し、
前記第1ウェーハの第1機能層と前記第2ウェーハの第2機能層とが接合され、前記第1ウェーハの第2機能層と前記第2ウェーハの第1機能層とが接合されるように、前記第1ウェーハの第1面と前記第2ウェーハの第1面とを貼り合わせたウェーハ接合体を形成し、
前記ウェーハ接合体を、前記第1ウェーハの第1機能層と前記第1ウェーハの第1機能層に接合された前記第2ウェーハの第2機能層とをそれぞれ含む複数の第1積層チップと、前記第2ウェーハの第1機能層と前記第2ウェーハの第1機能層に接合された前記第1
ウェーハの第2機能層とをそれぞれ含む複数の第2積層チップと、に分割する半導体装置の製造方法。 - 前記第1ウェーハの前記第2面に第1接続パッドを形成し、
前記第2ウェーハの前記第2面に第2接続パッドを形成し、
前記第1積層チップおよび前記第2積層チップは、前記第1ウェーハの一部である第1基板と、前記第2ウェーハの一部である第2基板と、を有し、
前記第1接続パッドと前記第2接続パッドとが対向するように複数の前記第1積層チップを積層し、前記第1接続パッドと前記第2接続パッドとの間を導体により接続して第1積層体を形成し、
前記第1接続パッドと前記第2接続パッドとが対向するように複数の前記第2積層チップを積層し、前記第1接続パッドと前記第2接続パッドとの間を導体により接続して第2積層体を形成する請求項5記載の半導体装置の製造方法。 - 複数の前記第1積層チップを含む第1積層体、および、複数の前記第2積層チップを含む第2積層体をベース部材上に形成する請求項5記載の半導体装置の製造方法。
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CN201821206107.1U CN208767302U (zh) | 2018-03-22 | 2018-07-27 | 半导体装置 |
CN201810847601.4A CN110299364A (zh) | 2018-03-22 | 2018-07-27 | 半导体装置及其制造方法 |
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