TWI476873B - 具有基板穿孔之積體電路結構及形成具有基板穿孔之積體電路結構的方法 - Google Patents
具有基板穿孔之積體電路結構及形成具有基板穿孔之積體電路結構的方法 Download PDFInfo
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- TWI476873B TWI476873B TW102100350A TW102100350A TWI476873B TW I476873 B TWI476873 B TW I476873B TW 102100350 A TW102100350 A TW 102100350A TW 102100350 A TW102100350 A TW 102100350A TW I476873 B TWI476873 B TW I476873B
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- substrate
- epoxy
- integrated circuit
- solder bumps
- flux
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims description 181
- 238000000034 method Methods 0.000 title claims description 11
- 238000010276 construction Methods 0.000 title 2
- 239000004593 Epoxy Substances 0.000 claims description 135
- 230000004907 flux Effects 0.000 claims description 112
- 229910000679 solder Inorganic materials 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 48
- 239000004020 conductor Substances 0.000 claims description 31
- 239000000203 mixture Substances 0.000 claims description 15
- 241000724291 Tobacco streak virus Species 0.000 claims description 7
- 239000011800 void material Substances 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
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Description
本文中所揭示之實施例係針對具有基板穿孔之積體電路結構及形成具有基板穿孔之積體電路結構之方法。
一基板穿孔(TSV)為完全穿過其內具有積體電路之一基板之一垂直電連接。TSV可用於產生3D積體電路封裝,且為其他技術(諸如堆疊封裝)之一改良,此係因為基板穿孔之密度可實質上更高。TSV透過內部佈線而互連垂直對準之電子裝置,其可減小一多晶片積體電路之複雜性及總尺寸。
含有TSV之一些個別積體電路基板具有與基板之一側上之TSV之一端鄰接連接之一接合墊。一柱狀導電結構與另一端鄰接連接且自基板之另一側突出,其中該柱狀導電結構之***最外部分為焊料。可藉由使焊料緊貼另一基板之對準接合墊而將兩個積體電路基板接合在一起。接著,可加熱所得結構以導致焊料流動且與各自接合墊接合。可在使基板彼此接觸之前將助焊劑施加至焊料。助焊劑含有可進行充分加熱以前促進直接鄰接基板保持在一起以使焊料與接合墊接合之黏著
劑。在接合完成之後,可將一介電底部填充材料設置於基板之間以增加支撐及保護。
可在基板之間之介電底部填充材料流動之前藉由清洗而移除剩餘助焊劑。替代地,一些助焊劑在業界被稱為「免清洗助焊劑」,藉此助焊劑剩餘物在介電底部填充材料流動之前有意地餘留於基板之間。無論如何,即使試圖在介電底部填充物之前清除助焊劑剩餘物,通常亦無法移除全部剩餘物。在此等例項中,助焊劑之移除難度已隨直接鄰接電路基板之間之間隔距離變小而增大。
具有介電底部填充材料之結構可經受可導致助焊劑剩餘物氣化之隨後加熱。此可導致結構失效,其包含使焊料結合劑與接合墊分離。此隨直接鄰接基板之間之間隔繼續減小(具體而言,在距離為40微米或更小時)而變得尤其成問題。
10‧‧‧積體電路結構/積體電路封裝
10a‧‧‧積體電路結構
12‧‧‧堆疊
14‧‧‧積體電路基板
16‧‧‧積體電路基板
18‧‧‧積體電路基板
20‧‧‧側
21‧‧‧外表面
22‧‧‧側
24‧‧‧基板穿孔(TSV)
26‧‧‧端
28‧‧‧端
30‧‧‧導電接合墊
31‧‧‧***最外表面
32‧‧‧導電焊料塊
33‧‧‧橫向側表面
34‧‧‧導電材料/導電結構
37‧‧‧預固化環氧助焊劑
38‧‧‧環氧助焊劑
38a‧‧‧環氧助焊劑
40‧‧‧環氧材料
42‧‧‧空隙空間
50‧‧‧托盤/容器
圖1係透過圖2中之線1-1取得之根據本發明之一實施例之一積體電路結構之一圖解截面圖。
圖2係透過圖1中之線2-2取得之圖1之基板之一截面圖。
圖3係圖1之基板之一部分之一放大圖,即,圖1之圓圈3內之部分之一放大圖。
圖4係根據本發明之一實施例之一積體電路結構之一圖解截面圖及圖1中所展示之結構之一替代例。
圖5係準備用在形成根據本發明之一實施例之一積體電路結構之一方法中之分離積體電路基板之一圖解視圖。
圖6係形成根據本發明之一實施例之一積體電路結構之一方法中之一實例性程序步驟之一圖解視圖。
圖7係在由圖6展示之步驟之後之一處理步驟處之圖6之組件之一視圖。
圖8係在由圖6及圖7展示之步驟之後之一處理步驟處之圖5至圖7之組件之若干者之一視圖。
圖9係在由圖8展示之步驟之後之一處理步驟處之圖8之組件之一視圖。
本發明之實施例涵蓋積體電路結構及形成積體電路結構之方法。首先,參考圖1至圖3而描述一積體電路結構10之實例性實施例。根據本發明之積體電路結構包括兩個或兩個以上積體電路基板之一堆疊。實例性結構10包括三個積體電路基板14、16及18之一堆疊12,該等積體電路基板可例如為已在製造完成時被切割為一半導體晶圓之部分之個別晶粒。可使用替代基板,其包含帶有電路之不同製造型基板之組合。基板14、16及18可包含半導體材料(例如矽)、介電質及導電材料。積體電路基板14、16、18可被視為具有相對側20與22,該等側具有各自外表面21。此等表面可實質上平坦或可實質上不平坦及/或彼此平行。
積體電路基板之至少一者包括TSV,其中基板14、16、18之各者在所描繪實例中具有TSV 24。在此項技術中,基板穿孔亦已被稱為矽穿孔。在本發明中,「基板穿孔」(TSV)涵蓋或一般意指矽穿孔,且TSV包含延伸穿過基板材料之導電通孔,無論該材料之任何者是否為矽。TSV 24可包括與本發明無關之任一或多個適合導電材料,其包含(若干)導電摻雜半導體材料。
TSV 24個別地包括相對端26與28。就積體電路基板14及16而言,TSV 24包含與基板側20上之TSV端26鄰接之一導電接合墊30。在一實施例中且如圖所展示,接合墊30相對於基板14、16、18之外表面21而凸起。例如,接合墊30具有一***最外表面31且周圍橫向側表面33(圖3)。一導電焊料塊32與另一TSV端28鄰接且在積體電路基板14及
16之另一側22上***地突出。在一實施例中且如圖所展示,一導電材料34介於個別TSV 24與個別焊料塊32之間。作為一替代實例,焊料塊32可緊貼TSV 24之端28而直接接合(圖中未展示)。在本發明中,當存在所陳述材料或結構相對彼此之至少一些實體觸碰接觸時,一材料或結構「直接緊貼」另一材料或結構。相比而言,前面未加「直接」之「在...上方」、「在...上」及「緊貼...」涵蓋「直接緊貼」以及結構,其中(若干)介入材料或結構導致所陳述材料或結構彼此無實體觸碰接觸。
導電材料34及焊料塊32之各者可同質或非同質,且可為或與本發明無關之任何適合導電材料。無論如何,當使用導電材料34時,導電材料34包含直接緊貼個別焊料塊之某一部分,該部分具有與個別焊料塊不同之組合物。導電材料34及焊料塊32可被視為形成在積體電路基板14及16之基板側22上***地突出之導電支柱。
實例性積體電路基板18包括與TSV 24之兩端鄰接之接合墊30。作為一實例,積體電路結構或封裝10可最終具有由安裝至另一基板(例如一印刷電路板)之導線或其他導體接合之基板18之側22上之接合墊30。無論如何,根據本發明之實施例之積體電路結構包括至少兩個積體電路基板之一堆疊,該等積體電路基板之至少一者具有TSV,TSV具有與其之一端鄰接之一接合墊及與其之另一端鄰接之一焊料塊,例如基板14及16之任一者所展示。
焊料塊之個別者接合至堆疊之一直接鄰接基板上之一各自接合墊。為了便利,主要參考堆疊12之電路基板16及18而進行論述,但可存在相似結構且相對於基板14及16而展示相似結構。焊料塊32可視為與基板16相關聯且接合至堆疊12之直接鄰接基板18之接合墊30。
環氧助焊劑38包圍個別焊料塊32。具有與環氧助焊劑38不同之組合物之一環氧材料40包圍個別焊料塊32上之環氧助焊劑38。環氧助
焊劑38及介電填充材料40之各者可獨立地同質或非同質。環氧助焊劑38之一實例性橫向厚度範圍為自約5微米至約30微米。環氧助焊劑38可具有可變橫向厚度,例如圖所展示。將直接鄰接焊料塊32及/或直接鄰接導電材料34包圍之環氧助焊劑可使此等鄰接塊及/或結構彼此互連(圖中未展示)。另外,具有環氧材料之環氧助焊劑之一介面將比展示為使環氧助焊劑38與環氧材料40分離之難界定介面線更可能構成兩種不同材料之一混合物(圖中未明確展示)。相應地,參考厚度係相對於不同組合物環氧助焊劑38與環氧材料40之間之一更可能混合介面區之一橫向中點。環氧助焊劑38及環氧材料40(即,底部填充材料)之實例性適合前驅體購自加州Irvine市之Henkel公司。
在一實施例中且如圖所展示,環氧助焊劑38自基板16延伸至直接鄰接基板18(即,環氧助焊劑38直接緊貼各基板16及18之至少某一部分,其中個別接合墊被視為某一基板之一部分)。替代地,環氧助焊劑可僅***地延伸至基板16及18之一者(圖中未展示)或不***地延伸至基板16及18之兩者(圖中未展示)。環氧助焊劑可被連續或間斷地吸附至焊料塊32周圍,且可以類似方式相對於焊料塊32而連續或間斷地***延伸。當此情況存在且環氧助焊劑被橫向吸附至導電材料34上時,環氧助焊劑可相對於導電材料34而連續或間斷延伸。
在一實施例中,環氧材料40自基板16延伸至直接鄰接基板18(即,環氧材料40直接緊貼各基板16及18)。替代地,環氧材料40可僅延伸至基板16及18之一者(圖中未展示)或不延伸至基板16及18之兩者(圖中未展示)。在一實施例中且如圖所展示,積體電路基板16及18界定自環氧助焊劑38橫向向外之介於積體電路基板16與18之間之一空隙空間42。在一實施例中且如圖所展示,環氧材料40完全填充空隙空間42。
在一實施例中,環氧助焊劑38直接緊貼焊料塊32,且在一實施
例中,環氧材料40直接緊貼環氧助焊劑38。在其中環氧助焊劑38延伸至直接鄰接基板18之一實施例中且如圖所展示,環氧助焊劑38可直接緊貼個別接合墊30之周圍橫向側表面33,且在一實施例中,環氧助焊劑38直接緊貼個別接合墊30之***最外表面31。當存在導電材料34時,環氧助焊劑38亦可在一實施例中包圍導電材料34且可在一實施例中直接緊貼導電材料34。
在一實施例中,基板16與直接鄰接基板18之相對外表面21之最接近部分相隔不足40微米。在一實施例中,相對外表面21在全部位置處之相隔距離不足40微米。
使用環氧助焊劑及自該環氧助焊劑橫向向外之其他環氧材料可提供相較於使用環氧填充材料及助焊劑(非為環氧助焊劑)之先前技術方法而改良之助焊劑與填充材料之間之相容性。此外,使用環氧助焊劑可在歸因於實質上完全交聯處理之隨後加熱之後產生減少之剩餘揮發性組分(若存在),且藉此可產生更可靠之完成積體電路封裝結構。另外,使用環氧助焊劑可相較於免清洗助焊劑而減少剩餘物容積,其可改良環氧底部填充材料至緊密空間中之流動。此外,來自預固化環氧助焊劑之剩餘物本身最終形成可與環氧底部填充材料非常良好地相容之一固化環氧樹脂。另外,環氧助焊劑可在封裝組裝期間提供比其他非環氧助焊劑更佳之黏著性。
圖1至圖3之積體電路結構為一實例性實施例,其中環氧助焊劑38自電路基板16延伸至電路基板18。圖4展示一實例性替代積體電路結構10a,其中環氧助焊劑38a未自電路基板16延伸至電路基板18。已適當使用來自上述實施例之相同元件符號,其中用後綴「a」指示一些結構差異。圖4之積體電路結構10a展示相對於基板16、18之一實例,其中一環氧助焊劑38a延伸至直接鄰接基板18,但未延伸至基板16。替代地,相對於基板16、18且舉例而言,環氧助焊劑可延伸至電
路基板16且不延伸至電路基板18(圖中未展示)。
上文相對於一堆疊內之兩個直接鄰接基板而描述之各種關係可適用於或可不適用於該堆疊中之一些及/或全部其他直接鄰接積體電路基板對。
本發明之實施例亦涵蓋形成一積體電路結構(例如圖1至圖4之結構或其他積體電路結構之任一者)之方法。本發明之方法實施例涵蓋提供兩個或兩個以上電路基板,其中該等基板之至少一者包括個別地包括相對端之TSV。一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板之另一側上***地突出之另一端。例如,圖5展示組裝成一積體電路結構(例如一單一電路結構)之前之積體電路基板14、16及18。
將預固化環氧助焊劑(即,(若干)尚未固化環氧助焊劑前驅體)施加至焊料塊上。圖6展示一實例性實施例,其中在一適合托盤或容器50內提供一預固化環氧助焊劑37。電路基板16已經定位,使得其焊料塊32被浸入至預固化環氧助焊劑37中。預固化環氧助焊劑可完全或部分覆蓋焊料塊32。此外,當存在導電材料34時,預固化環氧助焊劑可覆蓋導電材料34之部分、不覆蓋導電材料34或覆蓋導電材料34之全部。
圖7展示電路基板16自預固化環氧助焊劑37及容器50之移除,其中環氧助焊劑37已被吸附至焊料塊32上。
基板直接緊貼基板之另一者,其中其上具有預固化環氧助焊劑之焊料塊之個別者緊貼另一基板之各自接合墊。例如,圖8展示基板14、16、18相對於彼此之實例性並置。預固化環氧助焊劑理想地具有適合之固有黏著性或黏著添加劑以允許例如圖8之結構保持足夠之結構完整性以使基板14、16、18保持於相對彼此之適當位置中,如圖所展示。
充分加熱焊料塊以使得其等接合至各自接合墊且將預固化環氧助焊劑固化為將焊料塊之個別者包圍之固化環氧助焊劑38,例如相對於圖9所展示。僅舉例而言,圖8之結構可經受適合紅外線輻射以實現自約240℃至約260℃之一實例性組裝溫度範圍以導致焊料接合至接合墊且導致環氧助焊劑固化。如圖所展示,環氧助焊劑可流動以圍繞導電結構34(若存在)之多數或全部延伸。隨後,用具有與環氧助焊劑不同之組合物之環氧材料包圍環氧助焊劑以例如產生圖1至圖3之結構或其他結構。
結論
在一些實施例中,一種積體電路結構包括兩個或兩個以上積體電路基板之一堆疊,該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV)。一導電接合墊鄰接該基板之一側上之該等端之一者。一導電焊料塊鄰接在該基板之另一側上***地突出之另一端。該等焊料塊之個別者接合至該堆疊之一直接鄰接基板上之一各自接合墊。環氧助焊劑包圍該等個別焊料塊。具有與該環氧助焊劑不同之組合物之一環氧材料包圍該等個別焊料塊上之該環氧助焊劑。
在一些實施例中,一種積體電路結構包括兩個或兩個以上積體電路基板之一堆疊。該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV)。一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板之另一側上***地突出之另一端。一導電材料介於該等個別TSV與該等個別焊料塊之間。該導電材料包含直接緊貼該等個別焊料塊之一部分。該部分具有與該等個別焊料塊不同之組合物。該等個別焊料塊接合至該堆疊之一直接鄰接基板上之一各自接合墊。環氧助焊劑包圍該等個別焊料塊及該導電材料。該環氧助焊劑自該基板延伸至該直接鄰接基板。具有與該環氧助焊劑不同之組合物之一環氧材料包圍該導電材料及該等個別焊料塊上之該環氧助焊
劑。該環氧材料直接緊貼該環氧助焊劑且自該基板延伸至該直接鄰接基板。該環氧材料完全填充自該基板與該直接鄰接基板之間之該環氧助焊劑橫向向外之一空隙空間。該基板與該直接鄰接基板具有相隔不足40微米之相對外表面之最接近部分。
在一些實施例中,一種形成一積體電路結構之方法包括提供兩個或兩個以上積體電路基板。該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV)。一導電接合墊鄰接該基板之一側上之該等端之一者。一導電焊料塊鄰接在該基板之另一側上***地突出之另一端。將預固化環氧助焊劑施加至該等焊料塊上。該基板緊貼該等基板之另一者,其中其上具有該預固化環氧助焊劑之該等焊料塊之個別者緊貼該另一基板之各自接合墊。充分加熱該等焊料塊以導致其等接合至該等各自接合墊且將該預固化環氧助焊劑固化為將該等焊料塊之個別者包圍之固化環氧助焊劑。用具有與該環氧助焊劑不同之組合物之一環氧材料包圍將該等個別焊料塊包圍之該固化環氧助焊劑。
按照法規,已針對結構及方法特徵而大致具體地書面描述本文所揭示之標的。然而,應瞭解,申請專利範圍不受限於所展示及所描述之具體特徵,此係因為本文中所揭示之方法包括實例性實施例。因此,申請專利範圍應被給予書面用語之完全範疇且應根據等效物之教義而適當解譯。
10‧‧‧積體電路結構/積體電路封裝
12‧‧‧堆疊
14‧‧‧積體電路基板
16‧‧‧積體電路基板
18‧‧‧積體電路基板
20‧‧‧側
21‧‧‧外表面
22‧‧‧側
24‧‧‧基板穿孔(TSV)
26‧‧‧端
28‧‧‧端
30‧‧‧導電接合墊
32‧‧‧導電焊料塊
38‧‧‧環氧助焊劑
40‧‧‧環氧材料
42‧‧‧空隙空間
Claims (16)
- 一種積體電路結構,其包括:兩個或兩個以上積體電路基板之一堆疊,該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV),一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板之另一側上***地突出之另一端;該等焊料塊之個別者接合至該堆疊之一直接鄰接基板上之一各自接合墊;環氧助焊劑包圍該等個別焊料塊;及具有與該環氧助焊劑不同之組合物之一環氧材料包圍該等個別焊料塊上之該環氧助焊劑。
- 如請求項1之積體電路結構,其中該環氧助焊劑延伸至該直接鄰接基板。
- 如請求項2之積體電路結構,其中該等接合墊相對於該直接鄰接基板之一外表面而凸起,該等各自接合墊具有一***最外表面且包圍橫向側表面;及該環氧助焊劑直接緊貼該等個別接合墊之該等周圍橫向側表面。
- 如請求項3之積體電路結構,其中該環氧助焊劑直接緊貼該等個別接合墊之該***最外表面。
- 如請求項1之積體電路結構,其中該環氧助焊劑自該基板延伸至該直接鄰接基板。
- 如請求項1之積體電路結構,其中該環氧材料自該基板延伸至該直接鄰接基板。
- 如請求項1之積體電路結構,其中該環氧助焊劑直接緊貼該等焊料塊。
- 如請求項7之積體電路結構,其包括介於該等個別TSV與該等個別焊料塊之間之一導電材料,該導電材料包含直接緊貼該等個別焊料塊之一部分,該部分具有與該等個別焊料塊不同之組合物,該環氧助焊劑直接緊貼該導電材料。
- 如請求項1之積體電路結構,其中該環氧助焊劑直接緊貼該等焊料塊且該環氧材料直接緊貼該環氧助焊劑。
- 如請求項1之積體電路結構,其中該環氧材料完全填充自該基板與該直接鄰接基板之間之該環氧助焊劑橫向向外之一空隙空間。
- 如請求項1之積體電路結構,其中該環氧助焊劑未自該基板延伸至該直接鄰接基板。
- 如請求項11之積體電路結構,其中該環氧助焊劑延伸至該直接鄰接基板。
- 一種積體電路結構,其包括:兩個或兩個以上積體電路基板之一堆疊,該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV),一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板之另一側上***地突出之另一端,一導電材料介於該等個別TSV與該等個別焊料塊之間,該導電材料包含直接緊貼該等個別焊料塊之一部分,該部分具有與該等個別焊料塊不同之組合物。 該等個別焊料塊接合至該堆疊之一直接鄰接基板上之一各自接合墊;環氧助焊劑包圍該等個別焊料塊及該導電材料,該環氧助焊劑自該基板延伸至該直接鄰接基板;及具有與該環氧助焊劑不同之組合物之一環氧材料包圍該導電材料及該等個別焊料塊上之該環氧助焊劑,該環氧材料直接緊 貼該環氧助焊劑且自該基板延伸至該直接鄰接基板,該環氧材料完全填充自該基板與該直接鄰接基板之間之該環氧助焊劑橫向向外之一空隙空間,該基板與該直接鄰接基板具有相隔不足40微米之相對外表面之最接近部分。
- 如請求項13之積體電路結構,其中該等接合墊相對於該直接鄰接基板之一外表面而凸起,該等各自接合墊具有一***最外表面且包圍橫向側表面;及該環氧助焊劑直接緊貼該等個別接合墊之該等周圍橫向側表面。
- 一種形成一積體電路結構之方法,其包括:提供兩個或兩個以上積體電路基板,該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV),一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板之另一側上***地突出之另一端;將預固化環氧助焊劑施加至該等焊料塊上;使該基板緊貼該等基板之另一者,其中其上具有該預固化環氧助焊劑之該等焊料塊之個別者緊貼該另一基板之各自接合墊;充分加熱該等焊料塊以導致其等接合至該等各自接合墊且將該預固化環氧助焊劑固化為將該等焊料塊之個別者包圍之固化環氧助焊劑;及用具有與該環氧助焊劑不同之組合物之一環氧材料包圍將該等個別焊料塊包圍之該固化環氧助焊劑。
- 一種積體電路結構,其包括:兩個或兩個以上積體電路基板之一堆疊,該等基板之至少一者包括個別地包括相對端之基板穿孔(TSV),一導電接合墊鄰接該基板之一側上之該等端之一者且一導電焊料塊鄰接在該基板 之另一側上***地突出之另一端;該等焊料塊之個別者接合至該堆疊之一直接鄰接基板上之一各自接合墊;環氧助焊劑包圍該等焊料塊且正視地位於該堆疊之該兩個直接鄰接基板之間;及與該環氧助焊劑具有不同組合物之一環氧材料包圍該等個別焊料塊上之該環氧助焊劑,該環氧材料係正視地位於該堆疊之該兩個直接鄰接基板之間,該環氧材料係直接緊貼該堆疊之該兩個直接鄰接基板之一相對外表面及一面對外表面。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123700B2 (en) | 2012-01-06 | 2015-09-01 | Micron Technology, Inc. | Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8907494B2 (en) * | 2013-03-14 | 2014-12-09 | International Business Machines Corporation | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures |
KR102391249B1 (ko) | 2015-05-28 | 2022-04-28 | 삼성디스플레이 주식회사 | 표시 장치 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030096453A1 (en) * | 2001-11-16 | 2003-05-22 | Shanger Wang | Integrated void-free process for assembling a solder bumped chip |
US20070132104A1 (en) * | 2003-03-31 | 2007-06-14 | Farnworth Warren M | Semiconductor component having plate, stacked dice and conductive vias |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2793528B2 (ja) * | 1995-09-22 | 1998-09-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | ハンダ付け方法、ハンダ付け装置 |
US6367150B1 (en) | 1997-09-05 | 2002-04-09 | Northrop Grumman Corporation | Solder flux compatible with flip-chip underfill material |
US6265776B1 (en) | 1998-04-27 | 2001-07-24 | Fry's Metals, Inc. | Flip chip with integrated flux and underfill |
JP3836349B2 (ja) * | 2001-09-27 | 2006-10-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2003100810A (ja) * | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置とその製造方法 |
JP3829325B2 (ja) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | 半導体素子およびその製造方法並びに半導体装置の製造方法 |
CN100508148C (zh) | 2004-02-11 | 2009-07-01 | 英飞凌科技股份公司 | 具有接触支撑层的半导体封装以及制造该封装的方法 |
KR100570514B1 (ko) | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
TWI237370B (en) * | 2004-07-30 | 2005-08-01 | Advanced Semiconductor Eng | Chip package structure and process for fabricating the same |
JP2006165320A (ja) * | 2004-12-08 | 2006-06-22 | Matsushita Electric Ind Co Ltd | 半導体積層モジュールとその製造方法 |
US7169641B2 (en) | 2005-05-03 | 2007-01-30 | Stats Chippac Ltd. | Semiconductor package with selective underfill and fabrication method therfor |
US7517798B2 (en) * | 2005-09-01 | 2009-04-14 | Micron Technology, Inc. | Methods for forming through-wafer interconnects and structures resulting therefrom |
US7863727B2 (en) | 2006-02-06 | 2011-01-04 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
US8143719B2 (en) | 2007-06-07 | 2012-03-27 | United Test And Assembly Center Ltd. | Vented die and package |
US7843064B2 (en) | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
JP2009239256A (ja) * | 2008-03-03 | 2009-10-15 | Panasonic Corp | 半導体装置及びその製造方法 |
US7683459B2 (en) | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US8334170B2 (en) | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
US7843072B1 (en) * | 2008-08-12 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor package having through holes |
KR101553560B1 (ko) | 2008-11-26 | 2015-09-16 | 삼성전자주식회사 | 적층 패키지 및 이의 제조 방법 |
US8183673B2 (en) | 2008-10-21 | 2012-05-22 | Samsung Electronics Co., Ltd. | Through-silicon via structures providing reduced solder spreading and methods of fabricating the same |
JP4696152B2 (ja) * | 2008-11-10 | 2011-06-08 | 株式会社日立製作所 | 半導体装置の製造方法および半導体装置 |
US8900921B2 (en) | 2008-12-11 | 2014-12-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV |
KR101078735B1 (ko) | 2009-07-07 | 2011-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US8143097B2 (en) | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
KR101632399B1 (ko) * | 2009-10-26 | 2016-06-23 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US8451620B2 (en) | 2009-11-30 | 2013-05-28 | Micron Technology, Inc. | Package including an underfill material in a portion of an area between the package and a substrate or another package |
KR101124568B1 (ko) | 2010-05-31 | 2012-03-16 | 주식회사 하이닉스반도체 | 반도체 칩, 이를 포함하는 적층 칩 구조의 반도체 패키지 |
US9123700B2 (en) | 2012-01-06 | 2015-09-01 | Micron Technology, Inc. | Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias |
-
2012
- 2012-01-06 US US13/345,422 patent/US9123700B2/en active Active
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030096453A1 (en) * | 2001-11-16 | 2003-05-22 | Shanger Wang | Integrated void-free process for assembling a solder bumped chip |
US20070132104A1 (en) * | 2003-03-31 | 2007-06-14 | Farnworth Warren M | Semiconductor component having plate, stacked dice and conductive vias |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123700B2 (en) | 2012-01-06 | 2015-09-01 | Micron Technology, Inc. | Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias |
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US9123700B2 (en) | 2015-09-01 |
EP2801111A4 (en) | 2015-09-23 |
KR101649429B1 (ko) | 2016-08-19 |
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