TWI578472B - 封裝基板、半導體封裝件及其製法 - Google Patents

封裝基板、半導體封裝件及其製法 Download PDF

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TWI578472B
TWI578472B TW103141137A TW103141137A TWI578472B TW I578472 B TWI578472 B TW I578472B TW 103141137 A TW103141137 A TW 103141137A TW 103141137 A TW103141137 A TW 103141137A TW I578472 B TWI578472 B TW I578472B
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circuit layer
electrical connection
layer
carrier
package substrate
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TW103141137A
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TW201620100A (zh
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孫銘成
林俊賢
沈子傑
邱士超
白裕呈
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矽品精密工業股份有限公司
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Priority to TW103141137A priority Critical patent/TWI578472B/zh
Priority to CN201410791135.4A priority patent/CN105762127B/zh
Priority to US14/837,245 priority patent/US9640503B2/en
Publication of TW201620100A publication Critical patent/TW201620100A/zh
Priority to US15/466,063 priority patent/US9905438B2/en
Application granted granted Critical
Publication of TWI578472B publication Critical patent/TWI578472B/zh

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Description

封裝基板、半導體封裝件及其製法
本發明提供一種封裝基板、半導體封裝件及其製法，尤指一種提升覆晶接合強度的封裝基板、半導體封裝件及其製法。
隨著提高電子產品功能的需求，對具有與晶片覆晶接合之密集電性連接墊的封裝基板之製造技術的要求也不斷提高，遂產生了各種封裝基板之製造技術。
請參照第1圖，其係習知之封裝基板1的剖視圖。封裝基板1係包括絕緣層15、第一線路層11、第二線路層12、導電通孔13及第三電性連接墊18。
如上所述之絕緣層15具有相對之第一表面15a及第二表面15b，而該第一線路層11具有嵌設於該第一表面15a並由該第一表面15a露出的第一電性連接墊111，該第二線路層12具有嵌設於該第二表面15b並由該第二表面15b露出的第二電性連接墊121及導電墊122，且該絕緣層15中形成有導電通孔13以電性連接該導電墊122，另該第一表面15a上形成有第三電性連接墊18以電性連接該導電通 孔13，而可選擇地，在該導電墊122與該導電通孔13之間及該絕緣層15與該導電通孔13之間則可形成有導電層16。
然而，由於晶片功能不斷增強，故與封裝基板覆晶接合所須之電性接點的數目也不斷提高，而在輕薄化電子產品的要求下，有限之電性接點分布面積及不斷提高之電性接點的數目自然造成與晶片覆晶接合之第一電性連接墊面積的縮小，而在習知之封裝基板中，由於第一電性連接墊與晶片覆晶接合之表面為平面，故在縮小面積之第一電性連接墊與晶片覆晶接合時往往造成第一電性連接墊與晶片之導電凸塊上的銲料之間的接合強度不足，並發生不沾鍚(non-wetting)的問題，從而導致產品信賴度及良率大幅下降。
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種封裝基板，係包括：具有相對之第一表面及第二表面的絕緣層；嵌埋於該絕緣層中並由該第一表面所外露出且具有複數第一電性連接墊的第一線路層；嵌埋於該絕緣層中並由該第二表面所外露出且具有複數第二電性連接墊的第二線路層；形成於該第一表面上以電性連接該第一線路層的第三線路層；分別對應形成於各該第一電性連接墊上的複數第一金屬凸部；以及豎埋於該絕緣層中以電性連接該第二線 路層和第三線路層的至少一導電通孔。
本發明並提供一種半導體封裝件，係包括：封裝基板，其具有相對之第一表面及第二表面的絕緣層；嵌埋於該絕緣層中並由該第一表面所外露出且具有複數第一電性連接墊的第一線路層；嵌埋於該絕緣層中並由該第二表面所外露出且具有複數第二電性連接墊的第二線路層；形成於該第一表面上以電性連接該第一線路層的第三線路層；分別對應形成於各該第一電性連接墊上的複數第一金屬凸部；及豎埋於該絕緣層中以電性連接該第二線路層和第三線路層的至少一導電通孔；覆晶設於該封裝基板上之至少一半導體元件；以及形成於該封裝基板上並包覆該半導體元件的封裝膠體。
本發明又提供一種封裝基板之製法，係包括：準備第一載板和第二載板，該第一載板上形成有具複數第一電性連接墊之第一線路層，該第二載板上形成有具複數第二電性連接墊之第二線路層；在該第一線路層和第二線路層面對面之情況下，形成包覆該第一線路層和第二線路層之絕緣層，其中，該絕緣層具有相對之第一表面及第二表面；移除該第一載板和第二載板，以令該第一表面外露出該第一線路層，該第二表面外露出該第二線路層；以及於該第一表面上形成第三線路層，並對應於該第一電性連接墊上形成第一金屬凸部，及於該絕緣層中形成電性連接該第二線路層和第三線路層之至少一導電通孔。
本發明另提供一種半導體封裝件之製法，係包括：準 備第一載板和第二載板，該第一載板上形成有具複數第一電性連接墊之第一線路層，該第二載板上形成有具複數第二電性連接墊之第二線路層；在該第一線路層和第二線路層面對面之情況下，形成包覆該第一線路層和第二線路層之絕緣層，其中，該絕緣層具有相對之第一表面及第二表面；移除該第一載板和第二載板，以令該第一表面外露出該第一線路層，該第二表面外露出該第二線路層；以及於該第一表面上形成第三線路層，並對應於該第一電性連接墊上形成第一金屬凸部，及於該絕緣層中形成電性連接該第二線路層和第三線路層之至少一導電通孔，以形成封裝基板；於該封裝基板上覆晶設置至少一半導體元件；以及於該封裝基板上形成封裝膠體，以包覆該半導體元件。
本發明的封裝基板及其製法係藉由形成在第一電性連接墊之露出表面上且投影面積小於露出之第一電性連接墊之投影面積的第一金屬凸部而使之後覆晶接合於第一電性連接墊之晶片的導電凸塊上的銲料能提升第一電性連接墊與導電凸塊上的銲料之間的接合強度，進而可使第一電性連接墊能進一步縮小面積並防止第一電性連接墊與導電凸塊上的銲料於覆晶接合時發生不沾鍚(non-wetting)的問題，以提升產品信賴度及良率。
1、2‧‧‧封裝基板
3‧‧‧半導體元件
3a‧‧‧作用面
3b‧‧‧非作用面
4‧‧‧封裝膠體
11、21‧‧‧第一線路層
12、22‧‧‧第二線路層
13、23‧‧‧導電通孔
15、25‧‧‧絕緣層
15a、25a‧‧‧第一表面
15b、25b‧‧‧第二表面
16、26‧‧‧導電層
18‧‧‧第三電性連接墊
28‧‧‧第三線路層
24‧‧‧板體
24a‧‧‧第一載板
24b‧‧‧第二載板
25’‧‧‧絕緣材
27a‧‧‧第一金屬凸部
27b‧‧‧第二金屬凸部
31‧‧‧導電柱
32‧‧‧銲料
111、211‧‧‧第一電性連接墊
121、221‧‧‧第二電性連接墊
122、222‧‧‧導電墊
252‧‧‧通孔
H‧‧‧段差
第1圖係習知之封裝基板的剖視圖；第2A至2E圖係本發明之封裝基板的製法之一態樣的剖視圖，而第2A’-1及2A’-2圖係本發明之封裝基板的 第2A圖製法之另一態樣的剖視圖，且第2B-1及2B-2圖係本發明之封裝基板的第2B圖製法之另一態樣的剖視圖；第3圖係本發明之半導體封裝件及其製法的剖視圖；第4A至4E圖係本發明之封裝基板的製法之另一態樣的剖視圖；以及第5圖係本發明之半導體封裝件及其製法之另一態樣的剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
請參照第2A至2E圖，其係本發明之封裝基板的製法之一態樣的剖視圖。
如第2A圖所示，本發明之封裝基板的製法係首先準備第一載板24a和第二載板24b，該第一載板24a上形成有具複數第一電性連接墊211之第一線路層21，該第二載板24b上形成有具複數第二電性連接墊221之第二線路層22。而該第一載板24a和第二載板24b之準備亦可如第2A’-1圖般先提供一包括相互疊接之第一載板24a和第二載板24b的板體24，且於該第一載板24a上形成具複數第一電性連接墊211之第一線路層21，該第二載板24b上形 成具複數第二電性連接墊221之第二線路層22，並接著分離該二載板，得到如第2A’-2圖般分離該第一載板24a和第二載板24b。
詳而言之，在第2A’-1圖例子中，該板體24的該第一載板24a與第二載板24b之間可夾置有黏著層(未圖示)以黏著該第一載板24a及第二載板24b，而在該板體24是由單一板體所構成的情況下，可裁切該板體24為該第一載板24a及第二載板24b。而該第二線路層22亦可具有導電墊222，而其電性連接之細節係所屬技術領域中具有通常知識者所熟知，在此不再贅述。
其次，如第2B至2B-2圖所示，在該第一線路層21和第二線路層22面對面之情況下，形成包覆該第一線路層21和第二線路層22之絕緣層25，其中，該絕緣層25具有相對之第一表面25a及第二表面25b。
詳而言之但非限定而言，形成絕緣層25之絕緣材25’除了絕緣材料，亦可為用做介電材料、封裝材料或其組合的材料，且形成絕緣層25之方式可因製程策略之不同而有以下非限制性態樣，例如，可在該第一載板24a和第二載板24b之至少一者上形成絕緣材25’，例如，如第2B圖所示，在該第一載板24a上形成絕緣材25’，再壓合該第一載板24a和第二載板24b，以形成該絕緣層25，或者如第2B-1圖所示，可先提供一絕緣材25’，再於該第一線路層21和第二線路層22面對面之情況下，將該第一線路層21和第二線路層22壓入該絕緣材25’，以形成該絕緣 層25，又或者如第2B-2圖所示，於該第一線路層21和第二線路層22面對面之情況下，於該第一線路層21和第二線路層22之間填充絕緣材25’，以形成該絕緣層25。
接著，如第2C圖所示，移除該該第一載板24a和第二載板24b，以令該第一表面25a外露出該第一線路層21，該第二表面25b外露出該第二線路層22。
再者，如第2D圖所示，在該絕緣層25中由該第一表面25a側形成露出該第二線路層22之導電墊222的通孔252，而可選擇地，可在該通孔252中、由該通孔252露出之該導電墊222上及該第一表面25a上形成導電層26。
最後，如第2E圖所示，於該絕緣層25中形成電性連接該第二線路層22之至少一導電通孔23，及於該第一表面25a上形成電性連接該導電通孔23之第三線路層28，並對應於該第一電性連接墊211上形成第一金屬凸部27a，以形成本發明之封裝基板2。而各該第一金屬凸部27a在該第一表面25a上之投影面積小於該第一電性連接墊211之面積。另外，值得注意的是，該第三線路層28係電性連接該第一金屬凸部27a或第一線路層21，而該第三線路層28電性連接該第一金屬凸部27a或第一線路層21之方式可依設計而改變，而其細節係所屬技術領域中具有通常知識者可依設計而實施，在此不再贅述。
詳而言之但非限制而言，在形成該導電通孔23及第一金屬凸部27a之前，可以阻層(未圖示)遮蔽不欲形成該導電通孔23及第一金屬凸部27a處之該導電層26，並於形 成該導電通孔23及第一金屬凸部27a後，移除未形成該導電通孔23及第一金屬凸部27a處的該導電層26。而可選擇地，本發明可於形成該第一金屬凸部27a時，分別對應於各該第二電性連接墊221上形成第二金屬凸部27b，且該第二金屬凸部27b在該第二表面25b上之投影面積小於該第二電性連接墊221之面積，而該第二金屬凸部27b與該第二電性連接墊221之間亦形成有導電層26，其形成方式與該第一電性連接墊211和第一金屬凸部27a之間的導電層26大同小異，不再贅述。
本發明亦提供一種封裝基板2，其一態樣如第2E圖所示，該封裝基板2包括：具有相對之第一表面25a及第二表面25b的絕緣層25、嵌埋於該絕緣層25中並由該第一表面25a所外露出且具有複數第一電性連接墊211的第一線路層21、嵌埋於該絕緣層25中並由該第二表面25b所外露出且具有複數第二電性連接墊221的第二線路層22、形成於該第一表面25a上以電性連接該第一線路層21的第三線路層28、分別對應形成於各該第一電性連接墊211上的複數第一金屬凸部27a以及豎埋於該絕緣層25中以電性連接該第二線路層22和第三線路層28的至少一導電通孔23。並且，各該第一金屬凸部27a在該第一表面25a上之投影面積小於該第一電性連接墊211之面積，而該導電通孔23係延伸至該第一表面25a，並與該第一表面25a共平面。另外，本發明之封裝基板2復包括複數第二金屬凸部27b，係分別對應形成於各該第二電性連接墊221上，且各 該第二金屬凸部27b在該第二表面25b上之投影面積小於該第二電性連接墊221之面積。
請參照第3圖，其係本發明之半導體封裝件及其製法的剖視圖。本發明之半導體封裝件係於如第2E圖所示的封裝基板2上覆晶設置至少一半導體元件3，並於該封裝基板2上形成包覆該半導體元件3的封裝膠體4。
詳而言之但非限定而言，該半導體元件3具有作用面3a及非作用面3b，且該作用面3a上可具有導電柱31及導電柱31上的銲料32，而可選擇地，該半導體元件3可以迴銲方式而使該銲料32包覆該第一金屬凸部27a，以令該半導體元件3覆晶設於該封裝基板2之第一表面25a，進而形成如第3圖所示之半導體封裝件，或者，該半導體元件3可以迴銲方式而使該銲料32包覆該第二金屬凸部27b，以令該半導體元件3覆晶設於該封裝基板2之第二表面25b(未圖示此情況)。
請參照第4A至4E圖，其係本發明之封裝基板的製法之另一態樣的剖視圖，基於該第一線路層21和第二線路層22若由電鍍形成，該第一載板24a表面和第二載板24b表面皆可先形成導電層26，而該第一線路層21和第二線路層22係形成於該導電層26上，故於如第4C圖所示般移除該第一載板24a和第二載板24b後，第4C圖與第2C圖之差異係在於再移除該導電層26，且於移除該導電層26時可移除一部分外露之該第一線路層21，而於移除該導電層26時亦可移除一部分外露之該第二線路層22，故外露之該 第一線路層21的表面與該第一表面25a可具有段差H，而外露之該第二線路層22的表面與該第二表面25b亦可具有段差H。亦即，該外露之該第一線路層21的表面可與該第一表面25a構成凹部，外露之該第二線路層22的表面亦可與該第二表面25b構成凹部。其餘製法與第2B、2D及2E圖所示者大同小異，不再贅述。另外，如第4E圖所示的本發明之封裝基板2的另一態樣與第2E圖所示者之差異亦在於外露之該第一線路層21的表面與該第一表面25a可具有段差H，且外露之該第二線路層22的表面與該第二表面25b亦可具有段差H。而該第一金屬凸部27a及第二金屬凸部27b的高度皆分別突出第一表面25a和第二表面25b。
請參照第5圖，其係本發明之半導體封裝件及其製法之另一態樣的剖視圖，其與第3圖之差異亦在於外露之該第一線路層21的表面可與該第一表面25a具有段差H，且外露之該第二線路層22的表面亦可與該第二表面25b具有段差H。
綜上所述，相較於先前技術，由於本發明係藉由形成在第一電性連接墊(或第二電性連接墊)之露出表面上且投影面積小於露出之第一電性連接墊(或第二電性連接墊)之投影面積的第一金屬凸部(或第二金屬凸部)，而使之後覆晶接合於第一電性連接墊之半導體元件之導電凸塊上的銲料能同時與第一電性連接墊及第一金屬凸部的露出表面接合，或者使之後覆晶接合於第二電性連接墊之半導體元件 之導電凸塊上的銲料能同時與第二電性連接墊及第二金屬凸部的露出表面接合，從而提升導電凸塊上的銲料與第一電性連接墊或第二電性連接墊之間的接合強度，進而可使第一電性連接墊或第二電性連接墊能進一步縮小面積並防止導電凸塊上的銲料與第一電性連接墊或第二電性連接墊於覆晶接合時發生不沾鍚(non-wetting)的問題，以提升產品信賴度及良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝基板
21‧‧‧第一線路層
22‧‧‧第二線路層
23‧‧‧導電通孔
25‧‧‧絕緣層
25a‧‧‧第一表面
25b‧‧‧第二表面
26‧‧‧導電層
27a‧‧‧第一金屬凸部
27b‧‧‧第二金屬凸部
28‧‧‧第三線路層
211‧‧‧第一電性連接墊
221‧‧‧第二電性連接墊
222‧‧‧導電墊

Claims (27)

  1. 一種封裝基板，係包括：絕緣層，係具有相對之第一表面及第二表面；第一線路層，係嵌埋於該絕緣層中，且該第一表面外露出該第一線路層，其中，該第一線路層具有複數第一電性連接墊，且外露之該第一線路層的表面與該第一表面具有段差；第二線路層，係嵌埋於該絕緣層中，且該第二表面外露出該第二線路層，其中，該第二線路層具有複數第二電性連接墊；第三線路層，係形成於該第一表面上，以電性連接該第一線路層；複數第一金屬凸部，係分別對應形成於各該第一電性連接墊上；以及至少一導電通孔，係豎埋於該絕緣層中，以電性連接該第二線路層和第三線路層。
  2. 如申請專利範圍第1項所述之封裝基板，其中，各該第一金屬凸部在該第一表面上之投影面積小於該第一電性連接墊之面積。
  3. 如申請專利範圍第1項所述之封裝基板，其中，外露之該第二線路層的表面與該第二表面具有段差。
  4. 如申請專利範圍第1項所述之封裝基板，其中，該導電通孔，係延伸至該第一表面，並與該第一表面共平面。
  5. 如申請專利範圍第1項所述之封裝基板，復包括複數第 二金屬凸部，係分別對應形成於各該第二電性連接墊上。
  6. 如申請專利範圍第5項所述之封裝基板，其中，各該第二金屬凸部在該第二表面上之投影面積小於該第二電性連接墊之面積。
  7. 一種半導體封裝件，係包括：如申請專利範圍第1項所述之封裝基板；至少一半導體元件，係覆晶設於該封裝基板上，該半導體元件具有相對之作用面與非作用面，該半導體元件之作用面上具有導電柱，該導電柱上設有銲料，該銲料用以包覆該第一金屬凸部；以及封裝膠體，係形成於該封裝基板上，並包覆該半導體元件。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該封裝基板復包括分別對應形成於各該第二電性連接墊上之複數第二金屬凸部。
  9. 如申請專利範圍第8項所述之半導體封裝件，其中，各該第二金屬凸部在該第二表面上之投影面積小於該第二電性連接墊之面積。
  10. 如申請專利範圍第7項所述之半導體封裝件，其中，各該第一金屬凸部在該第一表面上之投影面積小於該第一電性連接墊之面積。
  11. 如申請專利範圍第7項所述之半導體封裝件，其中，外露之該第二線路層的表面與該第二表面具有段差。
  12. 如申請專利範圍第7項所述之半導體封裝件，其中，該導電通孔，係延伸至該第一表面，並與該第一表面共平面。
  13. 一種封裝基板之製法，係包括：準備第一載板和第二載板，該第一載板的表面具有導電層，且該第一載板的表面之導電層上形成有具複數第一電性連接墊之第一線路層，該第二載板上形成有具複數第二電性連接墊之第二線路層；在該第一線路層和第二線路層面對面之情況下，形成包覆該第一線路層和第二線路層之絕緣層，其中，該絕緣層具有相對之第一表面及第二表面；移除該第一載板和第二載板，以令該第一表面外露出該第一線路層，該第二表面外露出該第二線路層，其中，外露之該第一線路層的表面與該第一表面具有段差；於該絕緣層中形成電性連接該第二線路層之至少一導電通孔；以及於該第一表面上形成電性連接該導電通孔之第三線路層，並對應於該第一電性連接墊上形成第一金屬凸部。
  14. 如申請專利範圍第13項所述之封裝基板之製法，其中，該第一載板和第二載板之準備係包括：提供一包括相互疊接之第一載板和第二載板的板體； 於該第一載板上形成具複數第一電性連接墊之第一線路層，該第二載板上形成具複數第二電性連接墊之第二線路層；以及分離該第一載板和第二載板。
  15. 如申請專利範圍第13項所述之封裝基板之製法，其中，該第二載板表面具有另一導電層，該第二線路層係形成於該另一導電層上，且於移除該第二載板後，外露之該第二線路層的表面與該第二表面具有段差。
  16. 如申請專利範圍第13項所述之封裝基板之製法，其中，形成該絕緣層之方式係包括在該第一載板和第二載板之至少一者上形成絕緣材，再壓合該第一載板和第二載板，以形成該絕緣層。
  17. 如申請專利範圍第13項所述之封裝基板之製法，其中，形成該絕緣層之方式係包括提供一絕緣材，再於該第一線路層和第二線路層面對面之情況下，將該第一線路層和第二線路層壓入該絕緣材，以形成該絕緣層。
  18. 如申請專利範圍第13項所述之封裝基板之製法，其中，形成該絕緣層之方式係包括於該第一線路層和第二線路層面對面之情況下，於該第一線路層和第二線路層之間填充絕緣材，以形成該絕緣層。
  19. 如申請專利範圍第13項所述之封裝基板之製法，其中，各該第一金屬凸部在該第一表面上之投影面積小於該第一電性連接墊之面積。
  20. 如申請專利範圍第13項所述之封裝基板之製法，復包 括於形成該第一金屬凸部時，分別對應於各該第二電性連接墊上形成第二金屬凸部。
  21. 如申請專利範圍第20項所述之封裝基板之製法，其中，各該第二金屬凸部在該第二表面上之投影面積小於該第二電性連接墊之面積。
  22. 一種半導體封裝件之製法，係包括：於如申請專利範圍第13項之封裝基板上覆晶設置至少一半導體元件，其中該半導體元件具有相對之作用面與非作用面，該半導體元件之作用面上具有導電柱，該導電柱上設有銲料，該銲料用以包覆該第一金屬凸部；以及於該封裝基板上形成封裝膠體，以包覆該半導體元件。
  23. 如申請專利範圍第22項所述之半導體封裝件之製法，其中，各該第一金屬凸部在該第一表面上之投影面積小於該第一電性連接墊之面積。
  24. 如申請專利範圍第22項所述之半導體封裝件之製法，其中，外露之該第二線路層的表面與該第二表面具有段差。
  25. 如申請專利範圍第22項所述之半導體封裝件之製法，其中，該導電通孔係延伸至該第一表面，並與該第一表面共平面。
  26. 如申請專利範圍第22項所述之半導體封裝件之製法，其中，該封裝基板復包括分別對應形成於各該第二電性 連接墊上之複數第二金屬凸部。
  27. 如申請專利範圍第26項所述之半導體封裝件之製法，其中，各該第二金屬凸部在該第二表面上之投影面積小於該第二電性連接墊之面積。
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