TWI456714B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI456714B
TWI456714B TW097144932A TW97144932A TWI456714B TW I456714 B TWI456714 B TW I456714B TW 097144932 A TW097144932 A TW 097144932A TW 97144932 A TW97144932 A TW 97144932A TW I456714 B TWI456714 B TW I456714B
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pattern
insulating film
semiconductor substrate
rewiring
region
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TW200941664A (en
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Yuki Koide
Masataka Minami
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Renesas Electronics Corp
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Claims (19)

  1. 一種半導體裝置，其特徵在於：包括設置在半導體基板上之多層配線、以覆蓋上述多層配線之方式而設置在上述半導體基板上之無機類絕緣膜、設置在上述無機類絕緣膜上之第1有機系絕緣膜、設置在上述第1有機系絕緣膜上之再配線、及以覆蓋上述再配線之方式而設置在上述第1有機系絕緣膜上之第2有機系絕緣膜，上述再配線在上述半導體基板之面內，係具有彼此電性分離之第1圖案及第2圖案，在上述多層配線之最上層配線之一部分上且在上述無機類絕緣膜及上述第1有機系絕緣膜上所設置之第1開口部中，上述第1圖案與上述多層配線電性連接，且上述第2圖案與上述多層配線電性分離，在上述第1圖案之一部分上且在上述第2有機系絕緣膜上所設置之第2開口部中，上述第1圖案之一部分露出，且上述第1圖案與上述第2圖案設置成混合存在於上述半導體基板之面內。
  2. 如請求項1之半導體裝置，其中在上述第1圖案之一部分上，係設置有與上述第1圖案電性連接之凸塊電極。
  3. 如請求項1之半導體裝置，其中上述半導體基板係構成在面內具有第1區域及該第1區域周圍之第2區域之半導 體晶片，且上述第1圖案設置在上述第2區域，而上述第2圖案設置在上述第1區域及上述第2區域。
  4. 如請求項1之半導體裝置，其中上述第2圖案之平面形狀為圓形狀或者所有的角為鈍角之多角形狀。
  5. 如請求項1之半導體裝置，其中上述第2圖案之加工尺寸為上述第1圖案之加工尺寸以下。
  6. 如請求項1之半導體裝置，其中上述再配線在上述半導體基板之面內之佔有率為35%以上。
  7. 如請求項1之半導體裝置，其中上述再配線在上述半導體基板之面內之佔有率為60%以下。
  8. 一種半導體裝置之製造方法，其特徵在於包括以下步驟：(a)在半導體基板上形成多層配線之後，以覆蓋上述多層配線之方式在上述半導體基板上形成第1絕緣膜；(b)在上述第1絕緣膜上形成第2絕緣膜；(c)在上述多層配線之最上層配線之一部分上的上述第1絕緣膜及上述第2絕緣膜，形成使上述最上層配線之一部分露出之第1開口部；(d)使用電解電鍍法，以埋入到上述第1開口部之內部之方式，而在上述第2絕緣膜上形成構成第1圖案之再配線，並且以與上述第1圖案電性分離之方式，而在上述第2絕緣膜形成構成第2圖案之上述再配線；及(e)以覆蓋上述再配線之方式於上述半導體基板上形成 第3絕緣膜之後，將在上述第1圖案之一部分上而使上述第1圖案之一部分露出之第2開口部形成於上述第3絕緣膜上；在上述步驟(d)中，以使上述第1圖案及上述第2圖案混合存在於上述半導體基板之面內之方式而形成上述再配線。
  9. 如請求項8之半導體裝置之製造方法，其進一步包括以下步驟：(f)在上述步驟(d)之前，藉由使用有計算機之自動設計，而將上述第1圖案及上述第2圖案定位於上述半導體基板之面內，上述步驟(f)包括以下步驟：(f1)在上述半導體基板之面內形成配置有上述第1圖案之第1處理圖案；(f2)在上述半導體基板之整個面上形成配置有上述第2圖案之第2處理圖案；(f3)將上述第1處理圖案及上述第2處理圖案加以合成；及(f4)在上述步驟(f3)之後，計算與上述第1圖案在固定間隔內之上述第2圖案，並將其刪除。
  10. 一種半導體裝置之製造方法，其特徵在於包括以下步驟：(a)準備具有由第1晶片區域及第2晶片區域所構成之照射區域之半導體晶圓； (b)在上述半導體晶圓上形成多層配線之後，以覆蓋上述多層配線之方式在上述半導體晶圓上形成第1絕緣膜；(c)在上述第1絕緣膜上形成第2絕緣膜；(d)在上述第1晶片區域中，在上述多層配線之最上層配線之一部分上的上述第1絕緣膜及上述第2絕緣膜，形成使上述最上層配線之一部分露出之第1開口部；(e)使用電鍍法，在上述第1晶片區域中，以埋入到上述第1開口部之內部之方式，在上述第2絕緣膜上形成構成第1圖案之再配線，並且以與上述第1圖案電性分離之方式，而在上述第2絕緣膜上形成構成第2圖案之上述再配線；及(f)以覆蓋上述再配線之方式於上述半導體基板上形成第3絕緣膜之後，將在上述第1圖案之一部分上而使上述第1圖案之一部分露出之第2開口部形成於上述第3絕緣膜上；在上述步驟(e)中，在上述第1晶片區域中，以使上述第1圖案及上述第2圖案混合存在於上述半導體基板之面內之方式而形成上述再配線，並且在上述第2晶片區域中，形成構成第3圖案之上述再配線，上述第3圖案與上述第1圖案電性分離。
  11. 一種半導體裝置，其中包括設置在半導體基板上之多層配線、以覆蓋上述多層配線之方式設置在上述半導體基板上 之鈍化膜、設置在上述鈍化膜上之再配線、及以覆蓋上述再配線之方式設置在上述鈍化膜上之第1絕緣膜，上述再配線在上述半導體基板之面內具有彼此電性分離之第1圖案及第2圖案，在上述多層配線的最上層配線之一部分上且在上述鈍化膜上所設置之第1開口部中，上述第1圖案各個與上述多層配線電性連接，上述第2圖案與上述多層配線電性分離，在上述第1圖案之一部分上且在上述第1絕緣膜上所設置之第2開口部中，上述第1圖案各個之一部分露出，上述第1圖案與上述第2圖案混合存在於上述半導體基板之面內。
  12. 如請求項11之半導體裝置，其中在上述第2圖案之一部分上且在上述第1絕緣膜上所設置之第3開口部中，上述第2圖案之一部分露出。
  13. 如請求項12之半導體裝置，其中在上述第2圖案之上述一部分上，設置有與上述第2圖案電性連接之凸塊電極。
  14. 如請求項11之半導體裝置，其中在上述第1圖案之上述一部分上，設置有與上述第1圖案電性連接之凸塊電極。
  15. 如請求項11之半導體裝置，其中上述半導體基板構成在 面內具有第1區域及上述第1區域周圍之第2區域之半導體晶片，上述第1圖案設置在上述第2區域上，上述第2圖案設置在上述第1區域及上述第2區域上。
  16. 如請求項11之半導體裝置，其中上述第2圖案之平面形狀為圓形狀或者所有之角為鈍角之多角形狀。
  17. 如請求項11之半導體裝置，其中上述第2圖案之加工尺寸為上述第1圖案之加工尺寸以下。
  18. 如請求項11之半導體裝置，其中上述再配線在上述半導體基板之面內之佔有率為35%以上。
  19. 如請求項11之半導體裝置，其中上述再配線在上述半導體基板之面內之佔有率為60%以下。
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