JP6814698B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6814698B2 JP6814698B2 JP2017110582A JP2017110582A JP6814698B2 JP 6814698 B2 JP6814698 B2 JP 6814698B2 JP 2017110582 A JP2017110582 A JP 2017110582A JP 2017110582 A JP2017110582 A JP 2017110582A JP 6814698 B2 JP6814698 B2 JP 6814698B2
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Description
まず、図18および図19を用いて、本発明者の検討によって明らかになった問題点を検討例として説明する。
本実施の形態および以下の実施の形態の半導体装置は、再配線を備えた半導体装置である。
本実施の形態の半導体装置の構造について、図1および図2を用いて説明する。図1は、本実施の形態の半導体装置である半導体チップの平面レイアウトである。図2は、図1のA−A線における要部断面図である。
本実施の形態における半導体装置の構造の主な特徴は、有機絶縁膜PIQ1とバリアメタル膜BM3との間に、無機材料の絶縁膜IF2が形成されている点である。これによって、有機絶縁膜PIQ1の上面において、バリアメタル膜BM3が有機絶縁膜PIQ1と接することがないので、有機絶縁膜PIQ1を構成するC−H結合とバリアメタル膜BM3が反応してできる導電性の反応生成物RCが形成されない。
本実施の形態における半導体装置の製造方法を、図3〜図13を参照して説明する。図3は第4配線M4とその下層を示す断面図であり、図4〜図13は第4配線M4とその上層の構造を示す断面図である。なお、これらの断面図は図2と同様に、図1のA−A断面に対応している。
図14は実施の形態2における半導体装置の要部断面図であり、図1のA−A線における要部断面図である。実施の形態2では、有機絶縁膜PIQ3と絶縁膜IF3を、実施の形態1の有機絶縁膜PIQ1と絶縁膜IF2に対応するものとして説明する。
BM1、BM2、BM3 バリアメタル膜
CP 半導体チップ
IF1、IF2、IF3 絶縁膜
IL0、IL1、IL2、IL3、IL4、IL5 層間絶縁膜
M1 第1配線
M2 第2配線
M3 第3配線
M4 第4配線
M5 第5配線
MF1、MF2 導電膜
OP0、OP1、OP2、OP3 開口部
PD1 第1パッド電極
PD2 第2パッド電極
PIQ1、PIQ2、PIQ3 有機絶縁膜
PLG プラグ
Q1、Q2 MISFET
RC 反応生成物
RP1、RP2、RP3 レジストパターン
RW 再配線
SD シード層
STI 素子分離領域
SUB 半導体基板
TR 外部接続用の端子
V1、V2、V3、V4 ビア
WL ウエル
Claims (12)
- (a)半導体基板と、前記半導体基板上に形成された多層配線層と、前記多層配線層のうち最上層の配線層に形成された第1パッド電極と、前記第1パッド電極を覆うように形成され、且つ、無機材料からなる第1絶縁膜と、を準備する工程、
(b)前記第1絶縁膜上に第1有機絶縁膜を形成する工程、
(c)前記第1有機絶縁膜上に、無機材料からなる第2絶縁膜を形成する工程、
(d)前記第2絶縁膜上に第1レジストパターンを形成する工程、
(e)前記第1レジストパターンをマスクとしてエッチング処理を行うことで、前記第
1パッド電極上に位置する前記第2絶縁膜を選択的に除去する工程、
(f)前記(e)工程後に、前記第1レジストパターンと、前記第1パッド電極上に位置する前記第1有機絶縁膜とを除去する工程、
(g)前記(f)工程後に、前記第2絶縁膜が残されている状態でエッチング処理を行うことで、前記第1パッド電極上に位置する前記第1絶縁膜を選択的に除去し、前記第1パッド電極に到達する第1開口部を形成する工程、
(h)前記第2絶縁膜上および前記第1開口部内に、前記第1パッド電極と接続する第1バリアメタル膜を形成する工程、
(i)前記第1バリアメタル膜上に第2レジストパターンを形成する工程、
(j)前記第2レジストパターンから露出している領域において、めっき法によって、前記第1バリアメタル膜上に第1導電膜を形成する工程、
(k)前記(j)工程後、前記第2レジストパターンを除去する工程、
(l)前記(k)工程後、前記第1導電膜から露出している領域において、前記第1バリアメタル膜を除去する工程、
(m)前記(l)工程後、前記第1導電膜から露出している領域において、前記第2絶縁膜を除去する工程、
(n)前記(m)工程後、前記第1導電膜を覆うように、前記第1有機絶縁膜上に第2有機絶縁膜を形成する工程、
を有し、
前記第1導電膜から露出している領域において、前記第1有機絶縁膜と前記第2有機絶縁膜とは直接接している、
を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2絶縁膜は、前記第1絶縁膜と異なる材料からなる、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1パッド電極は、第2導電膜と、前記第2導電膜上に形成された第2バリアメタル膜とを含み、
前記(g)工程と前記(h)工程との間に、前記第1開口部の底面において、前記第2バリアメタル膜を除去する工程、を更に有し、
前記(h)工程にて、前記第1バリアメタル膜は、前記第2導電膜と直接接する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1有機絶縁膜は、ポリイミドからなり、
前記第1バリアメタル膜は、チタン、タンタルまたはクロムを含む材料からなり、
前記第1導電膜は、銅を主成分とする材料からなり、
前記第2絶縁膜は、酸化シリコンまたは窒化シリコンを含む材料からなる、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2絶縁膜は、350℃以下のプラズマCVD法を用いて形成される、半導体装置の製造方法。 - (a)半導体基板と、前記半導体基板上に形成された多層配線層と、前記多層配線層のうち最上層の配線層に形成された第1パッド電極と、前記第1パッド電極を覆うように形成され、且つ、無機材料からなる第1絶縁膜と、を準備する工程、
(b)前記第1絶縁膜上に第1有機絶縁膜を形成する工程、
(c)前記第1有機絶縁膜に、前記第1パッド電極に達する第1開口部を形成する工程、
(d)前記第1有機絶縁膜上および前記第1開口部内に、無機材料からなる第2絶縁膜を形成する工程、
(e)前記第2絶縁膜上に第1レジストパターンを形成する工程、
(f)前記第1レジストパターンをマスクとしてエッチング処理を行うことで、前記第1パッド電極上に位置する前記第2絶縁膜を選択的に除去する工程、
(g)前記(f)工程後に、前記第1パッド電極上に位置する前記第1絶縁膜を選択的に除去する工程、
(h)前記(g)工程後に、前記第2絶縁膜上および前記第1開口部内に、前記第1パッド電極と接続する第1バリアメタル膜を形成する工程、
(i)前記第1バリアメタル膜上に第2レジストパターンを形成する工程、
(j)前記第2レジストパターンから露出している領域において、めっき法によって、前記第1バリアメタル膜上に第1導電膜を形成する工程、
を有する、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記第2絶縁膜は前記第1絶縁膜と同じ材料からなり、
前記(f)工程と前記(g)工程は、同じ条件で連続的にエッチング処理が行われる、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記第1パッド電極は、第2導電膜と、前記第2導電膜上に形成された第2バリアメタル膜とを含み、
前記(g)工程と前記(h)工程との間に、前記第1開口部の底面において、前記第2バリアメタル膜を除去する工程、を更に有し、
前記(h)工程にて、前記第1バリアメタル膜は前記第2導電膜と直接接する、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、更に、
(k)前記(j)工程後、前記第2レジストパターンを除去する工程、
(l)前記(k)工程後、前記第1導電膜から露出している領域において、前記第1バリアメタル膜を除去する工程、
を有する、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、更に、
(m)前記(l)工程後、前記第1導電膜から露出している領域において、前記第2絶縁膜を除去する工程、
(n)前記(m)工程後、前記第1導電膜を覆うように、前記第1有機絶縁膜上に第2有機絶縁膜を形成する工程、
を有し、
前記第1導電膜から露出している領域において、前記第1有機絶縁膜と前記第2有機絶縁膜とは直接接している、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記第1有機絶縁膜は、ポリイミドからなり、
前記第1バリアメタル膜は、チタン、タンタルまたはクロムを含む材料からなり、
前記第1導電膜は、銅を主成分とする材料からなり、
前記第2絶縁膜は、酸化シリコンまたは窒化シリコンを含む材料からなる、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記第2絶縁膜は、350℃以下のプラズマCVD法を用いて形成される、半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017110582A JP6814698B2 (ja) | 2017-06-05 | 2017-06-05 | 半導体装置の製造方法 |
CN201810239119.2A CN108987357B (zh) | 2017-06-05 | 2018-03-22 | 半导体装置及其制造方法 |
TW107115517A TWI768040B (zh) | 2017-06-05 | 2018-05-08 | 半導體裝置及其製造方法 |
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