JP6435860B2 - 配線構造体 - Google Patents
配線構造体 Download PDFInfo
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- JP6435860B2 JP6435860B2 JP2014544625A JP2014544625A JP6435860B2 JP 6435860 B2 JP6435860 B2 JP 6435860B2 JP 2014544625 A JP2014544625 A JP 2014544625A JP 2014544625 A JP2014544625 A JP 2014544625A JP 6435860 B2 JP6435860 B2 JP 6435860B2
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- material film
- inorganic material
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- 229910010272 inorganic material Inorganic materials 0.000 claims description 143
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
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Description
図1は、本発明の一実施形態に係る配線構造体の断面図を示す。図1においては、第1層(下層)の配線と第2層(上層)の配線とを接続するための接続孔の断面も含まれている。接続孔は、第1層の配線と第2層の配線とが重畳する領域に配置される。なお、接続孔に配置される第2層の配線の部分をビア接続部という場合がある。
図4は、本発明の実施形態2に係る配線構造体を用いたLSIチップの配置の一例を示す。これは、いわゆる2.5次元実装と呼ばれる配置の一例である。
図8(a)は、本発明の実施形態3に係る配線構造体を用いたLSIチップの配置を示す。これは、いわゆる3次元実装と呼ばれる配置の一例である。
図11は、実施例3にて説明した工程により配線構造体を作成したSiインターポーザーについて、熱サイクル試験を実施したときの不良率を示すグラフである。この熱サイクル試験においては、Siインターポーザーの上面及び下面のそれぞれに、ビア接続部を介した4層からなるスタックビアチェーン(チェーン数:1000)を用いた。−25℃から125℃の温度サイクルを3000回繰り返し、チェーン抵抗が20%以上上昇したとき、その配線構造体は不良である判定した。
Claims (22)
- 第1の配線と、
第2の配線と、
前記第2の配線と前記第1の配線との間に設けられ、前記第2の配線の表面のうち少なくとも前記第1の配線の側の面を覆う無機材料膜と、前記無機材料膜を覆う第1の有機樹脂材料膜と、前記第1の有機樹脂材料膜上に設けられた第2の有機樹脂材料膜を含む第1の絶縁膜と、
前記第2の配線と前記第1の配線との間に設けられ、前記第1の有機材料絶縁膜と前記第2の有機材料絶縁膜との間に設けられた第3の配線と、
前記第1の配線と前記第2の配線とが重畳する領域の前記第1の絶縁膜を上下に貫通するビア接続孔に設けられたビア接続部と、
を備え、
前記ビア接続部は、前記ビア接続孔の底部に露出する前記第2の配線の前記第1の配線側の面上と前記ビア接続孔の内壁上とに配置された第1のバリア導電層を有する、
多層配線構造体。 - 前記無機材料膜は、前記第2の配線の前記ビア接続部に重畳する領域を除く前記第2の配線の上面全面と、前記第2の配線の側面全面とを直接覆い、SiN又はSiCから構成された第1の無機材料膜、及び前記第1の無機材料膜の全面を覆い、SiO2、SiOC
又はSiOFから構成された第2の無機材料膜からなる、請求項1に記載の多層配線構造体。 - 前記第1の無機材料膜の厚さは、前記第2の無機材料膜の厚さよりも薄い、請求項2に記載の多層配線構造体。
- 前記無機材料膜の前記ビア接続孔の内壁側の端部は、前記第1のバリア導電層に接触する、請求項1に記載の多層配線構造体。
- 前記第1の有機樹脂材料膜及び前記第2の有機樹脂材料膜を構成する材料の誘電率の値は、前記無機材料膜を構成する材料の誘電率の値よりも小さい請求項1に記載の多層配線構造体。
- 前記第1の配線と前記第2の配線とが重畳する領域において、前記無機材料膜と前記第1の有機樹脂材料膜との膜厚の合計に対して前記無機材料膜の割合が20%以上80%以下である請求項1に記載の多層配線構造体。
- 前記第1のバリア導電層の材料は高融点金属またはその化合物を含む請求項1に記載の多層配線構造体。
- 前記ビア接続部は、前記第1の配線、前記第2の配線、及び前記第3の配線が重畳する領域に設けられる、請求項1に記載の多層配線構造体。
- 前記ビア接続孔は、
第2の有機樹脂材料膜に設けられ、前記第3の配線の前記第1の配線側の面を露出する第1のビア接続孔と、
前記第1の有機樹脂材料膜及び前記無機材料膜に設けられ、前記第2の配線の前記第3の配線側の面を露出する第2のビア接続孔と、を有し、
前記ビア接続部は、
前記第1のビア接続孔に設けられ、前記第1の配線と前記第3の配線とを接続する第1のビア接続部と、
前記第2のビア接続孔に設けられ、前記第3の配線と前記第2の配線とを接続する第2のビア接続部と、を有し、
前記1のビア接続部は、前記第1のビア接続孔の底部に露出する前記第3の配線の前記第1の配線側の面に配置された第2のバリア導電層が配置されている請求項8に記載の多層配線構造体。 - 前記第1の配線の表面のうち前記第2の配線の側とは反対側の面の少なくとも一部を覆う無機材料膜を含む第2の絶縁膜をさらに備える、請求項1乃至9の何れか一項に記載の多層配線構造体。
- 前記第2の絶縁膜に含まれる無機材料膜は、前記第1の配線の上面の少なくとも一部と、前記第1の配線の側面全面とを直接覆い、SiN又はSiCから構成された第3の無機材料膜、及び前記第3の無機材料膜の全面を覆い、SiO2、SiOC又はSiOFから
構成された第4の無機材料膜からなる、請求項10に記載の多層配線構造体。 - 前記第3の配線と同層に設けられた第4の配線と、
前記第4の配線上に設けられた第5の配線と、
をさらに備え、
前記第4の配線と前記第5の配線との間には、他の配線が配置されていない請求項1に記載の多層配線構造体。 - 前記ビア接続孔は、0.5μm〜20μmの孔径を有し、
前記ビア接続孔の高さは、5μm〜20μmである、請求項1乃至12の何れか一項に記載の多層配線構造体。 - 第1の配線と、
第2の配線と、
前記第2の配線と前記第1の配線との間に設けられ、前記第2の配線の表面のうち少なくとも前記第1の配線の側の面を覆い、前記第2の配線の側面と接する第1の有機樹脂材料膜と、
前記第2の配線と前記第1の配線との間に設けられ、前記第1の有機樹脂材料膜上に設けられた第3の配線と、
前記第1の配線と前記第1の有機樹脂材料膜との間に設けられ、前記第3の配線の表面のうち少なくとも前記第1の配線の側の面を覆う無機材料膜と、前記無機材料膜を覆う第2の有機樹脂材料膜とを含む絶縁膜と、
前記第1の配線と第3の配線とが重畳する領域の前記絶縁膜を上下に貫通するビア接続孔に設けられた第1のビア接続部と、
前記第3の配線と第2の配線とが重畳する領域の前記第1の有機樹脂材料膜を上下に貫通するビア接続孔に設けられた第2のビア接続部と、
を備え、
前記第1のビア接続部は、前記第1のビア接続孔の底部に露出する前記第3の配線上と前記第1のビア接続孔の内壁上とに配置されたバリア導電層を有する、多層配線構造体。 - 前記無機材料膜は、前記第3の配線の前記ビア接続部に重畳する領域を除く前記第3の配線の上面全面と、前記第3の配線の側面全面とを直接覆い、SiN又はSiCから構成された第1の無機材料膜、及び前記第1の無機材料膜の全面を覆い、SiO2、SiOC
又はSiOFから構成された第2の無機材料膜からなる、請求項14に記載の多層配線構造体。 - 前記第1の無機材料膜の厚さは、前記第2の無機材料膜の厚さよりも薄い、請求項15に記載の多層配線構造体。
- 前記無機材料膜の前記第1のビア接続孔の内壁側の端部は、前記バリア導電層に接触する、請求項14に記載の多層配線構造体。
- 前記第1の有機樹脂材料膜及び前記第2の有機樹脂材料膜を構成する材料の誘電率の値は、前記無機材料膜を構成する材料の誘電率の値よりも小さい、請求項14に記載の多層配線構造体。
- 前記第1の配線と前記第3の配線とが重畳する領域において、前記無機材料膜と前記第2の有機樹脂材料膜との膜厚の合計に対して前記無機材料膜の割合が20%以上80%以下である、請求項14に記載の多層配線構造体。
- 前記バリア導電層の材料は高融点金属またはその化合物を含む、請求項14に記載の多層配線構造体。
- 前記第2の配線と同層に設けられた第4の配線と、
前記第4の配線上に設けられた第5の配線と、
をさらに備え、
前記第4の配線と前記第5の配線との間には、他の配線が配置されていない、請求項14に記載の多層配線構造体。 - 前記ビア接続孔は、0.5μm〜20μmの孔径を有し、
前記ビア接続孔の高さは、5μm〜20μmである、請求項14乃至21の何れか一項に記載の多層配線構造体。
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Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014069662A1 (ja) * | 2012-11-05 | 2014-05-08 | 大日本印刷株式会社 | 配線構造体 |
US20160086960A1 (en) * | 2014-09-22 | 2016-03-24 | Texas Instruments Incorporated | Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance |
US9564396B2 (en) * | 2014-09-26 | 2017-02-07 | Taiwan Semiconductor Manufucturing Company, Ltd. | Semiconductor device and process |
JP6361464B2 (ja) * | 2014-10-24 | 2018-07-25 | 富士通株式会社 | 配線構造 |
JP6589277B2 (ja) | 2015-01-14 | 2019-10-16 | 富士電機株式会社 | 高耐圧受動素子および高耐圧受動素子の製造方法 |
JP2017034155A (ja) * | 2015-08-04 | 2017-02-09 | 大日本印刷株式会社 | 表示装置 |
JP6908154B2 (ja) * | 2015-10-28 | 2021-07-21 | 大日本印刷株式会社 | インターポーザ及びインターポーザの製造方法 |
JP6699131B2 (ja) * | 2015-10-28 | 2020-05-27 | 大日本印刷株式会社 | インターポーザ及びインターポーザの製造方法 |
KR102334181B1 (ko) * | 2016-03-25 | 2021-12-03 | 쇼와덴코머티리얼즈가부시끼가이샤 | 유기 인터포저 및 유기 인터포저의 제조 방법 |
TWI698963B (zh) * | 2016-06-03 | 2020-07-11 | 日商大日本印刷股份有限公司 | 貫通電極基板及其製造方法、以及安裝基板 |
US10183258B2 (en) * | 2016-06-30 | 2019-01-22 | L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Metallopolyimide precursor fibers for aging-resistant carbon molecular sieve hollow fiber membranes with enhanced selectivity |
JP6801297B2 (ja) * | 2016-08-26 | 2020-12-16 | 大日本印刷株式会社 | 配線基板及び表示装置 |
WO2018043184A1 (ja) | 2016-08-31 | 2018-03-08 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
FR3061404B1 (fr) * | 2016-12-27 | 2022-09-23 | Packaging Sip | Procede de fabrication collective de modules electroniques hermetiques |
US10332839B2 (en) * | 2017-01-06 | 2019-06-25 | United Microelectronics Corp. | Interconnect structure and fabricating method thereof |
US10707123B2 (en) | 2017-04-28 | 2020-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch profile control of interconnect structures |
JP2019029581A (ja) | 2017-08-02 | 2019-02-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US10651362B2 (en) * | 2017-09-26 | 2020-05-12 | Microsoft Technology Licensing, Llc | Method of forming superconducting apparatus including superconducting layers and traces |
JP7098902B2 (ja) * | 2017-09-29 | 2022-07-12 | 大日本印刷株式会社 | 貫通電極基板 |
JP7334819B2 (ja) * | 2017-12-27 | 2023-08-29 | 大日本印刷株式会社 | 配線基板、および配線基板を有する半導体装置 |
JP7069711B2 (ja) * | 2017-12-27 | 2022-05-18 | 大日本印刷株式会社 | 配線基板、および配線基板を有する半導体装置 |
JP6725095B2 (ja) | 2018-06-21 | 2020-07-15 | 大日本印刷株式会社 | 配線基板および半導体装置 |
JP2019212934A (ja) * | 2019-09-20 | 2019-12-12 | 大日本印刷株式会社 | 表示装置 |
WO2021203415A1 (zh) | 2020-04-10 | 2021-10-14 | 京东方科技集团股份有限公司 | 驱动基板及其制作方法、显示装置 |
JP7248054B2 (ja) * | 2020-04-23 | 2023-03-29 | 大日本印刷株式会社 | インターポーザ及びインターポーザの製造方法 |
KR20220030051A (ko) | 2020-09-02 | 2022-03-10 | 삼성전자주식회사 | 배선 구조체 및 이를 포함하는 반도체 패키지 |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125447A (ja) * | 1988-06-22 | 1990-05-14 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11168141A (ja) * | 1997-12-03 | 1999-06-22 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JP3141844B2 (ja) * | 1998-06-05 | 2001-03-07 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP3501280B2 (ja) | 1998-08-31 | 2004-03-02 | 富士通株式会社 | 半導体装置の製造方法 |
US6420261B2 (en) | 1998-08-31 | 2002-07-16 | Fujitsu Limited | Semiconductor device manufacturing method |
US6479900B1 (en) * | 1998-12-22 | 2002-11-12 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US6656828B1 (en) | 1999-01-22 | 2003-12-02 | Hitachi, Ltd. | Method of forming bump electrodes |
JP2000216264A (ja) | 1999-01-22 | 2000-08-04 | Mitsubishi Electric Corp | Cmos論理回路素子、半導体装置とその製造方法およびその製造方法において用いる半導体回路設計方法 |
JP2000332107A (ja) * | 1999-05-20 | 2000-11-30 | Sony Corp | 半導体装置の製造方法 |
JP4031158B2 (ja) | 1999-09-27 | 2008-01-09 | 株式会社東芝 | 半導体装置 |
US6291331B1 (en) * | 1999-10-04 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue |
JP4683710B2 (ja) * | 1999-11-18 | 2011-05-18 | 株式会社半導体エネルギー研究所 | 液晶表示装置、el表示装置及び電子機器 |
JP3548082B2 (ja) * | 2000-03-30 | 2004-07-28 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
TW531802B (en) | 2000-07-21 | 2003-05-11 | Canon Sales Co Ltd | Semiconductor device and semiconductor device manufacturing method |
JP2002164342A (ja) | 2000-07-21 | 2002-06-07 | Canon Sales Co Inc | 半導体装置及びその製造方法 |
JP2002305193A (ja) | 2001-04-05 | 2002-10-18 | Sony Corp | 半導体装置とその製造方法 |
JP4340729B2 (ja) * | 2002-06-10 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置とその製造方法 |
JP4022180B2 (ja) * | 2002-07-11 | 2007-12-12 | 大日本印刷株式会社 | 多層配線基板の製造方法 |
JP3909283B2 (ja) | 2002-10-31 | 2007-04-25 | 富士通株式会社 | 半導体装置の製造方法 |
US7902062B2 (en) * | 2002-11-23 | 2011-03-08 | Infineon Technologies Ag | Electrodepositing a metal in integrated circuit applications |
JP2005150493A (ja) | 2003-11-18 | 2005-06-09 | Sony Corp | 半導体装置の製造方法 |
JP2005183766A (ja) * | 2003-12-22 | 2005-07-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3910973B2 (ja) * | 2004-04-22 | 2007-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP2006135058A (ja) | 2004-11-05 | 2006-05-25 | Advanced Lcd Technologies Development Center Co Ltd | 銅配線層の形成方法、半導体装置の製造方法 |
JP2006165040A (ja) * | 2004-12-02 | 2006-06-22 | Renesas Technology Corp | 半導体装置及び半導体装置のパターン設計方法 |
JP2006216746A (ja) * | 2005-02-03 | 2006-08-17 | Sony Corp | 半導体装置 |
JP2006324301A (ja) * | 2005-05-17 | 2006-11-30 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路配線構造 |
US20070194450A1 (en) * | 2006-02-21 | 2007-08-23 | Tyberg Christy S | BEOL compatible FET structure |
US8022552B2 (en) * | 2006-06-27 | 2011-09-20 | Megica Corporation | Integrated circuit and method for fabricating the same |
JP2008016502A (ja) * | 2006-07-03 | 2008-01-24 | Sharp Corp | Rf集積回路及びその製造方法 |
US7902643B2 (en) * | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US7470619B1 (en) * | 2006-12-01 | 2008-12-30 | Hrl Laboratories, Llc | Interconnect with high aspect ratio plugged vias |
JP2009088177A (ja) | 2007-09-28 | 2009-04-23 | Sanyo Electric Co Ltd | Siから成る実装基板およびそれを用いた半導体モジュール |
JP2009147218A (ja) * | 2007-12-17 | 2009-07-02 | Toshiba Corp | 半導体装置とその製造方法 |
EP2187439A1 (en) | 2007-12-28 | 2010-05-19 | Ibiden Co., Ltd. | Interposer and interposer manufacturing method |
JP4985411B2 (ja) | 2008-01-08 | 2012-07-25 | 住友電気工業株式会社 | 半導体光素子を作製する方法 |
JP5211730B2 (ja) * | 2008-02-12 | 2013-06-12 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP5007250B2 (ja) | 2008-02-14 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8138577B2 (en) * | 2008-03-27 | 2012-03-20 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Pulse-laser bonding method for through-silicon-via based stacking of electronic components |
JP2010098293A (ja) | 2008-09-22 | 2010-04-30 | Elpida Memory Inc | 半導体装置 |
US9299641B2 (en) * | 2012-08-10 | 2016-03-29 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US8929090B2 (en) | 2010-01-22 | 2015-01-06 | Nec Corporation | Functional element built-in substrate and wiring substrate |
JP5608605B2 (ja) * | 2010-11-05 | 2014-10-15 | 新光電気工業株式会社 | 配線基板の製造方法 |
KR101817159B1 (ko) | 2011-02-17 | 2018-02-22 | 삼성전자 주식회사 | Tsv를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법 |
US8487410B2 (en) * | 2011-04-13 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias for semicondcutor substrate and method of manufacture |
US9219016B2 (en) * | 2011-09-28 | 2015-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure design for 3DIC testing |
JP5857615B2 (ja) | 2011-10-17 | 2016-02-10 | 富士通株式会社 | 電子装置およびその製造方法 |
US9099485B2 (en) * | 2012-03-13 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of guard rings for wafer-level-packaging |
WO2014069662A1 (ja) * | 2012-11-05 | 2014-05-08 | 大日本印刷株式会社 | 配線構造体 |
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US10121748B2 (en) | 2018-11-06 |
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US20200144197A1 (en) | 2020-05-07 |
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US20210313277A1 (en) | 2021-10-07 |
US20200144196A1 (en) | 2020-05-07 |
US20240088040A1 (en) | 2024-03-14 |
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US9735108B2 (en) | 2017-08-15 |
JP6908090B2 (ja) | 2021-07-21 |
US10586768B2 (en) | 2020-03-10 |
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