TWI310969B - Multilayer interconnection substrate, semiconductor device, and solder resist - Google Patents
Multilayer interconnection substrate, semiconductor device, and solder resist Download PDFInfo
- Publication number
- TWI310969B TWI310969B TW095125998A TW95125998A TWI310969B TW I310969 B TWI310969 B TW I310969B TW 095125998 A TW095125998 A TW 095125998A TW 95125998 A TW95125998 A TW 95125998A TW I310969 B TWI310969 B TW I310969B
- Authority
- TW
- Taiwan
- Prior art keywords
- solder resist
- layer
- resin
- layers
- substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims description 90
- 229910000679 solder Inorganic materials 0.000 title claims description 71
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 229920005989 resin Polymers 0.000 claims description 60
- 239000011347 resin Substances 0.000 claims description 60
- 239000004744 fabric Substances 0.000 claims description 31
- 239000011521 glass Substances 0.000 claims description 30
- 239000002759 woven fabric Substances 0.000 claims description 7
- 239000011342 resin composition Substances 0.000 claims description 5
- 239000004519 grease Substances 0.000 claims description 2
- 239000004925 Acrylic resin Substances 0.000 claims 1
- GOOHAUXETOMSMM-UHFFFAOYSA-N Propylene oxide Chemical compound CC1CO1 GOOHAUXETOMSMM-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 66
- 239000011162 core material Substances 0.000 description 17
- 238000005452 bending Methods 0.000 description 13
- 239000010949 copper Substances 0.000 description 12
- 239000012792 core layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
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- 238000002474 experimental method Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
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- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 208000001613 Gambling Diseases 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
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- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4922—Bases or plates or solder therefor having a heterogeneous or anisotropic structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
1310969 -九、發明說明: [相關申請案交互參考] 本申請案基於2006年3月27日提出申請之日本優先 申明案第2006-086562號,該案之全部内容合併於本案作 為參考。 【發明所屬之技術領域】 ' 本發明大體上係關於半導體裝置,更詳言之,係關於 、樹脂材料和使用此種樹脂材料之多層互連基板。 •【先前技術】 近來高性能半導體裝置係使用多層樹脂基板作為封裝 基板而在該基板上載設半導體晶片。 另一方面,用於最近的高性能半導體裝置之半導體晶 片中發生咼溫的產生,因此,在載設了半導體晶片之多層 樹脂基板中有引起彎曲之傾向,該彎曲源自於熱應力。應 /主意的疋半導體晶片相較於樹脂基板有較大的彈性模數。 • 因此,當半導體裝置藉由焊錫凸塊或類似方式安裝在 電路基板上時,半導體晶片產生的熱使得大的應力施加到 該凸塊而引起半導體晶片與封裝基板之間,或者封震基 板〃、電路基板之間之電連接和機械連接受到破壞或損宝之 問題。 為了抑制此種封裝基板之彎曲之問題’已使用了大彈 性模數之多層樹脂基板,其中該大彈性模數之多層樹脂基 板具有以玻璃織物(glass cl〇th)增強之核心層配置在多 層樹脂基板之中心部分之構造。 318403 5 1310969 . 另一方面,利用具有此種厚核心層之封裝基板,將使 基板的厚度增加,然此情況導致譬如在基板上所形成之通 孔-插塞(via-plug)之訊號路徑中的電感增加之問題。由 此’引起了電訊號傳輸率降低之問題。 . 因此,已努力藉由自多層樹脂基板去除核心層以實現 厚度為5 0 0 # in或更小之極薄的多層樹脂基板。 ^參考文獻 專利參考1 ··日本早期公開專利申請案2000-133683 # 專利參考2:曰本早期公開專利申請案u_345898 專利參考3 :日本早期公開專利申請案9_289269 專利參考4 : WOOO/49652公告案 專利參考5 :日本早期公開專利申請案2〇〇2〜187935 專利參考6:日本早期公開專利申請案2〇〇卜127〇95 【發明内容】 第1圖顯示習知具有核心之多層樹脂基板之例子。 Φ 參照第1圖’在樹脂基板11之中心部分設有核心部分 11C,而使核心部分11C包括核心層11(:1和11(:2之疊層, .各110和11C2層具有40至6〇//111之厚度且由摻入了二璃 .織物11G之樹脂層所形成,其中在其上載有互連圖案i2A 和12B之增層(buiid-up)絕緣膜lu和UB係形成於核 心部分lie上。再者,在其上載有互連圖案12c和l2D之 增層絕緣膜11D和ΠΕ係形成於核心部分llc之下。 再者,形成貝穿孔12C以便貫穿過核心部分^丨c而連 接互連層12A和互連層12D。 318403 6 1310969 再者’阻焊膜13A和13B分別形成於最外面的增層絕 緣膜11B和11E上,其中電極墊14A形成於阻焊膜13A内 而電極墊14B形成於阻焊膜13B内。 於如此形成之多層樹脂基板丨丨上,半導體晶片丨5係 .以面朝下狀態安裝,其中半導體晶片15之電極凸塊16係 連接至對應的電極墊14A。再者,填底(underfill)樹脂 層17係填充於半導體晶片15與阻焊膜13 A之間的間隙。 ^ 於樹脂基板11之背面,焊錫凸塊17係形成於電極墊 _ 14B上,用於將由半導體晶片15和多層樹脂基板丨丨所形 成之半導體裝置安裝於電路基板上。 然而 使用具有此種核心部分llc<夕嘈樹脂基板 11’會有包括核心層11(:1和11C2之基板總厚度超過5〇〇以 之情況。一般而言,係使用超過一個核心層,而該等層3 t厚度變彳于大於5〇〇 # m。於此種情況下,由貫穿孔1 %户 ;成且從電極墊1延伸至電極塾⑽之訊號路徑的長肩 亦超過500 # ni,而經由此種長訊號路徑傳輸之訊號經歷矣 遲,結果增加電感值。 .避免此問題之一種方法是去除核心部分lie,如第2 :::不:並減少多層樹脂基板之厚度。然而,使用此種 3核""之所s胃的無核心樹脂基板會導致彈性模數減 =,從對應於提供核心部分之情況之2略減少至 的門題或2因而上述提及之基板f曲和變形變成首要 由:同:元: = 應注意的是先前說明之該等部分係 付號表示,並將省略其說明。 318403 7 1310969 ΓΓ-~~ p年3月奶丨修(彰正替換頁 於載設半導體晶片之樹脂基板已引起彎曲之情況一~-大的應力施加到樹脂基板和安裝有具備樹脂基板之半導體 裝置之電路基板之間的接合部分,並引起接合部 或損害之問題。 -包括: 依照本發明之—紐,絲供了-種多層互連基板, 樹脂疊層結構,其中疊置了複數層增層(bui 1 d-up layer) ’該複數層增層各包括絕緣層和互連圖案;以及 設於該樹脂疊層結構之上表面和下表面之 阻焊層, 乐一 其中,該第一和第二阻焊層各包括在其中之玻璃 物,該玻璃織物包括高開口織造織物(higMy 〇如、 fabric cloth) 〇 . · . . - .於本發明之另m提供了—種半導體裝置,包 多層互連基板;以及 豢在該多層互連基板上以面朝下狀態安裝之半導體晶 片, 日曰 • 該多層互連基板包括: 增層,該複數層增 - 樹脂璺層結構,其中疊置了複數層 層·各包括絕緣層和互連圖宰; 設於該樹赌疊層結構之上表面和下表面之第一 =層’該第—和第二阻焊層各包括在其中之破璃織物 形成於該第一和第二阻焊層之電極墊, 該玻璃織物包括高開口織造織物。 318403(修正版) 8 1310969 ^ v.zip: }:: L_:—一:, 於本發明之另一態樣,係提供了一種阻焊劑,包括: 具有阻焊樹脂組成物之層;以及 玻璃織物,摻入於該阻焊樹脂組成物之該層中, 該玻璃織物包括高開口織造織物。 依照本發明,藉由摻入阻烊劑於破璃混合物(glass cr〇ss)而使該阻烊膜機械性地增強,並改進阻焊膜之彈性 .,數。於是,藉由配置此種堅硬的阻焊膜於無核心增層式 夕層基板之正面和背面,使該無核心增層基板由正面和背 面機械性地增強,而可以減少基板的厚度,並同時保有足 夠之彈性模數。以此種方式,在互連基板令訊號路徑之電 ,值減J ’並成功抑制訊號延遲。由此,應注意的是,阻 ’啤未構成喊路u此由包含於其中之玻離混合物所 造成之轉麟度之增加不會對互連基板之電特性造成任 =不良的影響。雖㈣實上互連基板之厚度減少,但是因 t ^ W ^ ^ f + ^ ^ a ^ ^ a . _ /P chip)女裝於此種互連基板且以此方式安裝之半導 々引起熱產生時,在該互連基板中僅造成些微的變曲 -::由此’在半導體晶片和互連基板之間實現了高可 =了 和機械連接,亦在互連基板和電路基板之間實 -現了尚可罪的電連接和機械連接。、 锡橋5 H賴亦執行習知阻㈣之魏,#如防正焊 (solder bridging). (s〇lder 板:=方止錫銷(solderpot)污染、於組裝時保護基 除鋼互連圖案之氧化或職作用、消除電遷移作用 從下列之詳細說明配合所附圖式閱讀時,將可清楚瞭 3 Ϊ 8403(修正版) 9 1310969 解本發明之其他目的和進一步之特徵。 【實施方式】 第3圖顯示依照本發明之第一實施例之半導體裝置 的架構。 參照第3圖,半導體裝置20係由樹脂多層互連基板 和藉由焊錫凸塊22A以覆晶方式安裝於該樹脂多層互 連基板21上之半導體晶片22所形成,其中,該樹脂多層 癱互連基板21係由疊置了許多增層21Aj2U6之樹脂增層曰 -式層壓板21A所形成,而阻焊層21B和21C係分別形成在 樹脂增層式層壓板21A之上和下表面。各增層21^至2iA6 例如係與Cu互連圖案21Ac以直徑4〇#m之通孔圖案和 30/zm/30/zm之線與間隔(iine_and_Space)圖案之六層 堆疊形式形成。由此,一部分之Cu互連圖案21杬形成穿 透過樹脂增層式層壓板21A之貫穿孔21At。 利用本發明之半導體裝置20,應注意的是複合材料係 籲用於阻焊層21B和21C,於此複合材料中例如彈性模數為 40GPa之玻璃織物21G係由阻焊樹脂化合物所摻入。藉此, 阻知層21B和21C具有1〇至30GPa之彈性模數,譬如 15GPa ’儘管事實上阻焊樹脂組成物本身為習知者,其特性 為2至3 GPa之彈性模數。 以第3圖之架構’此種堅固的阻焊層21β和21C設於 具有小彈性模數之樹脂增層式層壓板21A之正面和背面, 使樹脂增層式層壓板21A由正面和背面機械性地增強。由 此,有效地抑制了基板之彎曲或變形。 318403 10 1310969 再者,在與增層21A6中之互連圖案2Uc接觸之阻焊 :21B中形成電極塾21b之陣歹4,且電極塾…相似地形 、在阻谭層21C中。由此,阻焊層21β和沉執行習知阻 烊膜之功能,譬如防止焊錫橋接、減少焊錫聚集、防止錫 =染、於組裝時賴基板、㈣銅互連㈣之氧化或腐 钱仙、消除電遷移作料。因&,任何用為習知之阻焊
劑之環氧樹脂、丙烯酸_脂或環氧㈣酸g|皆係用為構 成阻焊層21B和21C之樹脂材料。 雖然可想到將含有用於參照第!圖說明之核心材料 1^和11C2之玻璃織物之預浸體(prepreg)同樣使用於 阻焊層21B和21C ’但是設計用為核心層之此等材料用於 阻焊層21B和21C時不能良好地執行阻焊劑之功能。 因此’很難配置習知的核心材料於多層樹脂基板之最 外表面。 .對於玻璃織物21G,較佳為使用高密度之高開口織造 鲁(Mgh open fabric)之平坦玻璃織物。 再者,半導體晶片22為覆晶安裝在電極墊21b上,以 及焊錫凸塊23形成在電極墊21〇:上用來安裝電路基板。 利用此種結構之多層互連基板21,包含玻璃織物之阻 焊層21B和21C係位於形成在樹脂增層式層壓板2iA之訊 號路徑之外側,而因此,使用這種阻焊層21β和2ic不會 引起訊號路徑中電感值增加。雖然阻焊膜21B和2ic由於 摻入了玻璃織物而相較於習知的阻焊膜可具有增加的厚、 度’但是對於通過基板之訊號之傳輸特性沒有實質的影響。 318403 11 1310969 雖然阻焊層2ib和21C較佳係具有4〇//m至60//m之 厚度通吊相等於第1圖之架構之核心層11(:2之厚 度,但是只要厚度不超過約相等於1〇倍該核心層之厚度, 、J不會對夕層互連基板21之電特性造成不良之影響。 • 其次,將參照第4A至4H圖說明第3圖之多層互連基 板21之製程。 參照第4A圖,第一層之Cu互連圖案2Uc形成於Cu ^或ju 口金之支撐構件2〇s上,而第一層之增層絕緣膜 —係藉由真空疊置製程疊置樹脂層而形成,該樹脂層可自 Tomoegawa紙業有限公司購得,商品名稱為TLF_3〇。 接著於f 4B圖之製程,開口 21Av藉由⑽雷射鑽孔 製程形成於增層絕緣膜21^,而Cu晶種層(未圖示)藉 由使用非電解電鑛液而形成於第4B圖結構之整個表面,該 非電解電鍍液可自R0hm and flaas公司購得。 .再者,於第4C圖之步驟,藉由使用ph〇tec ry_3229 瞻(Hitachi化學有限公司之商品名稱),使抗蝕圖案 (reSlst pattern)形成在Cu晶種層上,並藉由執行a 之電解電鍍製程同時使用抗蝕圖案作為遮罩而將開口 _ 21Av填滿銅層。以此種方式,形成銅互連圖案2ΐΑ。應注 意的是第4C圖係顯示藉由電解電鍍製程形成。層後已去 除抗#圖案和不必要的Cu晶種層之狀態。 再者,藉由重複第4A至4C圖之製程,疊置絕緣膜2Ui 至21Ae,並形成包括銅互連圖案21Ac和貫穿孔。奴之 脂增層式層壓板21A ’如第4D圖中所示。 318403 12 1310969 . 其次,於第4E圖之步驟,阻焊層21B形成在樹脂增層 式層壓板21A_L ’其中,阻焊層21β係由接入了阻焊劑之 玻璃織物形成,其中所用阻焊劑可從Taiyo Ink MFG.有限 公司購得’商品名稱為PSR_4_sp。對於此玻璃織物,可 以使用由Asahi Fiberglass有限公司提供之高開口織造玻 璃織物,產品名稱為高開口織造平坦粗紡玻璃(耵扯—〇卩如
Fabric Flat Roving Glass)。 • 再者,於第4F圖之步驟,藉由蝕刻而去除支撐構件 _ 20S並將阻焊層2ic形成在樹脂增層式層壓板21A之下表 面,類似於阻焊層21B。 再者,於第4G圖之步驟,藉由雷射鑽孔製程而在阻焊 層21B中形成開口,與下層互連圖案a或貫穿孔2以七 相致,並且電極墊21b係形成於此開口中。再者,電極 塾21c係形成於此開口中。 將如此形成之多層互連基板21進行彎曲測量。在基板 丨每邊為4么为之情況下,證實彎曲被成功抑制至大約 50#m詳w之’證實於每邊具有h大小且安震半導體晶 片22之區域中,彎曲被抑制至大約2〇"。因此,證實可 以安裝半導體晶片22於此等多層互連基板21而不須使用 加強物(stif;fener)。 再者,對此構造進行熱循環測試,其中,半導體晶片 22以覆晶方式安裝於如此形成之多層互連基板u上,於 具有彈性模數1 〇Gpa之常用填底樹脂(^i ❻ 有限公司之產品名稱⑽—侧3S3)係提供絲作為填充 318403 13 1310969 *半導體晶片22與基板21間之間隙的填底樹脂層22B之狀 態。熱循環測試於-10°c與loot:之間重複300次。結果, 證貫於半導體晶片與多層樹脂基板21之間之電接觸不會 造成譬如剝離(exfoliation)或斷開(diSconnecti〇n) 之缺失。 再者,於半導體晶片22安裝後之狀態中對彎曲進行測 量,證實各邊具有4cm大小之基板中彎曲為1〇〇 # m或更 •少’並不會造成通孔接觸(via-contact)之脫離 _ (detachment)或斷開。 此處’應注意的是填底樹脂層22B可以加入或不加入 填料粒子。 於比較實驗中,使用Taiyo InkMFG·有限公司之相同 的PSR-4000SP阻焊材料於第3圖之結構中,但是並沒有摻 入玻璃織物,觀察到對於各邊具有4cm大小之基板而言, 彎曲的大小從50 之值(摻入了玻璃織物之情況)增加 鲁到300 # m。關於各邊具有2cm大小之晶片安装面積,證實 焉曲從2 0 // m增加到大約1 〇 〇 # m,如此大的彎曲並不允許 安裝半導體晶片22於基板上而不在基板上使用加固物。 於是,於另一個比較實驗中,將上述比較實驗之多層 樹脂互連基板沿著基板的週邊提供以厚度為lmm之Cu加 固物。以此方式,基板之彎曲被抑制至大約1〇〇#m。再者, 藉由使用填底樹脂,以類似方式安裝半導體晶片22,並於 -10°C與1〇〇。(:之間重複熱循環測試300次。於此比較實驗 中’證實於基板和晶片之間造成斷開。 318403 14 1310969 #者’於安裝了半導體晶片之狀態下測量基板之彎 曲,並觀察到在此比較實驗中彎曲高達3〇〇#m,半 片脫離且貫穿孔斷開。. aa ^於此方式,本發明能藉由利用玻璃織物機械性地增強 設於基板之最外表面之阻焊層而有效地抑制無核心多層曰 脂基板之彎曲或變形。 θ 再者,應當注意的是藉由阻焊層含有破璃織物而機械 性增強多層樹脂基板並不限於無核心基板,而是亦有效於 1第1圖之具有核心部分之基板,於該基板之厚度^ 5〇〇“ 或更小且彎曲或變形變成嚴重問題之情況。
因為本發明之阻焊層21Β和21C包含玻璃織物,該等 層之鑽孔製程係由雷射光束處理而進行。因此,阻焊層不 需要具有光敏性。然而,此並不意味著習知的光敏阻^劑 不能使用於本發明。事實上,用於本發明之實施例之阻焊 劑(Taiyo InkMFG.有限公司之PSR-4000sp)為光敏阻焊 再者’本發明並不限於上文說明之實施例,而可在不 偏離本發明之範圍内作各種改變和修飾。 【圖式簡單說明】 第1圖為顯示使用具有依照本發明相關技術之核心之 多層樹脂基板之半導體裝置的結構之圖示; 第2圖為顯示半導體裝置之結構之圖示,其中去除了 第1圖結構中之核心部分; 第3圖為顯示依照本發明實施例之半導體裝置的結構 318403 15 J310969 之圖示; 第4A至4G圖為顯示第3圖之半導體裝置的製程之圖 示。 【主要元件符號說明】 11 基板(多層樹脂基板) 11A、11B、11D、11E 增層(build-up)絕緣膜 11C 核心部分 11 Ci ' 11C2 核心層(核心材料) • 11G 玻璃織物 12A、12B、12C、12D 互連圖案(互連層) 12C 貫穿孔 13A、13B 阻焊膜 14A、14B 電極墊 15 半導體晶片 16 電極凸塊 Φ 17 填底(underfill )樹脂層 17 焊錫凸塊 '20 半導體裝置 '20S 支撐構件 21 (樹脂)多層互連基板 21A 樹脂增層式層壓板 21八]至21人6增層(增層絕緣膜) 21Ac ( Cu)互連圖案 21At 貫穿孔 16 318403 1310969 21Av 開口 21B、21C阻焊層 21b、21c電極墊 21G 玻璃織物 22 半導體晶片 22A 焊錫凸塊 22B 填底樹脂層 焊錫凸塊 23
Claims (1)
- 第95125998號專利申請案 (98年3月25曰) 包括: 1310969、申請專利範圍: 置有複數層增層,該複數層增層 一種多層互連基板 樹脂疊層結構 各包括絕緣層和互連圖案;以及 設於該樹脂疊層結構之上表面和下.表面之第一和 第二阻焊層, 其中’該第-和第二阻焊層各包括在其中之玻璃織 物,該玻璃織物包括高開口織造織物(highiy琴㈣ fabric cloth)。 2·如申請專利範圍帛丨項之多層互連基板,其中,該第一 和第二阻焊層各具有大於該樹脂疊層結構之彈性模數 之彈性模數。 ' 3·如申請專㈣圍第〗項之多層互連基板,其中,韓一 和第二阻焊層各具有1G至瓣a之彈性模數。 1.如申請專利範圍第1項之多層互連基板,其卜該第一 和第二阻焊層各具有30至60# m之厚度。 5.如中請專利範圍第1項之多層互連基板,其中,該多声 互連基板從該第-阻焊層之表面至該第二;= 面具有50—或更小之厚度。 知層之表 6·如:請專利範圍第!項之多層互連基板,其中,該第_ 和弟—阻焊層形成有個別的電極墊。 7.—種半導體裝置,包括: 多層互連基板;以及 在該多層互連基板上以面朝下狀態安裳之半導體 318403(修正版) 18 !310969 , 晶片, 該多層互連基板包括: 樹脂疊層結構’叠置有複數層增層,該複數層增層 各包括絕緣層和互連圖案; s θ a 設於該樹脂疊層結構之上表面和 第二阻焊層’該第一和第二阻焊層各包:表在面其= 織物;以及 形成於該弟一和第二阻焊層之電極塾, 該玻璃織物包括高開口織造織物。 如申請專利範圍第7項之半導體裝置,其中,該第一和 ::阻焊層各具有大於該樹脂疊層結構、之彈:模:: 彈性模數。 9. 如申請專利範圍第7項之半導體裝置,其中, 第二阻焊層各具有10至3〇(?1^之彈性模數。μ 和 10. —種阻焊劑,包括: # 具有阻嬋樹脂組成物之層;以及 • #璃織物’摻人於該阻谭樹脂組成物之該層中, 該玻璃織物包括高開口織造織物。 η·Γ成申物項之阻焊劑,其中,該阻焊樹脂 酸酯。 可%⑽脂、丙烯酸酯樹脂、和環氧丙烯 318403(修正版) 19
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Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100704919B1 (ko) * | 2005-10-14 | 2007-04-09 | 삼성전기주식회사 | 코어층이 없는 기판 및 그 제조 방법 |
JP5335364B2 (ja) * | 2007-10-31 | 2013-11-06 | 三洋電機株式会社 | 素子搭載用基板、半導体モジュール及び携帯機器 |
TWI382502B (zh) * | 2007-12-02 | 2013-01-11 | Univ Lunghwa Sci & Technology | 晶片封裝之結構改良 |
KR100908986B1 (ko) | 2007-12-27 | 2009-07-22 | 대덕전자 주식회사 | 코어리스 패키지 기판 및 제조 방법 |
JP2009218545A (ja) * | 2008-03-12 | 2009-09-24 | Ibiden Co Ltd | 多層プリント配線板及びその製造方法 |
JP5295596B2 (ja) | 2008-03-19 | 2013-09-18 | 新光電気工業株式会社 | 多層配線基板およびその製造方法 |
KR100923883B1 (ko) | 2008-04-25 | 2009-10-28 | 대덕전자 주식회사 | 강도가 부가된 코어 리스 인쇄회로기판 제조 방법 |
KR100956688B1 (ko) | 2008-05-13 | 2010-05-10 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US20100073894A1 (en) * | 2008-09-22 | 2010-03-25 | Russell Mortensen | Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same |
US8389870B2 (en) | 2010-03-09 | 2013-03-05 | International Business Machines Corporation | Coreless multi-layer circuit substrate with minimized pad capacitance |
KR101122140B1 (ko) | 2010-05-11 | 2012-03-16 | 엘지이노텍 주식회사 | 단일층 인쇄회로기판 및 그 제조방법 |
US8742603B2 (en) * | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
JP5444136B2 (ja) * | 2010-06-18 | 2014-03-19 | 新光電気工業株式会社 | 配線基板 |
JP5578962B2 (ja) * | 2010-06-24 | 2014-08-27 | 新光電気工業株式会社 | 配線基板 |
US8461676B2 (en) | 2011-09-09 | 2013-06-11 | Qualcomm Incorporated | Soldering relief method and semiconductor device employing same |
TWI541957B (zh) * | 2012-05-11 | 2016-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其封裝基板 |
CN104105346B (zh) * | 2013-04-15 | 2018-01-30 | 上海嘉捷通电路科技股份有限公司 | 一种带突点焊盘印制板的制造方法 |
JP6161380B2 (ja) * | 2013-04-17 | 2017-07-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
EP2986062B1 (en) * | 2013-05-03 | 2017-04-12 | Huawei Technologies Co., Ltd. | Power control method, device and system |
EP3051583B1 (en) | 2013-09-27 | 2018-09-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method for same |
KR101548816B1 (ko) | 2013-11-11 | 2015-08-31 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP6761224B2 (ja) * | 2014-02-19 | 2020-09-23 | 味の素株式会社 | プリント配線板、半導体装置及び樹脂シートセット |
US20160254220A1 (en) * | 2015-02-26 | 2016-09-01 | Bridge Semiconductor Corporation | Low warping coreless substrate and semiconductor assembly using the same |
JP6832630B2 (ja) * | 2016-03-28 | 2021-02-24 | 富士通インターコネクトテクノロジーズ株式会社 | 配線基板の製造方法 |
KR102185706B1 (ko) * | 2017-11-08 | 2020-12-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10643919B2 (en) | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
JP6915659B2 (ja) * | 2017-12-06 | 2021-08-04 | 味の素株式会社 | 樹脂シート |
KR102257926B1 (ko) | 2018-09-20 | 2021-05-28 | 주식회사 엘지화학 | 다층인쇄회로기판, 이의 제조방법 및 이를 이용한 반도체 장치 |
WO2023157624A1 (ja) * | 2022-02-15 | 2023-08-24 | 凸版印刷株式会社 | インターポーザ、半導体パッケージ及びそれらの製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2830504B2 (ja) * | 1991-05-16 | 1998-12-02 | 松下電工株式会社 | 半導体装置実装用基板 |
CN1202983A (zh) * | 1995-11-28 | 1998-12-23 | 株式会社日立制作所 | 半导体器件及其制造方法以及装配基板 |
JP3158034B2 (ja) * | 1995-12-28 | 2001-04-23 | 太陽インキ製造株式会社 | 光硬化性・熱硬化性ソルダーレジストインキ組成物 |
JP3346263B2 (ja) * | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP3147053B2 (ja) * | 1997-10-27 | 2001-03-19 | 日本電気株式会社 | 樹脂封止型ボールグリッドアレイicパッケージ及びその製造方法 |
US6136497A (en) * | 1998-03-30 | 2000-10-24 | Vantico, Inc. | Liquid, radiation-curable composition, especially for producing flexible cured articles by stereolithography |
JP3661444B2 (ja) * | 1998-10-28 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法 |
EP1030366B1 (en) * | 1999-02-15 | 2005-10-19 | Mitsubishi Gas Chemical Company, Inc. | Printed wiring board for semiconductor plastic package |
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
JP2001073249A (ja) * | 1999-08-31 | 2001-03-21 | Unitika Glass Fiber Co Ltd | プリント配線基板用のガラスクロス |
JP4674340B2 (ja) * | 2000-04-14 | 2011-04-20 | 三菱瓦斯化学株式会社 | プリプレグ及び金属箔張り積層板 |
JP2002026529A (ja) * | 2000-07-03 | 2002-01-25 | Ibiden Co Ltd | 多層プリント配線板 |
JP4845274B2 (ja) * | 2001-02-27 | 2011-12-28 | 京セラ株式会社 | 配線基板及びその製造方法 |
US6988312B2 (en) * | 2001-10-31 | 2006-01-24 | Shinko Electric Industries Co., Ltd. | Method for producing multilayer circuit board for semiconductor device |
JP2003218543A (ja) * | 2002-01-25 | 2003-07-31 | Kyocera Corp | 多層配線基板 |
AU2003222042A1 (en) * | 2002-04-11 | 2003-10-27 | Schenectady International, Inc. | Waterborne printed circuit board coating compositions |
WO2003099934A1 (en) * | 2002-05-24 | 2003-12-04 | Nippon Shokubai Co., Ltd. | Fire retardant resin composition, method of its production, shaped articles comprising the same, and silica |
JP4191055B2 (ja) * | 2004-01-23 | 2008-12-03 | Necエレクトロニクス株式会社 | 多層配線基板の製造方法、及び半導体装置の製造方法 |
SG119379A1 (en) * | 2004-08-06 | 2006-02-28 | Nippon Catalytic Chem Ind | Resin composition method of its composition and cured formulation |
-
2006
- 2006-03-27 JP JP2006086562A patent/JP4929784B2/ja not_active Expired - Fee Related
- 2006-07-14 US US11/486,061 patent/US20070221400A1/en not_active Abandoned
- 2006-07-17 TW TW095125998A patent/TWI310969B/zh not_active IP Right Cessation
- 2006-07-26 KR KR1020060070273A patent/KR100769637B1/ko not_active IP Right Cessation
- 2006-07-27 CN CN2006101075053A patent/CN101047159B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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TW200737380A (en) | 2007-10-01 |
US20070221400A1 (en) | 2007-09-27 |
KR20070096741A (ko) | 2007-10-02 |
JP2007266136A (ja) | 2007-10-11 |
JP4929784B2 (ja) | 2012-05-09 |
CN101047159A (zh) | 2007-10-03 |
CN101047159B (zh) | 2012-02-08 |
KR100769637B1 (ko) | 2007-10-23 |
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