CN1202983A - 半导体器件及其制造方法以及装配基板 - Google Patents
半导体器件及其制造方法以及装配基板 Download PDFInfo
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- CN1202983A CN1202983A CN96198629A CN96198629A CN1202983A CN 1202983 A CN1202983 A CN 1202983A CN 96198629 A CN96198629 A CN 96198629A CN 96198629 A CN96198629 A CN 96198629A CN 1202983 A CN1202983 A CN 1202983A
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Abstract
一种半导体器件,其特征是:半导体芯片(1)是用接合金属(2)粘接到由热膨胀系数与半导体芯片(1)相近的材料构成的热沉(4)的一个面上的;热沉(4)是用弹性模数小于10MPa的硅有机树脂(硅酮)粘接剂(5)粘接到框体(3)上的;在框体(3)上中介环氧树脂粘接剂(6)粘接有TAB载带(9);半导体芯片(1)由弹性模数大于10GPa的密封环氧树脂(8)密封,以保护其不受环境的影响。
Description
技术领域
本发明涉及半导体器件及其制造方法,特别是涉及对具有优良的散热性和可靠性的LSI封装的半导体器件适用且有效的技术。
背景技术
近些年来的最先进的逻辑器件,借助于工作频率的高频化和信号的多位化而实现了高速化。但是,当半导体芯片因高性能化而引出脚增加时,要是用现有的封装,例如,用具有引线框架的封装的话,就会因引线框架加工的限制受到制约,封装尺寸将变大。这样一来,在把封装装配到装配基板上去的时候,封装及其外引线所占有的装配基板的面积就会增加,把功能高集成化了的优点就会减半。此外,消耗功率将因高性能化所带来的工作频率的提高和高集成化所带来的门电路数的增加而增加。象这样由于从半导体芯片中发生大量的热,所以在满足多引出脚化的需要的同时,开发一种具有低热阻的封装构造是必不可少的。在现有的封装中,对从半导体芯片中发生的热的散热对策不够充分。解决这一问题的第1种技术,记述在特开平5-326625号公报中。这种技术使在电路整个面上有连接端子的半导体芯片(LSI)面朝下装配到承载基板上,并用树脂把半导体芯片与承载基板之间的间隙完全填充起来。此外,在半导体芯片的背面上具备有热散布器。
第2种技术记述于特开平6-224246号公报中。该封装包含具有放入备有多个键合焊盘的半导体芯片的空洞的导电基板和在导电基板上叠层的挠性电路。在其上边,含有已形成于布线图形和电路的表面焊盘上的突出电极的区域阵列。此外,在焊盘的下方,含有穿过挠性电路的多个窗口、接地线和在基板上进行的布线图形的走线。向基板上进行的挠性电路的层叠使用了使窗口放进了基板上的接地焊盘的电连接变得容易的导电粘接剂。
第3种技术,记述在特开平4-119653号公报中。这种技术的特征是:其构成为半导体芯片设置于金属板上边,绝缘体层叠于上述金属板上以把上述芯片包围起来;在上述绝缘体表面上,形成有用于得到与装配基板等的外部电路之间的电气导通的布线引线图形。
第4种技术,记述于特开平5-82567号公报中。这种技术具有由在中央部分上开有孔的陶瓷等构成的基板,芯片键合并密封连接到该基板上的TAB-LSI的管帽,填充于上述基板与TAB-LSI之间,使之密闭基板的孔的密封树脂;并因此采用向TAB-LSI的芯片键合处注入树脂对TAB-LSI加压力的办法,使TAB-LSI的芯片键合得以完全进行,且TAB-LSI的整个电路面由密封树脂覆盖起来。
第5种技术,记述于1994年2月28日发行的第602号日经电子学杂志上边。这种技术用散热用的粘接剂使散热板或机盖与半导体芯片相粘接,用TAB载带使半导体芯片和焊接端子相连接。上述TAB载带和半导体芯片被倒装式连接,TAB载带与半导体芯片之间由密封用树脂密封。封装整体的支持是采用用粘接剂把散热板或者机盖与TAB载带粘接到固定板上的办法进行的。
但是,即便是用这些从第1到第5的技术,在解决下述散热特性与可靠性的相反关系上也未成功。这种相反关系是:如果使散热特性优先,则装配后的可靠性将会降低,而如果使装配后的可靠性优先,则不可能得到大的散热特性。
就是说,高散热特性有赖于芯片-封装间的热阻,封装-空气间的热阻。因此,要想得到高散热特性,芯片与封装间的粘接剂及其材料不论哪一方都必须使用导热性高的物质。但是,仅仅使用满足上述条件的材料的话,封装的可靠性不会提高。就是说,本发明人已经弄清楚了下述事实:在从上述第1到第5种技术中所示的封装构造中,对在芯片工作时或向基板上装配芯片时所发生的热所引起的热应力的对策尚不充分。
本发明的目的是提供一种可以使高散热特性与高可靠性得以两立的满足多引出脚化的要求的半导体器件。本发明的其他目的是提供一种可以使高散热特性与高可靠性得以两立的满足多引出脚化的要求的半导体器件。
本发明的上述和其它的目的及新的特征,将会从本说明书的讲述和附图中弄明白。
发明的公开
本发明的半导体器件,半导体芯片用金属接合粘接到热膨胀系数与半导体芯片相近的热沉(散热片)的一面上。该热沉是用弹性模数小于10MPa的硅系的粘接剂与框体粘接的。在上述框体上介以环氧系等的有机系的粘接剂粘接有TAB载带。上述TAB载带与半导体芯片的电极电连接。上述半导体芯片,出于从外部进行保护的目的用弹性模数大于10GPa的环氧系密封树脂密封。
附图的简单说明
图1的剖面图示出了本发明的实施例1的半导体器件;图2的平面图示出了本发明的实施例1的半导体器件;图3的剖面图示出了本发明的实施例1的半导体器件上已经搭载上了散热用的散热片的状态;图4的平面图示出了已装配上本发明的实施例1的半导体器件的装配基板;图5是沿图4的b-b′线剖开的剖面图;图6的工序图示出了本发明的实施例1的半导体器件的制造方法;图7的剖面图示出了本发明的实施例2的半导体器件;图8的剖面图示出了本发明的实施例2的半导体器件;图9的剖面图示出了本发明的实施例2的半导体器件上已经搭载上了散热用的散热片的状态;图10的工序图示出了本发明的实施例2的半导体器件的制造方法;图11的剖面图示出了本发明的实施例2的半导体器件;图12的剖面图示出了本发明的实施例3的半导体器件;图13的剖面图示出了本发明的实施例2的半导体器件上已经搭载上了散热用的散热片的状态;图14的工序图示出了本发明的实施例3的半导体器件的制造方法;;图15的剖面图示出了本发明的实施例4的半导体器件;图16的剖面图示出了本发明的实施例5的半导体器件;图17的剖面图示出了本发明的其它的实施例的半导体器件。
实施本发明的最佳实施例
为了更详细地说明本发明,根据附图进行说明。在用来说明实施例的全部附图中,对具有同一功能的部分,仅赋予同一标号而不进行反复的说明。实施例1
图1是本实施例的半导体器件的剖面图(沿图2的a-a′线剖开的剖面图),图2是该半导体器件的平面图。
本实施例的半导体器件具有BGA(Ball Grid Array,球栅阵列)型的封装。这种封装由下述部分构成:在硅衬底的主面上已形成了门阵列等的逻辑LSI的半导体芯片1,把半导体芯片1围起来的框体(stiffener)3,使在半导体芯片中所发生的热向外部逃逸的热沉4,保护半导体芯片免受外部环境影响的密封树脂8,已在一面上形成了布线10的TAB载带9和本身为外部引出用电极的焊锡突出电极7。构成封装的各个构件的厚度,作为一个例子,其数据如下:半导体芯片1为0.28~0.55mm,框体3为0.10~0.60mm,热沉4为0.10~1.00mm,TAB载带9为0.05~0.125mm。此外,焊锡突出电极7的直径为0.3~0.9mm。
半导体芯片1用Au-Sn共晶合金接合到热沉4的一面的中央部分上。半导体芯片1的接合面是未形成LSI的面。框体3的一面用第1粘接剂5接合到热沉4的一面的周边部分上。TAB载带9用第2粘接剂6接合到框体3的另一面上。TAB载带9的一面上形成的布线10的一端(内引线)与半导体芯片1的电极(图中未画出来)电连接。布线10的一端(内引线)与半导体芯片一起,用密封树脂8进行密封。在TAB载带9的另一面上,以规定的间隔,形成有与布线10已电连接的多个焊锡突出电极7。TAB载带的另一面的未配置焊锡突出电极的区域,已用阻焊剂21覆盖起来。
由于本实施例的封装在热沉4与半导体芯片1之间的接合处使用的是金属(Au-Sn共晶合金2),所以为了确保两者的接合部分的可靠性,用热膨胀系数与半导体芯片1相近的材料构成热沉4。作为具有与半导体芯片1的热膨胀系数(3×10-6/℃)相近,且具有高热导率的材料,例如有Cu-W合金(热膨胀系数:~6×10-6/℃,弹性模数:300GPa)或Fe系合金,富铝红柱石,AlN,炭系的材料(例如金刚石)等。使热沉4和半导体芯片进行接合的金属,也可以是上边说过的Au-Sn共晶合金2以外的金属,例如也可以是Au-Si合金或高熔点的焊锡等。
支持封装的框体3用具有与装配该封装的1基板相近的热膨胀系数的材构成。例如,在装配基板由玻璃环氧系基材(热膨胀系数:10~20×10-6/℃,弹性模数:5~30GPa)构成的情况下,框体3也用玻璃环氧系基材和具有与之相近的热膨胀系数的材料构成。作为框体3的材料,除玻璃环氧系基材外,还可以举出Cu合金系基材或有机系基材等。此外,框体3的形状,并不限定于图示的那些形状,只要是把半导体芯片围起来的形状什么形状都行。例如,采用使多个立方体2个以上进行连接的办法,也可以实现与图示的框体3同样的形状。
使框体3和热沉4进行接合的第1粘接剂5,理想的是用比密封半导体芯片1的密封树脂8的弹性模数还低的材料,例如,弹性模数小于50MPa,更为理想的是用小于10MPa的材料构成。最为理想的是密封树脂8是弹性体(东丽株式会社制‘TX2206’等)。还有,硅系弹性体的热膨胀系数为大约300~×10-6/℃。
使框体3与TAB载带9进行接合的第2粘接剂6,用比第1粘接剂5的弹性模数还高的材料,例如用弹性模数约为500~1000MPa的环氧树脂构成。本身为半导体芯片1与焊锡突出电极7之间的连接手段的TAB载带9,用对已经贴到合成树脂的一面上的铜箔进行刻蚀形成了布线10的柔性带装载体构成。作为合成树脂基材,例如可以用聚亚酰胺(热膨胀系数:5~20×10-6/℃,弹性模数:50~500Mpa)或玻璃环氧系基材,聚脂基材等。
对已形成于TAB载带9上的布线10的一端和半导体芯片1进行密封的密封树脂8,用比使热沉4与框体3进行粘接的上述第1栅接剂5的弹性模数还高的材料,例如用弹性模数为5~30GPa,热膨胀系数为10~300×10-6/℃的环氧系密封树脂构成。最好的是弹性模数为10MGPa以上的环氧系树脂。此外,还可以用弹性模数大于5GPa的苯酚系密封树脂或聚亚酰胺系密封树脂等。
作为将形成于TAB载带9的一面上的外部引出用电极,除焊锡突出电极7之外,还可以利用在区域阵列方式的表面装配中采用的众所周知的各种电极。例如,可以是把柱状或岛状的金属端子接合到基底电极上边的电极,还可以仅仅是基底电极。
倘采用如上所述那样地构成的本实施例的半导体器件,由于使用热导率高的金属材料(Au-Sn共晶合金2)使半导体芯片1和热沉4接合,所以在半导体芯片1中所产生的热,得以高效率地向热沉4传导,对半导体芯片1的散热起到很大的作用。就是说,由于相对于含Ag的有机系粘接剂(Ag膏)的导热率约为1~50W/m,Au-Sn共晶合金2的导热率约为200W/m以上,所以与使用有机系粘接剂的情况下相比,可以大幅度地改善热传导性。此外,由于热沉4与半导体芯片1的热膨胀系数之差已减小,所以可以确保两者的接合部分的可靠性。此外,由于Au-Sn共晶合金2和热沉4中的不论哪一个的热导率都高,所以芯片-散热片间的热阻和封装-空气间的热阻大幅度地降低,可以得到高的散热特性。
此外,倘采用本实施例的半导体器件,由于用比密封树脂8的弹性模数低的,就是说用弹性极限高的粘接剂5使热沉4和框体3粘接,故可以用粘接剂5来吸收·缓和因构成封装的各个构件的热膨胀系数差而产生的应力。这样一来,就可以防止在把封装装配到装配基板上的时候和在LSI工作的时候所发生的热应力引起的封装裂纹或布线10的断线。
还有,倘采用本实施例的半导体器件,由于用弹性模数高的密封树脂8密封半导体芯片1和布线10(内引线),半导体芯片1和布线10(内引线)被密封树脂8牢固地固定,所以可以防止因热应力所引起的布线10(内引线)的断线。
本实施例的封装,如图3所示,由于在热沉4的上部搭载散热用的散热片11,故可以满足更多的引出脚和更高的功耗的LSI的要求。散热片11用Al之类的高热导率的材料构成,用润滑脂(grease)等的粘接剂与热沉4接合。或者,也可以把散热片11螺钉固定到热沉4上。散热片11的厚度或形状没什么限制。例如也可以分割成多个,只要考虑到半导体芯片1的发热量,热沉4的材料物性,制造工艺,制造价格等后选择最佳的厚度和形状即可。
图4的平面图示出了在内置于个人计算机或工作站等内的装配基板20上装配上本实施例的半导体器件的状态之一例,图5是图4中的沿b-b′线剖开的剖面图。
图中的标号12是本实施例的封装,13是例如QFP(Quad FlatPackage,四角扁平封装)等其它的表面装配型封装。在该装配基板20上除去已密封到本实施例的封装12中的门阵列以外,还装配有已密封到QFP、PLCC(Plastic Leaded Chip Carrier,塑料引出脚式芯片载体)等的封装中的MPU、逻辑LSI,或已密封到SOJ(Small Outline J-leadedPackage,小型J形引出脚式封装)中的DRAM。
本实施例的封装12,由于把外部引出用电极(焊锡突出电极7)配置成为2维的阵列状,所以引出脚步距比QFP还宽,装配时的不合格发生率比QFP要低的多。此外,可以与QFP等其它的表面装配型封装一起进行一揽子回流,故易于装配。
此外,本实施例的封装12由于用具有与装配基板20相近的热膨胀系数的材料构成支持封装12的框体3,所以可以防止在LSI的工作时所发生的热应力引起的封装12的挠曲或焊锡突出电极7的破裂,可以提高封装12与装配基板20的连接可靠性。
其次,用图6说明本实施例的半导体器件的组装工序。
首先,如图6(a)所示,在热沉4的一面的周边部分上,用粘接剂5粘接上框体3之后,如图6(b)所示,在热沉4的一面的中央部分上用Au-Sn共晶合金2接合半导体芯片1。或者,也可以在把半导体芯片1接合到热沉4上之后,粘接框体3。应用Au-Sn共晶合金2的接合温度为320℃,10分钟。在用Au-Sn共晶合金2以外的金属,例如用Au-Si合金或高熔点的焊锡的情况下的接合温度,分别为370℃,约2分钟,300℃,约10分钟。
其次,如图6(c)所示,在已粘接到热沉4上的框体3的另一面上,用第1粘接剂6粘接TAB载带9。框体3与TAB载带9之间的粘接,用众所周知的热压焊方式进行。接着,如图6(d)所示,把已形成于TAB载带9上的布线10的一端(内引线)键合到半导体芯片1的电极上。在用一缆子键合(gang bonding)方式进行的情况下,最好是先在半导体芯片1的电极上边形成好Au或焊锡的突出电极7。一缆子键合的温度条件为500℃,约一秒。另一方面,在单个键合方式的情况下,也可以在半导体芯片1上边不形成突出电极。
其次,如图6(e)所示,在用密封树脂8把半导体芯片1和布线10(内引线)的一端进行密封之后,如图6(f)所示,在TAB载带9上形成焊锡突出电极7并与布线10电连接。要形成焊锡突出电极7的话,先把焊锡球接合到TAB载带9上,再用比焊锡的熔融温度还高的温度进行回流。
此外,焊锡突出电极7的形成,虽然可以如上所述在封装的组装的最后工序中进行,但也可以在把封装装配到装配基板上去之前进行。
本实施例的半导体器件,由于在半导体芯片1的电极与布线10之间的连接中使用的是TAB载带9,所以可以把布线10一缆子键合到半导体芯片1的电极上。因此,键合所需要的时间与引出脚数无关,可以在短时间内完成。
此外,本实施例的封装12,由于用具有与装配基板20相近的热膨胀系数的材料构成支持封装12的框体3,所以可以防止在LSI的工作时所发生的热应力引起的封装12的挠曲或焊锡突出电极7的破裂,可以提高封装12与装配基板20的连接可靠性。实施例2
图7的剖面图示出了本实施例的半导体器件。
上述实施例1的封装,把TAB载带9粘接到支持封装的框体3上,然后使已形成于该TAB载带9上的布线10与半导体芯片1的电极电连接,但本实施例的封装在框体14上形成布线10并介以金属丝15使该布线10与半导体芯片1的电极电连接。
半导体芯片1,用Au-Sn共晶合金2接合到热沉4的一面的中央部分上。半导体芯片1的接合面是没有形成LSI的面。热沉4用具有与半导体芯片相近的热膨胀系数,且具有高的热传导性的材料,例如Cu-W合金、Fe系合金,富铝红柱石,AlN,炭系的材料(例如金刚石)等构成。使热沉4和半导体芯片接合的金属,也可以是Au-Sn共晶合金2以外的金属,例如也可以是Au-Si合金或高熔点的焊锡等。
框体14的一面,用粘接剂51到热沉4的一面的周边部分上。半导体芯片1和金属丝15用密封树脂8密封。在框体14的下表面上以规定的间隔形成有已与布线10电连接的多个焊锡突出电极7。
支持封装的框体14,用具有与将装配该封装的装配基板相近的热膨胀系数材料,例如热膨胀系数为10~20×10-6/℃,弹性模数为10~20GPa的玻璃环氧系基材等构成,其厚度作为一个例子,为0.20~1.00mm。框体14在金属丝15所连接的区域与将形成焊锡突出电极7的区域之间设置有台阶,使得在用密封树脂8对半导体芯片1进行密封之际把金属丝15也完全地密封起来。该台阶被做得把半导体芯片1包围起来。
接合框体14和热沉4的第1粘接剂5,理想的是用比密封半导体芯片1的密封树脂8的弹性模数还低的材料,例如,弹性模数小于50MPa,更为理想的是用小于10MPa的材料构成。最为理想的是密封树脂8是弹性体。密封半导体芯片1和金属丝15的密封树脂8,用比上述粘接剂5的弹性模数还高的材料,例如用弹性模数为5~30GPa以上的苯酚系密封树脂或聚压酰胺系密封树脂等构成。特别理想的是弹性模数为10GPa以上的环氧系密封树脂。形成于框体14的下表面上的外部引出用电极,除焊锡突出电极7之外,还可以利用在区域阵列方式的表面装配中采用的众所周知的各种电极。例如,可以是把柱状或岛状的金属端子接合到基底电极上边的电极,还可以仅仅是基底电极。
倘采用如上述那样地构成的本实施例的半导体器件,由于使用热导率高的金属材料(Au-Sn共晶合金2)使半导体芯片1和热沉4接合,所以在半导体芯片1中所产生的热得以高效率地向热沉4传导,对半导体芯片的散热起到很大的作用。此外,由于热沉4与半导体芯片1的热膨胀系数之差已减小,所以可以确保两者的接合部分的可靠性。此外,由于Au-Sn共晶合金2和热沉4中的不论哪一个的热导率都高,所以芯片-散热片间的热阻和封装-空气间的热阻被大幅度地降低,可以得到高的散热特性。
此外,倘采用本实施例的半导体器件,由于用比密封树脂8的弹性模数低的,就是说用弹性极限高的粘接剂5使热沉4和框体14粘接,故可以用粘接剂5来吸收·缓和因构成封装的各个构件的热膨胀系数差而产生的应力。这样一来,就可以防止在把封装装配到装配基板上的时候和在LSI工作的时候所发生的热应力引起的封装裂纹或布线10的断线。
还有,倘采用本实施例的半导体器件,由于用弹性模数高的密封树脂8密封半导体芯片1和金属丝15,半导体芯片1和金属丝15被密封树脂8牢固地固定,所以可以防止因热应力所引起的金属丝15的断线。
此外,倘采用本实施例的半导体器件,由于用具有与装配基板20相近的热膨胀系数的材料构成支持封装12的框体14,所以可以防止在LSI的工作时所发生的热应力引起的封装12的挠曲或焊锡突出电极7的破裂,可以提高封装与装配基板的连接可靠性。
本实施例的半导体器件,与上述实施例1的封装不同,由于不使用TAB载带9所以可以减少元件个数和组装工时。因此,与实施例1的封装相比,可以降低封装的造价。此外,如图8所示,在使在框体14的下表面的金属丝15所连接的区域与形成焊锡突出电极7的区域之间不设置台阶的情况下,框体14的构造变得简单,从而可以降低其造价,故还可以进一步降低封装的造价。
本实施例的封装,如图9所示,由于在热沉4的上部搭载散热用的散热片11,故可以满足更多的引出脚和更高的功耗的LSI的要求。散热片11用Al之类的高热导率的材料构成,用润滑脂(grease)等的粘接剂与热沉4进行接合。或者,也可以把散热片11螺钉固定到热沉4上。散热片11的厚度或形状没什么限制。例如也可以分割成多个,只要考虑到半导体芯片1的发热量,热沉4的材料物性,制造工艺,制造价格等后选择最佳的厚度和形状即可。
其次,用图10说明本实施例的半导体器件的组装工序。
首先,如图10(a)所示,在热沉4的一面的周边部分上,用粘接剂5粘接上框体14之后,如图10(b)所示,在热沉4的一面的中央部分上用Au-Sn共晶合金2接合半导体芯片1。或者,也可以在把半导体芯片1接合到热沉4上之后,粘接框体14。
其次,如图10(c)所示,用自动键合机,由金属丝15把半导体芯片1的电极和框体14的布线10连接起来之后,如图10(d)所示,用密封树脂8对半导体芯片1和金属丝15进行密封,接着,如图10(e)所示,在框体14的下表面上形成焊锡突出电极7。这时如图11所示,采用对密封树脂的厚度进行调整,使得在密封树脂8的下表面与框体14之间不产生台阶的办法,使封装的下表面变得平坦,把焊锡求接合到框体14的下表面上的作业变得容易起来。焊锡突出电极7的形成虽然可以在封装的组装的最终的工序中进行,但是也可以在把封装装配到装配基板上去之前进行。实施例3
图12是本实施例的半导体器件的剖面图。
本实施例的封装,用粘接剂6把在两面上已形成了布线10的柔软载带(或者TAB载带)19粘接到框体3的一面上,并介以焊锡突出电极16使该柔软载带19的布线10与半导体芯片1的电极电连接。半导体芯片1和焊锡突出电极16用在被热沉4、框体3和柔软载带19围起来的区域上已无间隙地填充好的密封树脂8与外部隔绝。
柔软载带19的基材,与上述实施例1的TAB载带一样,是聚亚酰胺基材、玻璃环氧系基材、聚脂基材等等。已形成于柔软载带19的两面上的布线10、10,介以通孔18电连接。柔软载带19的一面的布线10与另一面的布线10变成为互相重叠的布局,因此因在布线10中流动的电流的电学特性而产生电磁感应,通过它们的相互作用而被联结,起到降低电感的作用。在柔软载带19的中央部分处,设有用于从外部向被热沉4、框体3和柔软载带19围起来的空腔区域注入密封树脂8的通孔19。在柔软载带19的下表面上,以规定的间隔,形成了与布线10电连接的多个焊锡突出电极7。
半导体芯片1,用Au-Sn共晶合金2(或者,Au-Si合金或高熔点焊锡等)接合到热沉4的一面的中央部分上。此外,支持封装的框体3的一面,用弹性模数低的粘接剂5粘接到热沉4的一面的周边部分上。框体3、热沉4、粘接剂5和6,用与上述实施例1相同的材料构成。
倘采用如上述那样地构成的本实施例的半导体器件,则和上述实施例1、2一样,封装的可靠性、散热性和装配到装配基板上时的连接可靠性将提高。
此外,本实施例的封装,如图13所示,由于把散热用的散热片11搭载于热沉4的上部,所以可以满足更多的引出脚、更高的功耗的LSI的要求。
其次,用图14说明本实施例的半导体器件的组装工序。
首先,如图14(a)所示,用倒装芯片方式使半导体芯片1与柔软载带19电连接。接着,如图14(b)所示,用第1粘接剂5把框体3粘接到热沉4的一面的周边部分上。其次,如图14(c)所示,用Au-Sn共晶合金2把半导体芯片1接合到热沉4的一面的中央部分上,同时,用第2粘接剂6把柔软载带19粘接到已经粘接到热沉4上的框体3的另一面上。其次,如图14(d)所示,通过已形成于柔软载带19上的通孔17向空腔区域内无间隙地填充上密封树脂8后,如图14(e)所示,在柔软载带19上形成焊锡突出电极7并与布线10电连接。实施例4
图15是本实施例的半导体器件的剖面图。
密封半导体芯片1的密封树脂8和弹性模数低的硅系的粘接剂5,相互的粘接性不太好。于是,在本实施例中,减少粘接剂5的量并向热沉4的接合部分的一部分上填充密封树脂8的一部分(图中用箭头表示的部位)。这样一来,由于框体3和热沉4和密封树脂8的接触面积变大,故可以防止密封树脂8的剥离,改善封装的可靠性。实施例5
图16是本实施例的半导体器件的剖面图。
如上述实施例2的图8的封装所示,在使在连接框体14的下表面的金属丝15的区域和形成焊锡突出电极7的区域之间不设置台阶的情况下,为了使金属丝15不从密封树脂8中露出来,必须把密封树脂8填充得很厚。在这样的情况下,采用在空腔区域的周围的框体上设置围堰22的办法,就可以容易地进行密封树脂8的填充作业。实施例6
图17是本实施例的半导体器件的剖面图。
本实施例的封装,用硅胶构成密封树脂8,并用Al制的外壳密封材料23密封该硅胶。即便是在这样的构造的封装中,采用用弹性模数低的粘接剂5把热沉4粘接到框体3上的办法,也可以使因构成封装的各个构件的热膨胀系数差而产生的应力由粘接剂5来吸收·缓和,故可以防止在把封装装配到装配基板上去的时候和在LSI工作的时候发生的热应力引起的封装裂纹或金属丝15的断线。
此外,在框体3上,介以环氧系粘接剂6粘接上了TAB载带9。半导体芯片1,为了不受来自外部的影响,是用弹性模数大于10GPa的环氧系树脂8密封的。
以上,对本发明人的发明根据实施例具体地进行了说明,但是本发明并不受限于上述实施例,在不背离其宗旨的范围内,当然会有种种变更的可能性。工业上利用的可能性
如上所述,本发明的半导体器件,具有使高散热性和高可靠性得以两立的封装构造,是一种特别适用于BGA型封装置半导体器件。
Claims (42)
1、一种半导体器件,具有用金属接合接合到热沉的一面的中央部分上的半导体芯片,粘接到上述热沉的一面上以把体芯片围起来的框体,形成于上述框体的一面上的焊锡突出电极,使上述焊锡突出电极与上述半导体芯片电连接的连接装置,和密封上述半导体芯片的密封树脂,其特征是:上述热沉用与半导体芯片的热膨胀系数相近的材料构成,上述框体和上述热沉是用弹性模数比上述密封树脂低的粘接剂粘接的。
2、权利要求1所述的半导体器件,其特征是:上述粘接剂的弹性模数在50Mpa以下。
3、权利要求1所述的半导体器件,其特征是:上述粘接剂的弹性模数在10Mpa以下。
4、权利要求2所述的半导体器件,其特征是:上述密封树脂的弹性模数在5Gpa以上。
5、权利要求2所述的半导体器件,其特征是:上述密封树脂的弹性模数在10Gpa以上。
6、权利要求1所述的半导体器件,其特征是:上述粘接剂由硅系弹性体构成。
7、权利要求1所述的半导体器件,其特征是:上述框体,用与装配半导体器件的装配基板的热膨胀系数相近的材料构成。
8、权利要求1所述的半导体器件,其特征是:在上述框体和上述热沉之间的接合部分的一部分处填充有上述密封树脂的一部分。
9、权利要求1所述的半导体器件,其特征是:散热用的散热片连接到上述热沉上。
10、权利要求1所述的半导体器件,其特征是:上述密封树脂由硅胶构成,且是用外壳密封材料密封的。
11、权利要求1所述的半导体器件,其特征是:在上述密封树脂的开放端的周围设有围堰。
12、权利要求1所述的半导体器件,其特征是:连接上述焊锡突出电极和上述半导体芯片的上述连接装置是上述TAB载带。
13、权利要求12所述的半导体器件,其特征是:形成于上述TAB载带上的多条布线与上述半导体芯片多个电极,是用热压焊方式被一揽子连接。
14、权利要求12所述的半导体器件,其特征是:在上述热沉上连接有散热用的散热片。
15、权利要求12所述的半导体器件,其特征是:上述粘接剂的弹性模数在50Mpa以下。
16、权利要求12所述的半导体器件,其特征是:上述粘接剂的弹性模数在10Mpa以下。
17、权利要求15所述的半导体器件,其特征是:上述密封树脂的弹性模数在5Gpa以上。
18、权利要求15所述的半导体器件,其特征是:上述密封树脂的弹性模数在10Gpa以上。
19、权利要求1所述的半导体器件,其特征是:连接上述焊锡突出电极与上述半导体芯片的上述连接装置是金属丝。
20、权利要求19所述的半导体器件,其特征是:上述金属丝的一端被键合到已形成于上述框体上的布线上。
21、权利要求19所述的半导体器件,其特征是:使得在上述框体的下表面的连接上述金属丝的区域和形成上述焊锡突出电极的区域之间不设置台阶。
22、权利要求19所述的半导体器件,其特征是:在上述密封树脂的开放端的周围设有围堰。
23、权利要求19所述的半导体器件,其特征是:在上述热沉上连接有散热用的散热片。
24、权利要求19所述的半导体器件,其特征是:上述粘接剂的弹性模数在50Mpa以下。
25、权利要求19所述的半导体器件,其特征是:上述粘接剂的弹性模数在10Mpa以下。
26、权利要求24所述的半导体器件,其特征是:上述密封树脂的弹性模数在5Gpa以上。
27、权利要求24所述的半导体器件,其特征是:上述密封树脂的弹性模数在10Gpa以上。
28、权利要求1所述的半导体器件,其特征是:连接上述焊锡突出电极和上述半导体芯片的电极的上述连接装置,是在两面上已形成了布线的柔软载带。
29、权利要求28所述的半导体器件,其特征是:上述布线和上述半导体芯片的电极是介以形成于上述半导体芯片的主面上的焊锡突出电极电连接的。
30、权利要求28所述的半导体器件,其特征是:上述柔软载带的一面的布线与另一面的布线,被布局为至少一部分互相重叠。
31、权利要求28所述的半导体器件,其特征是:在上述热沉上连接有散热用的散热片。
32、权利要求28所述的半导体器件,其特征是:上述粘接剂的弹性模数在50Mpa以下。
33、权利要求28所述的半导体器件,其特征是:上述粘接剂的弹性模数在10Mpa以下。
34、权利要求32所述的半导体器件,其特征是:上述密封树脂的弹性模数在5Gpa以上。
35、权利要求32所述的半导体器件,其特征是:上述密封树脂的弹性模数在10Gpa以上。
36、一种半导体器件,具有用金属接合接合到热沉的一面的中央部分上的半导体芯片,粘接到上述热沉的一面上以把体芯片围起来的框体,形成于上述框体的一面上的焊锡突出电极,使上述焊锡突出电极与上述半导体芯片电连接的连接装置,密封上述半导体芯片的硅胶,和对上述半导体芯片和上述硅胶进行密封的外壳密封材料,其特征是:上述热沉用与半导体芯片的热膨胀系数相近的材料构成,上述框体和上述热沉是用弹性模数比上述密封树脂低的粘接剂粘接的。
37、权利要求36所述的半导体器件,其特征是:连接上述焊锡突出电极和上述半导体芯片的电极的上述连接装置是金属丝。
38、一种半导体器件的制造方法,具有用金属把半导体芯片接合到热沉的一面的中央部分上的工序;用粘接剂把框体粘接到上述热沉的一面上,以把上述半导体芯片围起来的粘接工序;在上述框体的一面上形成焊锡突出电极,并使上述焊锡突出电极与上述半导体芯片的电极电连接的工序;用密封树脂对述半导体芯片进行密封的工序的,其特征是:上述热沉用与半导体芯片的热膨胀系数相近的材料构成,上述框体和上述热沉是用弹性模数比上述密封树脂低的粘接剂粘接的。
39、权利要求38所述的半导体器件的制造方法,其特征是:用第2粘接剂把TAB载带粘接到上述框体的另一面上,并介以形成于上述TAB载带上的布线,使上述焊锡突出电极与上述半导体芯片的电极电连接。
40、权利要求38所述的半导体器件的制造方法,其特征是:介以形成于上述框体上的布线和键合到上述布线与上述半导体芯片的电极之间的金属丝,电连接上述焊锡突出电极和上述半导体芯片的电极。
41、权利要求38所述的半导体器件的制造方法,其特征是:采用用第2粘接剂把TAB载带粘接导上述框体的另一面上,并把上述半导体芯片倒装式连接到形成于上述TAB载带上的布线上的办法,使上述焊锡突出电极和上述半导体芯片的电极电连接。
42、一种装配基板,其特征是:权利要求1所述的半导体器件和与上述半导体器件不同的表面装配型封装是用一揽子回流法装配的,且是用热膨胀系数与上述半导体器件的上述框体相近的材料构成的。
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- 1996-09-27 CN CN96198629A patent/CN1202983A/zh active Pending
- 1996-09-27 US US09/077,190 patent/US6404049B1/en not_active Expired - Fee Related
- 1996-09-27 WO PCT/JP1996/002815 patent/WO1997020347A1/ja not_active Application Discontinuation
- 1996-09-27 AU AU70966/96A patent/AU7096696A/en not_active Abandoned
- 1996-09-27 KR KR1019980703650A patent/KR19990067623A/ko not_active Application Discontinuation
- 1996-09-27 EP EP96932027A patent/EP0865082A4/en not_active Withdrawn
- 1996-11-26 TW TW085114590A patent/TW322611B/zh active
-
2002
- 2002-01-16 US US10/046,258 patent/US6621160B2/en not_active Expired - Fee Related
- 2002-01-16 US US10/046,204 patent/US6563212B2/en not_active Expired - Fee Related
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CN1319138C (zh) * | 2002-02-07 | 2007-05-30 | 自由度半导体公司 | 封装的半导体器件的形成方法 |
CN100382298C (zh) * | 2002-12-20 | 2008-04-16 | Nxp股份有限公司 | 电子器件及其制造方法 |
CN100472739C (zh) * | 2004-11-08 | 2009-03-25 | Tel艾派恩有限公司 | 铜互连布线和形成铜互连布线的方法 |
CN102376611A (zh) * | 2010-07-28 | 2012-03-14 | 日东电工株式会社 | 半导体背面用膜、半导体背面用切割带集成膜、用于生产半导体器件的方法和半导体器件 |
CN102376611B (zh) * | 2010-07-28 | 2015-08-05 | 日东电工株式会社 | 半导体背面用膜、半导体背面用切割带集成膜、用于生产半导体器件的方法和半导体器件 |
US9293387B2 (en) | 2010-07-28 | 2016-03-22 | Nitto Denko Corporation | Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device |
CN103021973A (zh) * | 2012-12-12 | 2013-04-03 | 中国电子科技集团公司第五十八研究所 | 一种集成电路气密性封装散热结构 |
CN105428321A (zh) * | 2015-12-23 | 2016-03-23 | 中国电子科技集团公司第十三研究所 | 一种气密性芯片倒装安装用陶瓷焊盘阵列外壳结构 |
CN105428321B (zh) * | 2015-12-23 | 2019-01-04 | 中国电子科技集团公司第十三研究所 | 一种气密性芯片倒装安装用陶瓷焊盘阵列外壳结构 |
CN109390290A (zh) * | 2017-08-08 | 2019-02-26 | 太阳诱电株式会社 | 半导体组件 |
Also Published As
Publication number | Publication date |
---|---|
US20020105070A1 (en) | 2002-08-08 |
AU7096696A (en) | 1997-06-19 |
TW322611B (zh) | 1997-12-11 |
US6404049B1 (en) | 2002-06-11 |
US6563212B2 (en) | 2003-05-13 |
EP0865082A1 (en) | 1998-09-16 |
WO1997020347A1 (en) | 1997-06-05 |
US20020066955A1 (en) | 2002-06-06 |
KR19990067623A (ko) | 1999-08-25 |
US6621160B2 (en) | 2003-09-16 |
EP0865082A4 (en) | 1999-10-13 |
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