TW201513242A - 晶片及晶片製造方法 - Google Patents
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Abstract
本發明係關於一種晶片(1),具有一改良之裂痕偵測結構,用於該晶片之一既定區,其包括一導電路徑(5,6),圍繞該既定區之一周邊設置,以及該路徑(5,6)第一末端處之一第一焊墊(17a)、與該路徑(5,6)第二末端處之一第二焊墊(17b),其中該導電路徑(5,6)包含有至少一第一路徑區段(12),設於該晶片(1)之前側,及至少一第二路徑區段(13),設於該晶片(1)之背側,其中該至少一第一路徑區段(12)與該至少一第二路徑區段(13)係藉至少一貫通連接件(14)而連結。更,本發明係關於一種各別系統整合封裝,以及一種製造一各別晶片及一各別系統整合封裝之方法。
Description
本發明係關於一種晶片及系統整合封裝,以及一種晶片及系統整合封裝製造方法。
3維系統封裝(system-in-package)技術(以下:系統整合封裝(system-on-package))包含將多重半導體晶片或晶圓依一垂直方式疊積。為使體積最小化,垂直疊積需在晶圓明顯薄化後去框以分離晶片,或在某些實例中,需在晶圓層疊積後去框。晶圓薄化製程及去框製程二者中之應力,可引發細小微裂痕,此係潛在缺陷,可造成長期裂痕傳播、最終導致系統整合封裝在後續封裝、運輸或現場使用一已封裝產品之階段無功能。在大多數情況下,該微裂痕係產生自晶片邊緣,且經一段時間後傳播通過該晶片。裂痕可在晶片二側上產生,且可逐漸傳播。標準功能性結構測試無法用作微裂痕之測試。
已知存有一種結構,藉由在前端晶圓處理期間植入或金屬化達成,可調整成適應於偵測晶片前側上之早期裂痕起始部位。除此之外,增加絕緣層上矽晶圓及晶片之使用,亦可減慢裂痕傳播。但產生自背部而暫時中止於氧化層(絕緣)介面之一裂痕,可傳播且在後續使用現場中使晶片破裂。
更,已知為減少在背磨、去框或二者組合期間發生微裂痕,
可使用目視檢查,但其不易或不可能在建構一系統整合封裝時即實施。
美國專利案第US 6,649,986 B1號揭露一種半導體裝置,其
包含偵測晶片或複數晶片裂痕用結構,該或該等裂痕係在生產期間切割晶圓時,發生於半導體晶片中。該已知結構包括多重金屬化墊,及晶片或複數晶片裂痕偵測互連點,該墊與互連點二者環繞該半導體裝置之中心區域,其中該互連點係容置於晶片頂側上,作為偵測裂痕用之一單一連續結構,該裂痕係發生於半導體晶片頂表面側上且自該處起延伸。在另一具體實施例中,該結構包括一晶片裂痕偵測擴散層作為晶片裂痕偵測互連點,其中該擴散層係容置於邊界表面附近、場效應區下方之一區域中,可譬如藉摻雜入半導體基板所需區域中後之貫通擴散(through-diffusion)而加工。該擴散層係連接至,位於該半導體裝置頂部上之複數個偵測端子。該具體實施例容許偵測主要發生於半導體晶片底表面側上、且自該處起延伸之晶片/複數晶片裂痕。
美國專利案第US 2009/0201043 A1號關於一種用於半導體
裝置之裂痕感測器,其中該裂痕感測器包括一導體結構,形成如連續線,其沿該半導體裝置整個周邊區域,延伸於內部區域與一切割線區域之間。
該已知感測器包括一導電結構,其具有設於一第一半導體材料層中之複數個第一部、與設於一第二導電材料層中之複數個第二部,其中該複數個第一部係藉由一第三金屬化層中之通孔而連結至該複數個第二部至少其中之一。
上述構想特別提出,發源於一半導體裝置前側上,或在其
前側互連點疊積內之裂痕。然而,由於裂痕可發源於晶片二側上,且可傳播通過整個剖面,因此需一裂痕偵測技術,其係針對很可能隨內含於系統整合封裝技術中之重要背側處理而發生、發源於晶片二側上之裂痕。
可藉具申請專利範圍第1項特徵之一晶片,及具申請專利範
圍第5項特徵之一系統整合封裝,解決以上問題。更,可藉依據申請專利範圍第6項及第7項特徵之一製造個別晶片用方法,及製造一系統整合封裝用方法,解決該問題。
明確地,本發明晶片具有一裂痕偵測結構,用於該晶片之一既定區,其包括一導電路徑,圍繞該既定區之一周邊設置,以及該路徑第一末端處之一第一焊墊,與該路徑第二末端處之一第二焊墊,其中該導電路徑包含有至少一第一路徑區段,設於該晶片之前側,譬如一介電層上方之晶圓基板頂側,及至少一第二路徑區段,設於該晶片之背側,譬如晶圓基板背側,其中該至少一第一路徑區段與該至少一第二路徑區段係藉至少一貫通連接件而連結。
本發明之一鍊型結構解決方案具有優點,即其可針對晶片二側上之缺陷,而不論裂痕缺陷部位之起源,及其容許移除具初生破裂之功能部。
當一裂痕傳播,且到達導電路徑之其中一元件時,該路徑之電阻將明顯增加,且因此可使用該第一與該第二焊墊提供一裂痕偵測。
可藉多重晶片疊積對此作一延伸,其中該鍊係連接至多重疊積晶片,以允許測試一已封裝3維系統整合封裝中、發源於邊緣處之裂痕。
在一較佳具體實施例中,該導電路徑係由設於該晶片前側處之複數個第一金屬區段與設於該晶片背側處之複數個第二金屬區段、以及複數個貫通連接件組成,其中該第一金屬區段與該第二金屬區段係容置成,使一第一金屬區段之第二末端藉一貫通連接件而連結至一第二金屬區段之第一末端,及一第二金屬區段之第二末端係藉另一貫通連接件而連結至次一第一金屬區段之第一末端。此中,該某一第二金屬區段與該次一第一金屬區段未連結至第一或第二焊墊。
以上所解說之較佳具體實施例係指以上所解說發明之一低成本解決方案,其具有關於製造程序之優點。
在另一具體實施例中,至少一第一路徑區段及至少一第二路徑區段形成一雙路徑結構,其具有一內導電路徑及一外導電路徑。較佳地,該內導電路徑之第一末端係連結至該外導電路徑之第一末端及一第一焊墊,且該內導電路徑之第二末端係連結至該外導電路徑之第二末端及一第二焊墊。此中,當考慮橫向時,該內導電路徑係位於周邊區域內之內側處。當考慮橫向時,該外導電路徑係位於周邊區域內之外側處。每一內導電路徑及外導電路徑皆具有,相同於大致描述於上之導電路徑結構。依據本具體實施例之結構更昂貴,但提供更高之可能性,可偵測到源自於晶片二側之裂痕。
又一優點為,倘該雙路徑結構之貫通連接件係設為,可形成一偏置型態,而可能偵測一較大區域中之裂痕。此意味該內與外路徑之貫通連接件係交替地設置。
本發明之解決方案尚關於一種系統整合封裝,包括複數個
晶片,其中每一該等晶片包括上述特徵,其中一第一晶片之第一焊墊係連結至一鄰接晶片之第一焊墊,及該第一晶片之第二焊墊係連結至該鄰接晶片之第二焊墊。
本發明製造一晶片之方法,包括以下步驟:a.提供一晶圓基板,其具有一陣列晶片,較佳地包括在該晶圓基板頂側之一介電層,其中每一該晶片各包括一既定區,在此裂痕可發生於各別晶片中,b.在每一晶片之頂側、譬如該介電層之上,沿每一晶片既定區之一周邊區段,加工一裂痕偵測結構之至少一第一路徑區段,其較佳地結合前側電路元件,c.薄化/背磨該晶圓基板,藉以建立一薄晶圓基板,其上具多重晶片,d.在每一晶片處使用複數貫通晶片通孔並以一合適金屬建立且填滿複數貫通連接件,以容許電氣連接至每一晶片之各鄰接第一路徑區段,e.在每一晶片之背側上、較佳地該晶圓基板之一背側處,沿每一晶片既定區之一周邊區段,加工至少一第二路徑區段,其可作動以與各別鄰接貫通連接件形成一電氣連接,以完成晶片周邊裂痕偵測器,這意味如此可在每一晶片處建立一導電路徑,包括該至少一第一路徑區段、該貫通連接件及該至少一第二路徑區段,f.在每一晶片處加工一第一焊墊與一第二焊墊,其各位於該晶片之該至少一第一路徑區段、該貫通連接件及該至少一第二路徑區段所形成之該導電路徑某一末端處,及g.較佳地使用一金鋼石鋸或雷射切割機,自該晶圓去框而得每一晶片。
明確地,該晶片之周邊區較易於破裂,因此該既定區較佳地位於周邊上。可依任何積體電路製程製造積體電路(譬如矽上互補金屬氧化物半導體(CMOS on Si)、砷化鎵上金屬半導體場效電晶體(MESFET’s on GaAs)、或發明所屬技術領域中具有通常知識者已知之其他積體電路製程。)
貫通晶片通孔用之一合適金屬係銅、金、鋁、鎢或包含有至少一該金屬之一合金。
該晶圓背側上之至少一第二路徑區段,較佳地係使用積體電路工業中一般之加成/脫除製程(譬如微影、蝕刻)加工。
藉上述發明方法,可能在薄化/背磨該晶圓基板(步驟c)前或後,在(步驟d)中建立且填滿該貫通晶片通孔。
本發明製造一系統整合封裝之方法包括以下步驟:A.加工一第一晶片及至少一第二晶片,其待依上述方法封裝,B.為該第一晶片及該至少一第二晶片加工一第一互連點,電氣連結至該第一焊墊,及一第二互連點,電氣連結至該第二焊墊,及C.藉對正且疊積該第一晶片與該至少一第二晶片以建構該系統整合封裝,使該第一晶片之該第一互連點電氣連接至該至少一第二晶片之該第一互連點,及該第一晶片之該第二互連點電氣連接至該至少一第二晶片之該第二互連點。
該至少一第一路徑區段及該至少一第二路徑區段可製作成金屬線,其譬如為銅、鋁、金或其一合金。
可譬如藉銲點凸塊或銅柱技術,達成該至少一互連點之加工,以容許周邊裂痕偵測結構自該第一晶片連接至該至少一第二晶片。
可藉譬如熱壓接合,達成該晶片之相互接合。
以下之不同具體實施例說明中將提出,指引發明所屬技術領域中具有通常知識者之本發明一完整且有用說明,包含其最佳模式。是以,存有進一步特徵與優點,其為無關於申請專利範圍中所界定標的之本發明一部份。
1‧‧‧第一晶片
1’‧‧‧第二晶片
1”‧‧‧第三晶片
1a‧‧‧第一晶片1內部區段
1b‧‧‧第一晶片1周邊區段
5‧‧‧內導電路徑
6‧‧‧外導電路徑
11‧‧‧介電層
12‧‧‧第一金屬區段
12a‧‧‧第一金屬區段12第一末端
12b‧‧‧第一金屬區段12第二末端
13‧‧‧第二金屬區段
13a‧‧‧第二金屬區段13第一末端
13b‧‧‧第二金屬區段13第二末端
14‧‧‧貫通連接件
17a‧‧‧第一焊墊
17b‧‧‧第二焊墊
19‧‧‧第一晶片1晶圓基板
20a‧‧‧第一互連點
20a’‧‧‧第一互連點
20a”‧‧‧第一互連點
20b‧‧‧第二互連點
20b’‧‧‧第二互連點
20b”‧‧‧第二互連點
詳細說明係關於隨附圖式,概略地顯示:第1圖係一本發明晶片之上視圖,第2圖係以一剖面顯示第1圖之本發明晶片,第3圖係以一透視圖顯示第1圖之本發明晶片,及第4圖係以一透視圖顯示一本發明系統整合封裝。
第1圖至第3圖係描述一本發明晶片1之一具體實施例,其具有一內部區域1a,用於導電結構與電氣模組,及一周邊區域1b。晶片1尚包括一晶圓基板19,及在晶片基板19頂側上之一介電層11。
在恰遠離去框製程所致切口之周邊區域1b中,晶片1包括一雙路徑結構,具有一內導電路徑5及一外導電路徑6,其每一個各包括,位於晶片1前側之複數個第一金屬區段12、及位於晶片1背側之複數個第二金屬區段13。內導電路徑5之第一末端與外導電路徑6之第一末端係連接至一第一焊墊17a,且內導電路徑5之第二末端與外導電路徑6之第二末端係連接至一第二焊墊17b,其中第一焊墊17a與第二焊墊17b形成雙導電路徑5、6所屬之焊墊。
內導電路徑5及外導電路徑6之第一金屬區段12與第二金屬區段13係如第2圖剖面中所顯示,相似地藉複數個貫通連接件14連結,如此某一第一金屬區段12之一第二末端12b係藉一貫通連接件14連結至一第二金屬區段13之一第一末端13a,且該第二金屬區段13之一第二末端13b係藉一貫通連接件14連結至,一相鄰第一金屬區段12之一第一末端12a,及諸如此類者。
依據第1圖至第3圖中所顯示之具體實施例,第一金屬區段12係容置於介電層11頂部上。更,如特別顯示於第1圖所描述晶片1之左手側與右手側者,貫通連接件(貫通矽通孔金屬)14係依一偏置型態容置。如此意味貫通連接件14並非沿該圖式之水平方向呈平行,而具偏移。
邊緣上無任何裂痕之一晶片1在經由第一與第二焊墊17a、17b作量測時,具有一正常、較低電阻,而晶片1邊緣上之一裂痕可造成導電路徑5及/或6開路或具較高電阻。
為對一系統整合封裝提供一裂痕偵測,焊墊17a與17b可連接至該系統上方疊積晶片之各別焊墊,如第4圖中所顯示。藉此,可能在單一步驟中,為整個系統整合封裝進行一裂痕偵測用電阻量測。
因此,可藉譬如打線、銅柱、或導電環氧樹脂等技術加工複數個互連點,以容許連接至焊墊17a、17b,使一第一互連點20a電氣且機械地連接至第一焊墊17a,及一第二互連點20b電氣且機械地連接至第二焊墊17b(請參閱第3圖)。
類似於以上說明地加工一第二晶片1’及一第三晶片1”,其各包括一第一互連點20a’、20a”及一第二互連點20b’、20b”。
現在,藉由對正且疊積第一晶片1、第二晶片1’、與第三晶片1”,建構如第4圖中所描述之系統整合封裝。該互連點係藉譬如熱壓接合等技術而電氣地連接,使第一晶片1之第一互連點20a連接至第二晶片1’之第一互連點20a’,及該第二晶片之第一互連點20a’連接至該第三晶片之第一互連點20a”。類似地,第一晶片1之第二互連點20b連接至第二晶片1’之第二互連點20b’,及該第二晶片之第二互連點20b’連接至該第三晶片之第二互連點20b”。第4圖係顯示,下方晶片如何連接至頂部晶片,藉以建立一大型三維菊鍊。藉此,可使用跨越墊20a”與20b”間之一電阻量測,偵測該鍊任何鍊結中之一裂痕引發破裂。
在又一具體實施例中,該導電路徑相對晶片邊緣之距離將最小化達,積體電路(IC)之微影與貫通通孔生成能力、及晶片分離技術之限制。例如,該距離可最小化達~1微米或更小。可經由一特徵及去框製程之公差分析,決定該最小可達成邊緣距離,再以程序試驗確認。除此以外,第一金屬區段12、第二金屬區段13及貫通連接件14之寬度應最小化,以當一微裂痕衝擊到偵測線時,即容許最高程度之電阻變化。倘有需要時,該等數值可如微影技術所容許者(2013年起為30毫微米)一樣小。其中,第一金屬區段12及第二金屬區段13之寬度係個別金屬區段在垂直於晶片1頂或背表面之方向上之尺寸。對比地。貫通連接件14之寬度係該元件平行於晶片1頂或背表面之尺寸。
該提出之測試結構係提供改良之晶片破裂偵測,及針對具微裂痕之晶片或系統整合封裝獲同意為良品時,提供一更高程度之保證。
11‧‧‧介電層
12‧‧‧第一金屬區段
12a‧‧‧第一金屬區段12第一末端
12b‧‧‧第一金屬區段12第二末端
13‧‧‧第二金屬區段
13a‧‧‧第二金屬區段12第一末端
13b‧‧‧第二金屬區段13第二末端
14‧‧‧貫通連接件
19‧‧‧第一晶片1晶圓基板
Claims (7)
- 一種晶片(1),具有一裂痕偵測結構,用於該晶片之一既定區,其包括一導電路徑(5,6),圍繞該既定區之一周邊設置,以及該路徑(5,6)第一末端處之一第一焊墊(17a)、與該路徑(5,6)第二末端處之一第二焊墊(17b),其中該導電路徑(5,6)包含有至少一第一路徑區段(12),設於該晶片(1)之前側,及至少一第二路徑區段(13),設於該晶片(1)之背側,其中該至少一第一路徑區段(12)與該至少一第二路徑區段(13)係藉至少一貫通連接件(14)而連結。
- 根據申請專利範圍第1項所述之晶片(1),其中該導電路徑係由設於該晶片前側處之複數個第一金屬區段(12)與設於該晶片背側處之複數個第二金屬區段(13)、以及複數個貫通連接件(14)組成,其中該第一金屬區段(12)與該第二金屬區段(13)係容置成,使某一第一金屬區段(12)之一第二末端(12b)藉某一貫通連接件(14)而連結至某一第二金屬區段(13)之一第一末端(13a),及該某一第二金屬區段(13)之一第二末端(13b)係藉另一貫通連接件(14)而連結至次一第一金屬區段(12)之一第一末端(12a)。
- 根據前述任一項申請專利範圍所述之晶片(1),其中該至少一第一路徑區段(12)及該至少一第二路徑區段(13)形成一雙路徑結構,其具有一內導電路徑(5)及一外導電路徑(6)。
- 根據申請專利範圍第3項所述之晶片,其中該內導電路徑(5)之第一末端係連結至該外導電路徑(6)之第一末端及一第一焊墊(17a),及其中該內導電路徑(5)之第二末端係連結至該外導電路徑(6)之第二末端及一第二焊墊(17b)。
- 一種系統整合封裝,包括複數個晶片(1,1’,1”),其中每一晶片包括前述任一項申請專利範圍所述之特徵,其中一第一晶片(1)之第一焊墊(17a)係連結至一鄰接晶片(1’)之第一焊墊,及該第一晶片(1)之第二焊墊(17b)係連結至該鄰接晶片(1’)之第二焊墊,其較佳地各經由一互連點(20a,20a’,20a”,20b,20b’,20b”)達成。
- 一種製造一晶片(1)之方法,包括以下步驟:a.提供一晶圓基板(19),其具有一陣列晶片(1,1’,1”),其中每一晶片各包括一既定區,在此裂痕可發生於各別晶片中,b.在每一晶片之頂側,沿每一晶片既定區之一周邊區段(1b),加工一裂痕偵測結構之至少一第一路徑區段(12),c.薄化/背磨該晶圓基板(19),d.在每一晶片處使用複數貫通晶片通孔並以一合適金屬建立且填滿複數貫通連接件(14),以容許電氣連接至每一晶片之各鄰接第一路徑區段(12),e.在每一晶片之背側上、較佳地該晶圓基板(19)之一背側處,沿每一晶片既定區之一周邊區段,加工至少一第二 路徑區段(13),其可作動以與各別鄰接貫通連接件(14)形成一電氣連接,f.在每一晶片處加工一第一焊墊(17a)與一第二焊墊(17b),其各位於該晶片之該至少一第一路徑區段(12)、該等貫通連接件(14)、及該至少一第二路徑區段(13)所形成之該導電路徑(5,6)某一末端處,及g.較佳地使用一金鋼石鋸或雷射切割機,自該晶圓去框而得每一晶片(1,1’,1”)。
- 一種製造一系統整合封裝之方法,包括以下步驟:A.加工一第一晶片(1)及至少一第二晶片(1’,1”),其待依根據申請專利範圍第6項之方法封裝,B.為每一該第一晶片(1)及該至少一第二晶片(1’,1”)加工一第一互連點(20a,20a’,20a”),電氣連結至該第一焊墊(17a),及一第二互連點(20b,20b’,20b”),電氣連結至該第二焊墊(17b),及C.藉對正且疊積該第一晶片(1)與該至少一第二晶片(1’,1”)以建構該系統整合封裝,使該第一晶片(1)之該第一互連點(20a)電氣連接至該至少一第二晶片(1’)之該第一互連點(20a’),及該第一晶片(1)之該第二互連點(20b)電氣連接至該至少一第二晶片(1’)之該第二互連點(20b)。
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US6649986B1 (en) * | 2002-06-18 | 2003-11-18 | Oki Electric Industry Co, Ltd. | Semiconductor device with structure for die or dice crack detection |
JP3998647B2 (ja) * | 2004-02-12 | 2007-10-31 | 株式会社東芝 | 半導体チップおよび半導体チップのテスト方法 |
JP2005277338A (ja) * | 2004-03-26 | 2005-10-06 | Nec Electronics Corp | 半導体装置及びその検査方法 |
US7791070B2 (en) * | 2005-11-02 | 2010-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device fault detection system and method |
JP2007305739A (ja) * | 2006-05-10 | 2007-11-22 | Nec Electronics Corp | 半導体装置 |
JP4949733B2 (ja) * | 2006-05-11 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2008021864A (ja) * | 2006-07-13 | 2008-01-31 | Nec Electronics Corp | 半導体装置 |
US9601443B2 (en) * | 2007-02-13 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structure for seal ring quality monitor |
US20110221460A1 (en) * | 2010-03-10 | 2011-09-15 | Heinrich Trebo | Integrated Circuit Arrangement Having a Defect Sensor |
US8193039B2 (en) * | 2010-09-24 | 2012-06-05 | Advanced Micro Devices, Inc. | Semiconductor chip with reinforcing through-silicon-vias |
US8421073B2 (en) * | 2010-10-26 | 2013-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC) |
JP2012243910A (ja) * | 2011-05-18 | 2012-12-10 | Elpida Memory Inc | 半導体チップのクラックのチェックテスト構造を有する半導体装置 |
US20130009663A1 (en) * | 2011-07-07 | 2013-01-10 | Infineon Technologies Ag | Crack detection line device and method |
JP6054029B2 (ja) * | 2011-12-22 | 2016-12-27 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体チップおよび半導体装置 |
US9287184B2 (en) * | 2013-12-13 | 2016-03-15 | Micron Technology, Inc. | Apparatuses and methods for die seal crack detection |
US9741667B2 (en) * | 2015-04-10 | 2017-08-22 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated circuit with die edge assurance structure |
KR102417143B1 (ko) * | 2015-04-29 | 2022-07-05 | 삼성디스플레이 주식회사 | 표시 장치 |
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WO2015028213A1 (en) | 2015-03-05 |
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