TWI533415B - 半導體製程 - Google Patents
半導體製程 Download PDFInfo
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- TWI533415B TWI533415B TW103108020A TW103108020A TWI533415B TW I533415 B TWI533415 B TW I533415B TW 103108020 A TW103108020 A TW 103108020A TW 103108020 A TW103108020 A TW 103108020A TW I533415 B TWI533415 B TW I533415B
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- 239000004065 semiconductor Substances 0.000 title claims description 122
- 238000000034 method Methods 0.000 title claims description 36
- 239000002184 metal Substances 0.000 claims description 210
- 229910052751 metal Inorganic materials 0.000 claims description 210
- 238000012360 testing method Methods 0.000 claims description 75
- 239000000758 substrate Substances 0.000 claims description 43
- 150000002739 metals Chemical class 0.000 claims description 35
- 238000005520 cutting process Methods 0.000 claims description 13
- 239000000523 sample Substances 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 55
- 239000000463 material Substances 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000012634 fragment Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- SZUVGFMDDVSKSI-WIFOCOSTSA-N (1s,2s,3s,5r)-1-(carboxymethyl)-3,5-bis[(4-phenoxyphenyl)methyl-propylcarbamoyl]cyclopentane-1,2-dicarboxylic acid Chemical compound O=C([C@@H]1[C@@H]([C@](CC(O)=O)([C@H](C(=O)N(CCC)CC=2C=CC(OC=3C=CC=CC=3)=CC=2)C1)C(O)=O)C(O)=O)N(CCC)CC(C=C1)=CC=C1OC1=CC=CC=C1 SZUVGFMDDVSKSI-WIFOCOSTSA-N 0.000 description 1
- 229940126543 compound 14 Drugs 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
本發明係關於3D半導體封裝之領域,且更特定而言,係關於用以促進導電通路(conductive via)之測試的技術及結構。
在堆疊式晶片封裝中,可以垂直堆疊方式將多個積體電路晶片封裝於單一封裝結構中。此情形增加堆疊密度而使封裝結構較小,且常常縮短信號必須在晶片之間橫穿之路徑的長度。因此,堆疊式晶片封裝傾向於增加晶片之間或之中的信號傳輸速度。另外,堆疊式晶片封裝允許將具有不同功能之晶片整合於單一封裝結構中。使用矽穿孔(Through Silicon Via,TSV)因其可在晶片之間提供短垂直導電路徑的能力而成為在實現堆疊式晶片封裝整合方面之關鍵技術。
通常,在TSV製造製程中,自半導體晶圓之底表面蝕刻半導體晶圓以形成複數個通路孔(Via Hole),使得曝露半導體晶圓之最底圖案化金屬層(亦即,「金屬1」(M1))。接著,將導電金屬電鍍於通路孔,以便形成矽穿孔(TSV)。接著,切割半導體晶圓以形成半導體晶粒。在一些狀況下,在半導體晶圓之蝕刻製程期間,蝕刻劑可能未精確地蝕刻半導體晶圓,使得一些通路孔將不達到最底圖案化金屬層(M1)。在其他狀況下,在導電金屬之電鍍製程期間,可能未良好地控制電鍍參數,使得導電金屬之厚度不均勻,且一些導電金屬將不接觸最底圖
案化金屬層(M1)。以上兩種狀況將引起TSV之導電金屬在電鍍製程中不會完美地終止(stop)於最底圖案化金屬層(M1)上,且在導電金屬與最底圖案化金屬層(M1)之間形成開路。然而,僅在對半導體晶粒執行測試後才發現此類不當缺陷,此意謂僅在已將半導體晶圓切割成半導體晶粒後才發現此類不當缺陷。
本發明之一態樣係關於一種半導體封裝。在一實施例中,該半導體封裝包括:一半導體晶粒,其包含一基板;複數個介電層,其設置於該基板上;一積體電路,其包括設置於該等介電層之間且彼此電性連接之複數個圖案化金屬層;及至少一金屬片段(Metal Segment),其與該積體電路隔絕且自該半導體晶粒之一側表面(Lateral Side Surface)曝露。在此實施例中,該至少一金屬片段設置於為該等介電層中之最底介電層的一介電層上,至少一金屬片段及該積體電路之一最底圖案化金屬層各自具有一下表面,且該等下表面實質上共平面,且該半導體晶粒進一步包含至少一導電通路(Conductive Via)。
本發明之另一態樣係關於一種半導體晶圓。在一實施例中,該半導體晶圓包括一基板,該基板被劃分成複數個晶粒區域及複數個渠溝區域(Trench Area);其中每一該等晶粒區域中包括一積體電路,該積體電路具有設置於介電層之間且彼此電性連接之複數個圖案化金屬層;且其中該等渠溝區域設置於該等晶粒區域之間,且至少一金屬片段設置於該渠溝區域中且與一鄰近晶粒區域之該積體電路隔絕。在此實施例中,該至少一金屬片段設置於一最底介電層上,且該至少一金屬片段及一最底圖案化金屬層在同一層處共平面。
本發明之另一態樣係關於一種半導體製程。在一實施例中,該半導體製程包含:(a)提供一半導體晶圓,該半導體晶圓具有一基板、至少一金屬片段、複數個積體電路及複數個介電層,其中該至少
一金屬片段、該等積體電路及該等介電層設置於該基板之一頂表面上,每一該等積體電路包括設置於該等介電層之間且彼此電性連接之複數個圖案化金屬層,且該至少一金屬片段與該等積體電路隔絕;(b)自該基板之一底表面形成複數個測試孔及內孔,以分別曝露該至少一金屬片段及該積體電路之一最底圖案化金屬層;(c)在該等測試孔及該等內孔中形成複數個導電金屬,其中該等測試孔中之該等導電金屬彼此分離;及(d)探測二個測試孔中的至少二個導電金屬。該半導體晶圓被界定為複數個晶粒區域及複數個渠溝區域,每一該等晶粒區域具有每一該等積體電路,且該等渠溝區域設置於該等晶粒區域之間。在一實施例中,該至少一金屬片段設置於該渠溝區域中。在一替代實施例中,該至少一金屬片段設置於該等晶粒區域中。在一實施例中,該至少一金屬片段可設置於一最底介電層上,該至少一金屬片段及該積體電路之一最底圖案化金屬層在同一層處共平面。在步驟(c)中,該等導電金屬可電鍍於每一該等測試孔之一側壁及每一該等內孔之一側壁上。此外,在步驟(c)中,該等導電金屬可填滿該等測試孔及該等內孔,該等測試孔中之該等導電金屬可進一步延伸至該基板之該底表面,以形成在步驟(d)中用以探測之複數個測試部分,且該等測試孔中之該等導電金屬可接觸該至少一金屬片段,且該等內孔中之該等導電金屬接觸該積體電路之該最底圖案化金屬層。該半導體製程進一步包括一沿著該等渠溝區域切割該半導體晶圓以形成複數個半導體晶粒之步驟。在該切割製程(Sawing Process)期間,可移除該至少一金屬片段及該等測試孔中之該等導電金屬。
1‧‧‧半導體封裝
3‧‧‧半導體晶粒
3a‧‧‧半導體晶粒
4‧‧‧半導體晶圓
4a‧‧‧半導體晶圓
4b‧‧‧半導體晶圓
4c‧‧‧半導體晶圓
11‧‧‧封裝基板
12‧‧‧焊線
14‧‧‧封膠體
16‧‧‧焊料層
20‧‧‧積體電路
22‧‧‧測試孔
24‧‧‧內孔
26‧‧‧導電金屬
27‧‧‧測試通路
28‧‧‧導電通路
29‧‧‧探針
30‧‧‧實際切割路徑
30a‧‧‧實際切割路徑
31‧‧‧側表面
40‧‧‧基板
42‧‧‧晶粒區域
44‧‧‧渠溝區域
46‧‧‧金屬片段
46a‧‧‧金屬片段
46b‧‧‧金屬片段
46c‧‧‧金屬片段
51‧‧‧第一探測路徑
52‧‧‧第二探測路徑
53‧‧‧第三探測路徑
54‧‧‧第四探測路徑
111‧‧‧頂表面
112‧‧‧底表面
201‧‧‧最底圖案化金屬層
202‧‧‧第二圖案化金屬層
203‧‧‧第三圖案化金屬層
204‧‧‧互連金屬
261‧‧‧測試部分
271‧‧‧測試通路
272‧‧‧測試通路
273‧‧‧測試通路
274‧‧‧測試通路
275‧‧‧測試通路
276‧‧‧測試通路
277‧‧‧測試通路
278‧‧‧測試通路
401‧‧‧頂表面
402‧‧‧底表面
421‧‧‧凹口
461‧‧‧接墊部分
462‧‧‧連接部分
463‧‧‧突起部分
481‧‧‧最底介電層
482‧‧‧第二介電層
483‧‧‧第三介電層
484‧‧‧第四介電層
4821‧‧‧開口
4831‧‧‧開口
4841‧‧‧開口
圖1說明根據本發明之一實施例的半導體封裝之剖面圖;圖2至圖16說明根據本發明之一實施例的用於製造半導體晶粒之製程;
圖17說明根據本發明之另一實施例的用於製造半導體晶粒之製程;圖18及圖19分別說明根據本發明之另一實施例的半導體晶粒之仰視圖及側視圖;圖20說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖;圖21說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖;圖22說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖;及圖23說明根據本發明之另一實施例的金屬片段之半導體晶圓探測的部分放大仰視圖。
參看圖1,說明根據本發明之一實施例的半導體封裝1之剖面圖。半導體封裝1包含一封裝基板11、一半導體晶粒3、複數個焊線12、一封膠體(Molding Compound)14及一焊料層16。該封裝基板11具有一頂表面111及一底表面112。
該半導體晶粒3設置於該封裝基板11之該頂表面111上。在此實施例中,該半導體晶粒3包含一基板40、複數個介電層481,482,483,484、一積體電路20、一金屬片段(Metal Segment)46之一部分、四個側表面31,及複數個導電通路(Conductive Via)28。該基板40具有一頂表面401及一底表面402。該金屬片段46及該等介電層481,482,483,484設置於該基板40之該頂表面401上。最底介電層481直接地設置於該基板40之該頂表面401上,且該第二介電層482、該第三介電層483及該第四介電層484以此次序設置於該最底介電層481上。該積體電路20包括複數個圖案化金屬層201,202,203及複數個互連金屬204。該
等圖案化金屬層201,202,203設置於該等介電層481,482,483,484之間且彼此電性連接。該金屬片段46與該積體電路20隔絕。亦即,該金屬片段46未電性連接至該積體電路20。該金屬片段46及該積體電路20之最底圖案化金屬層201在同一層處實質上共平面。應注意,該積體電路20未自該半導體晶粒3之四個側表面31曝露,但該金屬片段46之部分自該半導體晶粒3之一側表面31曝露。
該焊料層16用於將該半導體晶粒3之該基板40的該底表面402接合至該封裝基板11之該頂表面111。在此實施例中,該焊料層16之一部分可填滿由該導電金屬26在該導電通路28中界定的中心孔之部分。該積體電路20經由該導電通路28及該焊料層16而電性連接至該封裝基板11以供接地,使得電感低。該等焊線12電性連接該積體電路20之該第三圖案化金屬層203及該封裝基板11之該頂表面111。該封膠體14包覆該半導體晶粒3、該等焊線12及該封裝基板11之部分。
參看圖2至圖16,說明根據本發明之一實施例的用於製造半導體晶粒之製程。參看圖2,提供一半導體晶圓4,其顯示的是根據本發明之一實施例的半導體晶圓4之仰視圖。該半導體晶圓4被界定為複數個晶粒區域42及複數個渠溝區域(Trench Area)44。該晶粒區域42係預定的、以陣列形式而配置,且將在該半導體晶圓4被切割之後變為每一該等半導體晶粒3(圖1)。該等渠溝區域44設置於該等晶粒區域42之間。在此實施例中,該等渠溝區域44包括將在切割步驟(Sawing Step)期間移除之「切割道(Saw Street)」。該半導體晶圓4包含至少一金屬片段46。在此實施例中,該金屬片段46設置於該渠溝區域44中。然而,在其他實施例中,該金屬片段46可設置於該晶粒區域42中。
參看圖3,說明沿著圖2之線3-3的剖面圖。該半導體晶圓4包含一基板40、該金屬片段46及複數個介電層。在此實施例中,該基板40之材料為諸如矽或鍺之半導體材料。該基板40具有一頂表面401及一底
表面402。該金屬片段46及該等介電層設置於該基板40之該頂表面401上。該等介電層為層間介電質(Inter-level Dielectric),其包括但不限於一最底介電層481、一第二介電層482、一第三介電層483及一第四介電層484。每一該等介電層481,482,483,484可包含具有低介電常數(K)(小於3.4)或超低介電常數(K)(小於2.5)之介電層,且該等介電層481,482,483,484之材料可彼此相同或不同。該最底介電層481直接地設置於該基板40之該頂表面401上,且該第二介電層482、該第三介電層483及該第四介電層484按順序設置於該最底介電層481上。該第二介電層482具有複數個開口4821,該第三介電層483具有複數個開口4831,且該第四介電層484具有複數個開口4841。
該晶粒區域42具有一積體電路20。該積體電路20包括複數個圖案化金屬層及複數個互連金屬204。該圖案化金屬層包括但不限於一最底圖案化金屬層201、一第二圖案化金屬層202及一第三圖案化金屬層203。該等圖案化金屬層201,202,203設置於該等介電層481,482,483,484之間且彼此電性連接。該等圖案化金屬層201,202,203之材料為銅(Cu)。在此實施例中,該最底圖案化金屬層201設置於該最底介電層481上,且由該第二介電層482所覆蓋。該第二圖案化金屬層202設置於該第二介電層482上,且由該第三介電層483所覆蓋。該等互連金屬204設置於該第二介電層482之開口4821中,以用於電性連接該最底圖案化金屬層201及該第二圖案化金屬層202。該第三圖案化金屬層203設置於該第三介電層483之開口4831中,以用於電性連接該第二圖案化金屬層202。該第四介電層484之開口4841曝露該第三圖案化金屬層203。
在此實施例中,該金屬片段46設置於該渠溝區域44中,且與該晶粒區域42之該積體電路20隔絕。亦即,該金屬片段46未電性連接至該積體電路20。該金屬片段46直接地設置於該最底介電層481上。亦
即,該金屬片段46及該積體電路20之最底圖案化金屬層201在同一層處共平面,且其係運用相同材料同時形成。在其他實施例中,該金屬片段46設置於該晶粒區域42中,但與該積體電路20隔絕。應注意的是,該金屬片段46並不是該最底圖案化金屬層201之一部分。
參看圖4,說明沿著圖2之線4-4的剖面圖。在此實施例中,該金屬片段46設置於該渠溝區域44內,且在該金屬片段46上方未設置有圖案化金屬層。然而,若該金屬片段46設置於晶粒區域42內,則該第二圖案化金屬層202可設置於該金屬片段46上方。
參看圖5,說明圖4之仰視圖。該金屬片段46包括三個接墊部分(Pad Portion)461及二個連接部分462。該等連接部分462連接該等接墊部分461。該連接部分462之寬度小於該接墊部分461之寬度。
參看圖6,說明圖5之另一實例。在此實例中,該金屬片段46為矩形且具有一均一寬度(Equal Width)。
參看圖7,藉由蝕刻而自該基板40之該底表面402形成複數個測試孔22,以曝露該金屬片段46。該等測試孔22貫穿該基板40及該最底介電層481。在此實施例中,一個金屬片段46對應於三個測試孔22。
參看圖8,說明圖7之仰視圖。每一該等接墊部分461對應於每一該等測試孔22。
參看圖9,說明沿著垂直於圖7之方向的剖面圖。藉由蝕刻而自該基板40之該底表面402形成複數個內孔24,以曝露該晶粒區域42中之該積體電路20的該最底圖案化金屬層201。該等內孔24貫穿該基板40及該最底介電層481。在此實施例中,該內孔24之直徑約等於該測試孔22之直徑。然而,在其他實施例中,該內孔24之直徑不同於該測試孔22之直徑。
參看圖10,藉由電鍍而在該等測試孔22中形成複數個導電金屬26,以便在該等測試孔22中形成複數個測試通路27。該等導電金屬26
之材料為銅(Cu)。較佳地,該等導電金屬26接觸該金屬片段46,使得該等導電金屬26位於該金屬片段46上。應注意的是,該等測試孔22中之該等導電金屬26彼此分離。亦即,其未彼此實體地連接。該等測試孔22中之該等導電金屬26進一步延伸至該基板40之該底表面402,以形成可供探測之複數個測試部分261。在此實施例中,該等導電金屬26係電鍍於每一該等測試孔22之側壁上。然而,在其他實施例中,該等導電金屬26填滿該等測試孔22。
參看圖11,說明圖10之仰視圖。每一該等導電金屬26具有一個測試部分261。較佳地,該等導電金屬26該接觸金屬片段46。
參看圖12,說明沿著垂直於圖10之方向的剖面圖。藉由電鍍,該等導電金屬26亦形成在該等內孔24中,以便在該等內孔24中形成複數個導電通路28。較佳地,該等導電金屬26接觸該最底圖案化金屬層201,使得該等導電金屬26端接(end on)於該最底圖案化金屬層201上。在此實施例中,該等導電金屬26電鍍於每一該等內孔24之側壁上。然而,在其他實施例中,該等導電金屬26填滿該等內孔24。
參看圖13,進行該等導電金屬26之探測。如圖所示,藉由使用二個探針29而探測任二個測試孔22中的二個導電金屬26。在此實施例中,二個探針29分別用以接觸二個測試部分261。若二個測試孔22中之導電金屬26產生短路(例如,如由二個探針29之間所量測到的電阻低於100Ω所判定),則確認該等測試孔22中之該等導電金屬26完美地位於該金屬片段46上,且該等內孔24中之該等導電金屬26被假設為完美地終止(stop on)於該最底圖案化金屬層201上。此外,該導電金屬26及導電通路28彼此靠近且同時地形成。當該等導電金屬26被假設為終止於金屬上時,該等導電通路28亦可被假設為終止於金屬上。因此,導電通路28被判定為適當地形成,且因此「合格(qualified)」;接著,可切割或遞送該半導體晶圓4。若二個測試孔22中之導電金屬26
產生開路(例如,如由二個探針29之間所量測到的電阻大於或等於100Ω所判定),則確認該等測試孔22中之該等導電金屬26未接觸該金屬片段46,且此外,假設該等內孔24中之該等導電金屬26未能終止於該最底圖案化金屬層201上。此外,該導電金屬26及該等導電通路28彼此靠近且同時地形成。當該等導電金屬26被假設為未能終止於金屬上時,該等導電通路28亦可被假設為未能終止於金屬上。因此,該等導電通路28可被判定為「不合格(unqualified)」。因此,不合格導電通路28之不當缺陷可以在該半導體晶圓4被切割或遞送之前發現。因此,若發生此類不當缺陷,則可及時地選擇晶圓,且可顯著地增加晶圓之良率。
參看圖14,沿著該等渠溝區域44切割該半導體晶圓4以移除部份該金屬片段46及該等測試通路27,以形成複數個半導體晶粒3(圖15及圖16)。該等渠溝區域44為預定切割道(Sawing Street),然而,在實際切割製程中,係沿著實際切割路徑(Real Cutting Path)30切割該半導體晶圓4。該實際切割路徑30設置於該渠溝區域44內,且該實際切割路徑30之寬度窄於該渠溝區域44之寬度。在此實施例中,該實際切割路徑30之寬度窄於該金屬片段46之寬度,但大於該測試通路27之寬度,使得該測試通路27被切除,但保留該金屬片段46之另一部分。
參看圖15及圖16,分別說明根據本發明之一實施例的半導體晶粒3之仰視圖及側視圖。該半導體晶粒3包含該基板40、該等介電層481,482,483,484、該積體電路20、該金屬片段46之一部分、四個側表面31及該等導電通路28。該基板40具有一頂表面401及一底表面402。該金屬片段46及該等介電層481,482,483,484設置於該基板40之該頂表面401上。該最底介電層481直接地設置於該基板40之該頂表面401上,且該第二介電層482、該第三介電層483及該第四介電層484按順序設置於該最底介電層481上。該積體電路20(圖3)係設置於該晶
粒區域42內,且包括該圖案化金屬層201,202,203及該互連金屬204。該等圖案化金屬層201,202,203設置於該等介電層481,482,483,484之間且彼此電性連接。該金屬片段46與該晶粒區域12之該積體電路20隔絕。亦即,該金屬片段46未電性連接至該積體電路20。該金屬片段46直接地設置於該最底介電層201上。亦即,該金屬片段46及該積體電路20之該最底圖案化金屬層201處於同一層。該半導體晶粒3之實際晶粒區域係由四個側表面31界定,且大於該晶粒區域42。應注意的是,該積體電路20未自該半導體晶粒3之四個側表面31曝露,但該金屬片段46之部分自該半導體晶粒3之一側表面31(Lateral Side Surface)曝露。
參看圖17,說明根據本發明之另一實施例的用於製造半導體晶粒之製程。此實施例之半導體製程相似於圖2至圖16之半導體製程,且差異之處係關於切割製程。
參看圖17,沿著該等渠溝區域44切割該半導體晶圓4以移除該金屬片段46及該等測試通路27,以形成複數個半導體晶粒3a(圖18及圖19)。該等渠溝區域44為預定切割道,然而,在實際切割製程中,沿著實際切割路徑30a切割該半導體晶圓4。該實際切割路徑30a窄於圖14之實際切割路徑30,且該實際切割路徑30a之寬度小於該測試通路27之直徑。因此,該測試通路27之一部分不會被切掉,以保留該測試通路27之一部分及該金屬片段46之一部分。
參看圖18及圖19,說明根據本發明之另一實施例的半導體晶粒之仰視圖及側視圖。此實施例之半導體晶粒3a實質上相似於圖15及圖16之半導體晶粒3,且此實施例之半導體晶粒3a與圖15及圖16之半導體晶粒3之間的差異如下所述。除了該金屬片段46之一部分以外,該測試通路27之一部分亦保留於該半導體晶粒3a中。因此,該半導體晶粒3a進一步包含自該金屬片段46延伸至該基板40之該底表面402的導
電金屬26。該金屬片段46及該測試通路27自該半導體晶粒3a之側表面31曝露。應注意的是,圖1之半導體晶粒3可被圖18及圖19之半導體晶粒3a替換。
參看圖20,說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖。此實施例之半導體晶圓4a實質上相似於圖2之半導體晶圓4,且此實施例之半導體晶圓4a與圖2之半導體晶圓4之間的差異如下所述。此實施例之金屬片段46a呈十字形形狀,且設置於四個晶粒區域42之間。另外,在電鍍製程之後,該等測試通路27之位置分別對應於該金屬片段46a之四個分支。
參看圖21,說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖。此實施例之半導體晶圓4b實質上相似於圖2之半導體晶圓4,且此實施例之半導體晶圓4b與圖2之半導體晶圓4之間的差異如下所述。此實施例之金屬片段46b呈L形形狀,且設置於圍繞該晶粒區域42之角落之位置。另外,在電鍍製程之後,該等測試通路27之位置分別對應於該金屬片段46b之端部分(End Portion)。
參看圖22,說明根據本發明之另一實施例的具有金屬片段之半導體晶圓的部分放大仰視圖。此實施例之半導體晶圓4c實質上相似於圖21之半導體晶圓4b,且此實施例之半導體晶圓4c與圖21之半導體晶圓4b之間的差異如下所述。至少一該等晶粒區域42具有一凹口421,且不為矩形。亦即,該晶粒區域42未以陣列形式而配置。此實施例之金屬片段46c進一步具有對應於該凹口421之突起部分463。另外,在電鍍製程之後,至少一該等測試通路27設置於對應於該突起部分463之位置處。應注意的是,該突起部分463不設置於切割道中,因此,在切割製程期間,可不切去該突起部分463及對應於該突起部分463之該測試通路27。
參看圖23,說明根據本發明之另一實施例的顯示不同探測路徑
之半導體晶圓的部分放大仰視圖。在此實施例中,說明四個探測路徑。第一探測路徑51為自測試通路271至測試通路272,其中該第一探測路徑51之金屬片段呈L形形狀,且設置於圍繞該晶粒區域42之角落之位置。第二探測路徑52為自測試通路273至測試通路274,其中該第二探測路徑52之金屬片段呈C形形狀,且設置於圍繞該晶粒區域42之二個角落之位置。第三探測路徑53為自測試通路275至測試通路276,其中該第三探測路徑53之金屬片段呈L形形狀,且設置於圍繞該晶粒區域42之角落之位置。第四探測路徑54為自測試通路277至測試通路278,其中該第四探測路徑54之金屬片段呈U形形狀,且設置於圍繞該晶粒區域42之二個角落之位置。
雖然已參考本發明之特定實施例而描述及說明本發明,但此等描述及說明並不限制本發明。熟習此項技術者應理解,在不脫離如由附加申請專利範圍界定的本發明之真實精神及範疇的情況下,可進行各種改變且可取代等效者。該等說明可未必按比例繪製。歸因於製造製程及容限,在本發明中之藝術轉譯與實際裝置之間可存在區別。可存在未特定地說明的本發明之其他實施例。本說明書及圖式應被認作說明性的而非限制性的。可進行修改以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改皆意欲屬於所附申請專利範圍之範疇。雖然已參考以特定次序所執行之特定操作而描述本文所揭示之方法,但應理解,在不脫離本發明之教示的情況下,可組合、細分或重新排序此等操作以形成等效方法。因此,除非本文特定地指示,否則操作之次序及分組並不限制本發明。
1‧‧‧半導體封裝
3‧‧‧半導體晶粒
11‧‧‧封裝基板
12‧‧‧焊線
14‧‧‧封膠體
16‧‧‧焊料層
20‧‧‧積體電路
26‧‧‧導電金屬
28‧‧‧導電通路
31‧‧‧側表面
40‧‧‧基板
46‧‧‧金屬片段
111‧‧‧頂表面
112‧‧‧底表面
201‧‧‧最底圖案化金屬層
202‧‧‧第二圖案化金屬層
203‧‧‧第三圖案化金屬層
204‧‧‧互連金屬
401‧‧‧頂表面
402‧‧‧底表面
421‧‧‧凹口
481‧‧‧最底介電層
482‧‧‧第二介電層
483‧‧‧第三介電層
484‧‧‧第四介電層
4831‧‧‧開口
4841‧‧‧開口
Claims (13)
- 一種半導體製程,其包含:(a)提供一半導體晶圓,該半導體晶圓具有一基板、至少一金屬片段、複數個積體電路及複數個介電層,其中該至少一金屬片段、該等積體電路及該等介電層設置於該基板之一頂表面上,每一該等積體電路包括設置於該等介電層之間且彼此電性連接之複數個圖案化金屬層,且該至少一金屬片段與該等積體電路隔絕;(b)自該基板之一底表面形成複數個測試孔及內孔,以分別曝露該至少一金屬片段及該積體電路之一最底圖案化金屬層;(c)在該等測試孔及該等內孔中形成複數個導電金屬,其中該等測試孔中之該等導電金屬彼此分離;及(d)探測二個測試孔中的至少二個導電金屬。
- 如請求項1之半導體製程,其中在步驟(a)中,該半導體晶圓被界定為複數個晶粒區域及複數個渠溝區域,每一該等晶粒區域具有每一該等積體電路,且該等渠溝區域設置於該等晶粒區域之間。
- 如請求項2之半導體製程,其中在步驟(a)中,該至少一金屬片段設置於該渠溝區域中。
- 如請求項2之半導體製程,其中在步驟(a)中,該至少一金屬片段設置於該等晶粒區域中。
- 如請求項2之半導體製程,其中該等渠溝區域包括切割道(Saw Street)。
- 如請求項1之半導體製程,其中在步驟(a)中,該至少一金屬片段設置於一最底介電層上。
- 如請求項1之半導體製程,其中在步驟(a)中,該至少一金屬片段及該積體電路之一最底圖案化金屬層在同一層處共平面。
- 如請求項1之半導體製程,其中在步驟(c)中,該等導電金屬電鍍於每一該等測試孔之一側壁及每一該等內孔之一側壁上。
- 如請求項1之半導體製程,其中在步驟(c)中,該等導電金屬填滿該等測試孔及該等內孔。
- 如請求項1之半導體製程,其中在步驟(c)中,該等測試孔中之該等導電金屬進一步延伸至該基板之該底表面,以形成在步驟(d)中用以探測之複數個測試部分。
- 如請求項1之半導體製程,其中在步驟(c)中,該等測試孔中之該等導電金屬接觸該至少一金屬片段,且該等內孔中之該等導電金屬接觸該積體電路之該最底圖案化金屬層。
- 如請求項2之半導體製程,其進一步包含一沿著該等渠溝區域切割該半導體晶圓以形成複數個半導體晶粒之步驟。
- 如請求項3之半導體製程,其進一步包含一沿著該等渠溝區域切割該半導體晶圓以移除該至少一金屬片段及該等測試孔中之該等導電金屬以形成複數個半導體晶粒之步驟。
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2013
- 2013-03-15 US US13/843,304 patent/US8987734B2/en active Active
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2014
- 2014-03-07 TW TW103108020A patent/TWI533415B/zh active
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CN104051392B (zh) | 2017-04-12 |
TW201436123A (zh) | 2014-09-16 |
CN104051392A (zh) | 2014-09-17 |
US8987734B2 (en) | 2015-03-24 |
US20140264716A1 (en) | 2014-09-18 |
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