TWI646644B - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
TWI646644B
TWI646644B TW106121861A TW106121861A TWI646644B TW I646644 B TWI646644 B TW I646644B TW 106121861 A TW106121861 A TW 106121861A TW 106121861 A TW106121861 A TW 106121861A TW I646644 B TWI646644 B TW I646644B
Authority
TW
Taiwan
Prior art keywords
bonding
region
protective film
bonding pad
semiconductor wafer
Prior art date
Application number
TW106121861A
Other languages
English (en)
Other versions
TW201733061A (zh
Inventor
安村文次
土屋文男
伊東久範
井手琢二
川邊直樹
佐藤齊尚
Original Assignee
日商瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201733061A publication Critical patent/TW201733061A/zh
Application granted granted Critical
Publication of TWI646644B publication Critical patent/TWI646644B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本發明提供一種可防止半導體裝置最上層之保護膜之裂痕，以謀求半導體裝置之可靠性之提高之技術。將半導體晶片之主面上所形成之接合焊墊BP1設為長方形狀，並以使接合焊墊BP1之打線接合區域BP1w中之保護膜5之重疊寬度寬於接合焊墊BP1之探針區域BP1p中之保護膜5之重疊寬度之方式，而於接合焊墊BP1上之保護膜5上形成開口部6。

Description

半導體裝置
本發明係有關於一種半導體裝置，尤其係有關於一種適用於搭載具有接合焊墊之半導體晶片之半導體裝置的有效技術。
例如，於日本專利特開平03-79055號公報(專利文獻1)中，揭示有一種電極焊墊，其具備：第1部分，其將金屬線或薄膜引線予以接合；以及第2部分，其與第1部分一體地連結，可在圖案上與第1部分區別辨識，於晶圓測試時使探針與其接觸。
又，於日本專利特開2000-164620號公報(專利文獻2)中，揭示有一種技術，其具有由接合用電極區域及檢查用接合區域形成之電極焊墊，並使接合用電極區域之中心與檢查用接合區域之中心隔開特定間隔以上，藉此可確實地進行半導體裝置之檢查與接合。
又，於日本專利特開2001-338955號公報(專利文獻3)中，揭示有一種打線接合法，其於接合焊墊具備接合區域及探針接觸區域，且於接合區域接合導體金屬線之一端，並使測試用探針之前端與探針接觸區域接觸。
又，於日本專利特開2007-318014號公報(專利文獻4)中，揭示有一種半導體裝置，其呈長方形狀形成有具有第1區域與第2區域之複數個焊墊，焊墊於一部分角部具有倒棱部並且以鋸齒狀排列而設，進而，倒棱部於鋸齒狀排列之內側列與外側列之焊墊上對向地設置，且在半導體晶片之核心邏輯區域側配置有第1區域。
[先行技術文獻] [專利文獻]
[專利文獻1]
日本專利特開平03-79055號公報
[專利文獻2]
日本專利特開2000-164620號公報
[專利文獻3]
日本專利特開2001-338955號公報
[專利文獻4]
日本專利特開2007-318014號公報
半導體裝置中，作為將半導體晶片之主面上所形成之積體電路與搭載半導體晶片之基板之主面上所形成的連接端子(接合引線、焊盤、內部引線)等予以連接之方法之一，使用有打線接合連接方式。打線接合連接方式，係使用包含金(Au)等金屬細線(例如30μm )之複數條接合線，將與半導體晶片的主面上所形成之積體電路電性連接之接合焊墊(電極焊墊、金屬焊墊)、與搭載半導體晶片之基板的主面上所形成之複數個連接端子分別電性連接。
又，於半導體裝置之製造過程中，一般會在裝配步驟(安裝步驟、後步驟)之前，進行半導體晶片的主面上所形成之積體電路之基本功能等之檢查(P檢、探針檢查)。該檢查，通常係在晶圓之狀態下使探針同時接觸複數個接合焊墊，以對半導體晶片的主面上所形成之積體電路之各種電氣 特性進行測定者。再者，於該測定中，係使用預先配合半導體晶片之所有接合焊墊之配置而配置有多數個探針之探針卡。探針卡係與測試器電性連接，且自探針卡輸出與所有探針對應之信號。
然而，於使探針接觸接合焊墊時，有時會劃傷接合焊墊，而剝離構成接合焊墊之金屬膜(例如鋁(Al)膜)。於打線接合連接中，適宜地形成構成接合焊墊之金屬膜與構成接合線前端之金屬球之金屬的合金，對於提高其接合強度較為重要。然而，當因探針之接觸而導致構成接合焊墊之金屬膜被剝離時，存在形成上述合金之區域會變小，而接合焊墊與金屬球之接合可靠性會下降之危險。因此，近年來，係採用如下方法：藉由將1個接合焊墊之表面區域分為接合線所接合之區域(打線接合區域)與探針所接觸之區域(探針區域)，並將接合線連接於不會被探針劃傷之區域。
圖16表示本發明者們所研究接合焊墊之一例。圖16(a)係接合焊墊之主要部分平面圖，圖16(b)係沿圖16(a)之A-A'線放大之主要部分剖面圖。圖16(a)中，例示有2個接合焊墊，但實際上，於1個半導體晶片上，例如形成有300個左右之接合焊墊。
如圖16(a)及(b)所示，接合焊墊B1例如包含以厚度0.85μm之鋁膜為主材料之金屬膜，且為例如第1方向之尺寸為60μm，與第1方向正交之第2方向之尺寸為125μm之長方形狀。鄰接之接合焊墊B1之間隔例如為5μm。接合焊墊B1之表面區域，被分為接合線前端之金屬球所接合之打線接合區域B1w與探針所接觸之探針區域B1p。
接合焊墊B1之周緣部係由保護膜(鈍化膜)51所覆蓋。該保護膜51例如包含厚度0.2μm之氧化矽膜51a與厚度0.6μm之氮化矽膜51b之積層膜。觸及接合焊墊B1之周緣部，並覆蓋接合焊墊B1之周緣部之保護膜51 之寬度例如為2.5μm。於保護膜51與接合焊墊B1之間，例如形成有厚度0.075μm之氮化鈦(TiN)膜52，其係於對構成接合焊墊B1之金屬膜進行加工時之光微影步驟中，為了防止光暈而設，並具有作為抗反射膜之功能之膜。
然而，對於圖16(a)及(b)所示之區別打線接合區域B1w與探針區域B1p之接合焊墊B1而言，存在以下說明之各種技術問題。亦即，在將接合線前端之金屬球接合於接合焊墊B1之打線接合區域B1w時，當金屬球觸及接合焊墊B1之周緣部而施加超聲波時，可明確會於保護膜51之一部分出現裂痕。圖17表示保護膜51上出現之裂痕53之一例。裂痕53主要在接合焊墊B1之端部側面且由金屬球54所覆蓋之部分產生。進而，亦有時會因出現裂痕53，而導致保護膜51之一部分被剝離等之不良產生。
若產生如此之不良，則例如於作為半導體製品之耐濕性測試之一的HAST(Highly-Accelerated Temperature and Humidity Stress Test，測試條件85℃/85%/Bias)測試等中，水分容易浸入接合焊墊B1。因浸入之水分而於鄰接之接合焊墊B1間產生電位差，從而導致鄰接之接合焊墊B1間發生短路。進而，浸入之水分會使為了防止光暈而設並殘存於保護膜51與接合焊墊B1之間之氮化鈦膜52被氧化。氮化鈦膜52一旦氧化將會膨脹，在因其膨脹所產生之應力下，接合焊墊B1更下層之內部配線間所設之層間絕緣膜會受到破壞，從而在內部配線間、或接合焊墊B1與內部配線發生短路。接合焊墊B1間之短路、內部配線間之短路、或接合焊墊B1與內部配線之短路等電氣不良，會導致半導體裝置之可靠性顯著下降。
例如，藉由改變將金屬球接合於接合焊墊之打線接合區域時之條件，可防止保護膜上產生之裂痕。作為打線接合時之接合條件之一例，例 如有於230度左右之溫度下，一面施加120mN左右之固定載荷，一面藉由超聲波使金屬球振動而進行摩擦接合焊墊之動作。如此般，在適宜地形成構成接合焊墊之金屬膜與構成金屬球之金屬的合金之條件下進行打線接合連接，對於提高其接合強度較為重要，但難以輕易地變更接合條件(例如溫度、載荷、超聲波施加時間等)。
又，藉由縮小金屬球之直徑，以使金屬球不會觸及接合焊墊之周緣部，可防止保護膜上產生之裂痕。然而，形成構成接合焊墊之金屬膜與構成金屬球之金屬的合金之區域將會變小，存在接合焊墊與金屬球之接合可靠性下降之危險。
又，藉由增大接合焊墊之面積，以使金屬球不會觸及接合焊墊之周緣部，亦可防止保護膜上產生之裂痕。然而，若不改變鄰接之接合焊墊之間隔而增大接合焊墊之面積，則接合焊墊所佔之區域將會增大，因而必須擴大半導體晶片之尺寸。雖亦考慮縮窄鄰接之接合焊墊間之尺寸而增大接合焊墊之面積之方法，但若考慮到加工精度等，則難以較現狀(約5μm左右)進一步縮窄其尺寸。
又，藉由擴寬與接合焊墊之周緣部重疊之保護膜之寬度，可防止保護膜上產生之裂痕。然而，若擴寬與接合焊墊之周緣部重疊之保護膜之寬度，則探針區域之面積將會減少而探針會接觸保護膜，從而因探針導致保護膜被破壞之可能性將變高。
又，藉由設為保護膜不重疊於接合焊墊之周緣部之構造，可防止保護膜上產生之裂痕。然而，當在使保護膜成膜後，於接合焊墊上之保護膜上形成開口部時，由於要將接合焊墊用作蝕刻阻止膜，因此不可設為保護膜不重疊於接合焊墊之周緣部之構造。在形成最上層之配線及保護膜，並 於保護膜上形成開口部而使最上層之配線之一部分露出之後，通過該開口部形成電性連接於最上層配線之接合焊墊，藉此可設為保護膜不重疊於接合焊墊之周緣部之構造。然而，由於最上層之配線與接合焊墊係由彼此不同層之金屬膜所形成，因此會產生步驟數及材料成本等增加，而半導體裝置之製造成本將會增加之問題。
本發明之目的在於提供一種可防止半導體裝置最上層之保護膜之裂痕，以謀求半導體裝置之可靠性之提高之技術。
本發明之上述以及其他目的與新穎之特徵，可根據本說明書之記述及附圖而明確。
對本案所揭示之發明中具代表性者之一實施形態進行簡單說明如下。
該實施形態係一種半導體裝置，其包含：半導體晶片，其具有：第一主面(first main surface)，與上述第一主面為相反側之第二主面(second main surface)，延伸於第一方向之邊，及形成於上述第一主面且沿上述邊延伸之複數個接合焊墊；各上述接合焊墊具有：第一邊及與上述第一邊為相反側之第二邊，且延伸於上述第一方向；其中上述半導體晶片之上述第一主面被形成有複數個開口部的保護膜覆蓋，各上述接合焊墊之上面(upper surface)之周緣部被上述保護膜覆蓋，且各上述接合焊墊之上述上面之上述周緣部以外的部分係自上述複數個開口部中之對應者露出；各上述接合焊墊之上述上面被區分(sectioned)為接合區域及探針區域(probe region)；於俯視時，在垂直於上述第一方向之第二方向上，上述保護膜與上述接合區域中之各上述接合焊墊之上述周緣部之重疊寬度係較上述保 護膜與上述探針區域中之各上述接合焊墊之上述周緣部之重疊寬度寬；於俯視時，接觸線(contact trace)沿上述第二方向形成於上述探針區域中。
該實施形態係一種半導體裝置，其包含：半導體晶片，其具有：主面，該主面上沿著延伸於第一方向之邊形成有複數個接合焊墊；及配線構件，其具有：頂面(top surface)，該頂面之上搭載有上述半導體晶片，且電性連接於該半導體晶片；其中各上述接合焊墊之上面之周緣部被形成有複數個開口部之絕緣膜覆蓋，且各上述接合焊墊之上述上面之上述周緣部以外的部分係自上述複數個開口部中之對應者露出；各上述接合焊墊之上述上面被區分為接合區域及探針區域；於俯視時，在垂直於上述第一方向之第二方向上，上述絕緣膜與上述接合區域中之各上述接合焊墊之上述周緣部之重疊寬度係較上述絕緣膜與上述探針區域中之各上述接合焊墊之上述周緣部之重疊寬度寬；於俯視時，接觸線沿上述第二方向形成於上述探針區域中。
該實施形態係一種半導體裝置，其搭載具有主面及背面之四邊形之半導體晶片，該主面配置有被區分有接合區域與探針區域之長方形狀之複數個接合焊墊，該背面係與上述主面為相反側者。半導體晶片於接合焊墊之上層具有保護膜，保護膜係以覆蓋接合焊墊之周緣部，而使接合焊墊之上面露出之方式開口。進而，接合區域中之接合焊墊之周緣部與保護膜之重疊寬度，較探針區域中之接合焊墊之周緣部與保護膜之重疊寬度更寬。
又，該實施形態係一種半導體裝置，其搭載具有主面及背面之四邊形之半導體晶片，該主面配置有被區分有接合區域與探針區域之凸形狀之複數個接合焊墊，該背面係與主面為相反側者。半導體晶片於接合焊墊之上層具有保護膜，保護膜係以覆蓋接合焊墊之周緣部，而使接合焊墊之上 面露出之方式開口。進而，接合區域中之接合焊墊之周緣部與保護膜之重疊寬度，較探針區域中之接合焊墊之周緣部與保護膜之重疊寬度更寬，複數個接合焊墊係分別配置成，沿半導體晶片之邊而於接合焊墊之長邊方向上分別交替錯開，且，凸形狀交替反轉。
該實施形態係一種半導體裝置，其搭載具有四邊形狀之電源用接合焊墊之半導體晶片，該電源用接合焊墊被區分有接合區域與探針區域。於電源用接合焊墊之上層，形成有具有使電源用接合焊墊之上面之一部分跨及接合區域及探針區域而露出之2個開口部之保護膜，電源用接合焊墊之接合區域及探針區域自2個開口部分別露出，且僅於2個開口部之間之電源用接合焊墊之接合區域中形成狹縫。又，以覆蓋電源用接合焊墊之周緣部而形成有保護膜，且接合區域中之電源用接合焊墊之周緣部與保護膜之重疊寬度寬於探針區域中之電源用接合焊墊之周緣部與保護膜之重疊寬度之方式，而形成有2個開口部。
對藉由本案所揭示之發明中具代表性者之一實施形態所獲得之效果進行簡單說明如下。
本發明可防止半導體裝置最上層之保護膜之裂痕，以謀求半導體裝置之可靠性之提高。
1‧‧‧半導體裝置
2‧‧‧配線基板
2x‧‧‧主面
2y‧‧‧背面
3‧‧‧半導體晶片
3a‧‧‧焊墊區域
3b‧‧‧核心區域
4‧‧‧焊錫球
5‧‧‧保護膜
5a‧‧‧氧化矽膜
5b‧‧‧氮化矽膜
6、6a‧‧‧開口部
7‧‧‧接合引線
8‧‧‧背面電極焊墊
9B‧‧‧凸塊
9W‧‧‧接合線
10‧‧‧樹脂密封體
11‧‧‧抗反射膜
12‧‧‧開口部
13‧‧‧保護膜
13a‧‧‧第1絕緣膜
13b‧‧‧第2絕緣膜
13c‧‧‧第3絕緣膜
14‧‧‧狹縫
51‧‧‧保護膜
51a‧‧‧氧化矽膜
51b‧‧‧氮化矽膜
52‧‧‧氮化鈦膜
53‧‧‧裂痕
54‧‧‧金屬球
55‧‧‧開口部
56‧‧‧保護膜
57‧‧‧裂痕
B1‧‧‧接合焊墊
B1p‧‧‧探針區域
B1w‧‧‧打線接合區域
BP1、BP2、BP3‧‧‧接合焊墊
BP1p、BP2p、BP3p、BP4p‧‧‧探針區域
BP1w、BP2w、BP3w、BP4w‧‧‧打線接合區域
P1‧‧‧間距
VB‧‧‧電源用接合焊墊
VBp‧‧‧探針區域
VBw‧‧‧打線接合區域
VBP1、VBP2‧‧‧電源用接合焊墊
圖1係表示本實施形態1之採用打線接合連接之BGA型半導體裝置之構成之平面圖。
圖2係表示本實施形態1之採用打線接合連接之BGA型半導體裝置之構成之剖面圖。
圖3係將本實施形態1之接合焊墊放大表示之主要部分平面圖。
圖4係將本實施形態1之接合焊墊之一部分放大表示之主要部分剖面圖(沿圖3之I-I'線之剖面圖)。
圖5(a)係表示本實施形態1之採用倒裝晶片連接之BGA型半導體裝置之構成之平面圖，圖5(b)係將圖5(a)之一部分放大表示之主要部分剖面圖。
圖6係表示本實施形態1之採用倒裝晶片連接之BGA型半導體裝置之構成之剖面圖。
圖7係將本實施形態2之接合焊墊放大表示之主要部分平面圖。
圖8係將本實施形態2之接合焊墊之一部分放大表示之主要部分剖面圖(沿圖7之II-II'線之剖面圖)。
圖9係將本實施形態3之接合焊墊放大表示之主要部分平面圖。
圖10係將本實施形態3之接合焊墊之一部分放大表示之主要部分剖面圖(沿圖9之III-III'線之剖面圖)。
圖11係將本發明者等人所研究之電源用接合焊墊放大表示之主要部分平面圖。
圖12係將本發明者等人所研究之電源用接合焊墊之一部分放大表示之主要部分剖面圖(沿圖11之B-B'線之剖面圖)。
圖13係將本實施形態4之電源用接合焊墊放大表示之主要部分平面圖。
圖14係將本實施形態4之電源用接合焊墊之一部分放大表示之主要部分剖面圖(沿圖13之IV-IV'線之剖面圖)。
圖15係將本實施形態4之電源用接合焊墊之變形例之一部分放大表示 之主要部分剖面圖。
圖16(a)係將本發明者等人所研究之接合焊墊放大表示之主要部分平面圖，圖16(b)係沿圖16(a)之A-A'線放大之主要部分剖面圖。
圖17係表示保護膜上出現之裂痕之一例之接合焊墊之主要部分剖面圖。
於以下之實施形態中，有時為了方便，分割為複數個部分或實施形態進行說明，但除了特別明示之情形以外，該等部分或實施形態並非彼此無關者，存在其中一者係為另一者之一部分或全部之變形例、詳細、補充說明等之關係。
又，於以下實施形態中，當言及要素之數等(包括個數、數值、量、範圍等)時，除了特別明示之情形及原理上明確被限定於特定數之情形等以外，並不限定於該特定數，既可為特定數以上亦可為特定數以下。進而，於以下實施形態中，其構成要素(亦包括要素步驟等)，除了特別明示之情形及被認為原理上明確必須如此之情形等以外，當然未必必須如此。同樣地，於以下實施形態中，當言及構成要素等之形狀、位置關係等時，除了特別明示之情形及被認為原理上明確並非如此之情形等以外，包括實質上近似或類似該形狀者等。該情形對於上述數值及範圍亦為同樣。
又，在以下之實施形態中所使用之圖式中，即使為平面圖，有時亦會為使圖式便於觀察而標註影線。又，於以下之實施形態中，當言及晶圓時，係以Si(Silicon)單晶晶圓為主，但不僅為此，亦指SOI(Silicon On Insulator)晶圓、用於在其上形成積體電路之絕緣膜基板等。其形狀不僅可為圓形或大致圓形，亦包括正方形、長方形等。
又，在用於說明以下實施形態之所有圖中，具有相同功能者原則上標註相同符號，並省略其重複說明。以下，根據圖式詳細說明本發明之實施形態。
(實施形態1)使用圖1~圖4，對本實施形態1之採用打線接合連接之面朝上接合構造之BGA(Ball Grid Array，球柵陣列)型半導體裝置進行說明。圖1係表示採用打線接合連接之BGA型半導體裝置之構成之平面圖，圖2係表示採用打線接合連接之BGA型半導體裝置之構成之剖面圖，圖3係將接合焊墊放大表示之主要部分平面圖，圖4係將接合焊墊之一部分放大表示之主要部分剖面圖(沿圖3之I-I'線之剖面圖)。
如圖1及圖2所示，半導體裝置1並不限定於此，其呈封裝構造，即：在位於配線基板2之彼此相反側之主面2x及背面2y中，於主面2x側搭載有半導體晶片3，於配線基板2之背面2y側配置有複數個焊錫球4作為外部用連接端子。
於配線基板2之主面2x上，經由糊狀或DAF(Die Attach Film，晶片貼裝薄膜)等之薄膜狀接著劑而搭載有半導體晶片3，半導體晶片3中，與其厚度方向交叉之平面形狀呈四邊形。沿半導體晶片3之主面之各邊(周緣部)，配置有1列之複數個接合焊墊BP1。又，於設有複數個接合焊墊BP1之區域(焊墊區域)3a之內側，形成有核心區域3b，於此處，形成有CPU(Central Processing Unit，中央處理單元)、DSP(Digital Signal Processing，數位訊號處理器)、RAM(Bandom Access Memory，隨機存取記憶體)、PLL(Phase Locked Loop，鎖相迴路)、及DLL(Delay Locked Loop)等之積體電路。
複數個接合焊墊BP1包含半導體晶片3之多層配線層(將絕緣膜與配線 層分別層疊複數段而成之多層配線層)中之最上層配線。於複數個接合焊墊BP1之上層，覆蓋多層配線層而形成有保護膜5，各個接合焊墊BP1之上面之一部分藉由保護膜5上所形成之開口部6而露出。
配線基板2例如為增層基板等，與其厚度方向交叉之平面形狀呈四邊形。配線基板2呈主要具有芯材、以覆蓋該芯材之主面之方式而形成之主面保護膜、及以覆蓋位於與該芯材之主面為相反側之背面之方式而形成之背面保護膜的構成。芯材例如呈於其主面、背面及內部具有配線之多層配線構造。
於配線基板2之主面2x上，在自半導體晶片3之周邊端部直至配線基板2之周邊端部之間之區域，沿配線基板2之各邊而配置有1列之複數條接合引線7。該等接合引線7包含配線基板2之芯材上所形成之最上層之配線，各條接合引線7之上面藉由主面保護膜上所形成之開口部而露出。於配線基板2之背面2y，配置有複數個背面電極焊墊8。該等背面電極焊墊8包含配線基板2之芯材上所形成之最下層之配線，各個背面電極焊墊8之下面藉由背面保護膜上所形成之開口部而露出。芯材上所形成之複數條最上層之配線與複數條最下層之配線，藉由貫穿芯材之複數個貫穿孔之內部所形成之配線而分別電性連接。
半導體晶片3之主面上所配置之複數個接合焊墊BP1與配線基板2之主面上所配置之複數條接合引線7，藉由複數條接合線9W而分別電性連接。對於接合線9W，例如使用20~30μm 左右之金線。對於該打線接合連接，例如可使用於熱壓接中併用超聲波振動之釘頭式接合(球形接合)法。半導體晶片3及接合線9W係藉由配線基板2之主面上所形成之樹脂密封體10而密封。樹脂密封體10例如包含環氧化物等絕緣性樹脂。
如圖3所示，各接合焊墊BP1具有長方形狀，沿著半導體晶片之邊之方向具有短邊，在與半導體晶片之邊交叉之方向上具有長邊。又，沿著沿長邊之方向(長邊方向)，1個接合焊墊BP1之表面區域被分為用於使接合線接合之區域(打線接合區域)BP1w與檢查用探針所接觸之區域(探針區域)BP1p。此處，對於打線接合區域BP1w及探針區域BP1p之配置，較為理想的是，以打線接合區域BP1w處於靠近半導體晶片之邊之一側之方式，配置接合焊墊BP1。藉由將打線接合區域BP1w配置於靠近半導體晶片之邊之一側，較之將探針區域BP1p配置於靠近半導體晶片之邊之一側之情形，可縮短電性連接接合焊墊BP1與配線基板之主面上所形成之接合引線7的接合線之長度，可縮小接合焊墊BP1與接合引線7之間之電感。
接合焊墊BP1例如包含以鋁膜為主材料之金屬膜，其厚度例如為0.85μm左右。又，當將沿半導體晶片之邊而配置之鄰接之接合焊墊BP1之間距(P1)設為例如65μm時，作為接合焊墊BP1之尺寸，例如長邊方向之一邊為120μm，短邊方向之一邊為60μm，作為鄰接之接合焊墊BP1之間隔，例如可例示5μm。
又，接合焊墊BP1具備打線接合區域BP1w與探針區域BP1p不會重疊之寬窄度即可，因此亦可使探針區域BP1p之面積與打線接合區域BP1w之面積相同。然而，於本實施形態1中，為擴寬探針區域BP1p，而使探針區域BP1p之尺寸長於接合焊墊BP1之長邊方向之打線接合區域BP1w之尺寸。例如，如圖3所示，接合焊墊BP1之長邊方向之打線接合區域BP1w之尺寸例如為50μm，接合焊墊BP1之長邊方向之探針區域BP1p之尺寸例如為62.5μm。
接合焊墊BP1包含半導體晶片之多層配線層中之最上層配線，並藉由 於以覆蓋多層配線層之方式而形成之保護膜5上對應於各個接合焊墊BP1所形成之開口部6而露出。
如圖4所示，保護膜5係於接合焊墊BP1上成膜，例如包含氧化矽膜5a及堆積於其上之氮化矽膜5b的積層膜。氧化矽膜5a例如藉由電漿CVD(Chemical Vapor Deposition，化學氣相沈積)法而形成，其厚度例如為0.2μm左右。氮化矽膜5b例如藉由電漿CVD法而形成，其厚度例如為0.6μm左右。藉由電漿CVD法而形成之氮化矽膜5b具有防止來自外部之水分浸入之功能。
於接合焊墊BP1之上面與保護膜5之間，殘存有抗反射膜11。該抗反射膜11係藉由光微影法及蝕刻法而形成接合焊墊BP1時，為了防止光微影步驟中之光暈而設之膜。亦即，於在晶圓之整個面上形成金屬膜(例如鋁膜)及抗反射膜之後，藉由光微影法及蝕刻法，對該等金屬膜及抗反射膜進行加工而形成接合焊墊BP1(同時亦形成最上層配線)。繼而，於在晶圓之整個面上形成保護膜5之後，藉由光微影法及蝕刻法，於保護膜5上形成使接合焊墊BP1之上面露出之開口部6。此時，由於保護膜5下之抗反射膜11未被去除，因此在接合焊墊BP1之上面與保護膜5之間殘存抗反射膜11。抗反射膜11例如包含氮化鈦膜，其厚度例如為0.075μm左右。
又，保護膜5上所形成之開口部6係被設於接合焊墊BP1上。其原因在於，於在接合焊墊BP1上所成膜之保護膜5上形成開口部6時，將接合焊墊BP1用作保護膜5之蝕刻用阻止膜。因而，保護膜5以特定之寬度重疊於接合焊墊BP1之周緣部上，接合焊墊BP1之周緣部係由保護膜5所覆蓋。
於本實施形態1之接合焊墊BP1中，係以重疊於接合焊墊BP1之周緣部之保護膜5之寬度在打線接合區域BP1w與探針區域BP1p中彼此不同， 打線接合區域BP1w中之保護膜5之重疊寬度寬於探針區域BP1p中之保護膜5之重疊寬度之方式，形成凸形狀之開口部6。作為打線接合區域BP1w中之保護膜5之重疊寬度，例如可例示5μm，作為探針區域BP1p中之保護膜5之重疊寬度，例如可例示2.5μm。因而，打線接合區域BP1w之短邊方向之開口部6之尺寸例如為50μm，探針區域BP1p之短邊方向之開口部6之尺寸例如為55μm。
於上述尺寸之接合焊墊BP1之情形時，例如於直徑為30μm之接合線中，其前端之金屬球之直徑例如為40μm左右，若僅將金屬球接合於打線接合區域BP1w之中心，則金屬球將不會觸及接合焊墊BP1之周緣部與保護膜5重疊之部分。然而，於實際之打線接合步驟中，難以以金屬球不會觸及接合焊墊BP1之周緣部與保護膜5重疊之部分之方式，而進行打線接合。
對其理由進行說明。打線接合步驟中所使用之打線接合裝置，係於熱壓接中併用超聲波振動來進行打線接合者。打線接合裝置係藉由接合線，將半導體晶片上所設之接合焊墊及與其對應之配線基板上所設之接合引線之間予以接線。於該接線步驟中，最先，使毛細管下降至特定之接合焊墊之打線接合區域上，壓接接合線前端之金屬球。此時，例如在施加230℃左右之熱之狀態下，併用超聲波振動。載荷例如為120mN左右。繼而，將毛細管提起至特定高度為止，並描繪環形，使毛細管移行至對應之接合引線。於接合引線上，對毛細管進行加壓而將接合線稍微壓破並提起，藉此自毛細管切斷接合線。將其依序對配置成一列之複數個接合焊墊之打線接合區域及與該等分別對應之接合引線予以實施。亦即，以接合線連接1個接合焊墊之打線接合區域與1條接合引線之間之時間較為高速，一 般例如為0.1秒以下。並且，於該打線接合裝置之接線步驟之中，存在金屬球會偏離打線接合區域之中心之各種因素。
為了自動執行上述接線步驟，打線接合裝置被預先輸入半導體晶片之接合焊墊及配線基板之接合引線之位置座標，並將該資料保持於內部。該位置座標一般係使用打線接合裝置所具備之相機而藉由圖像識別來輸入者，但由於輸入圖像之良否判斷及操作打線接合裝置者係為人類，因此難免會產生識別誤差。又，成為接合對象之半導體晶片及配線基板，被設置於打線接合裝置之基台所具備之XYθ平台上，於接合時，由於該XYθ平台以高速反覆進行多次移動，因此亦會產生XYθ平台之移動停止誤差。又，金屬球係藉由經由毛細管施加載荷及超聲波而壓破，但壓破後之球徑亦具有數微米級別之偏差。進而，由於近年來之半導體裝置之小型化之進程，半導體晶片之尺寸變小，伴隨於此，接合焊墊之尺寸亦變小，因此接合焊墊之端與金屬球外周之間隙僅為數微米左右。
即，由於上述圖像識別誤差、XYθ平台之移動停止誤差、球徑之偏差、接合焊墊之端與金屬球外周之間隙之減少、及其他因素之積累，大多金屬球會觸及接合焊墊之周緣部與保護膜重疊之部分。
然而，如本實施形態1般，打線接合區域BP1w中之接合焊墊BP1之周緣部與保護膜5之重疊寬度較寬，例如為5μm，藉此，接合焊墊BP1之周緣部與保護膜5重疊之部分之強度提高，因此即使金屬球觸及該重疊部分，亦可防止保護膜5出現裂痕。又，藉由在金屬球與接合焊墊BP1之間良好地形成合金層且接合不會產生問題之限度內縮小金屬球，亦可進一步擴寬打線接合區域BP1w中之接合焊墊BP1之周緣部與保護膜5之重疊寬度。藉此，可進一步降低保護膜5出現裂痕之危險性。再者，根據本發明 者等人之研究結果可確認，若接合焊墊BP1之周緣部與保護膜5之重疊寬度為5μm，則即使金屬球觸及接合焊墊BP1之周緣部與保護膜5重疊之部分，保護膜5亦不會出現裂痕。
另一方面，於半導體晶片之檢查步驟中，若探針僅接觸探針區域BP1p之中心，則即使探針區域BP1p之接合焊墊BP1所露出之開口部6之面積較小，探針亦不會接觸接合焊墊BP1之周緣部與保護膜5重疊之部分。然而，於實際之半導體晶片之檢查步驟中，難以使探針僅接觸探針區域BP1p之中心。
對其理由進行說明。例如半導體晶片在藉由切割而單片化之前之晶圓之階段，接受測試器之檢查。於該檢查中，使用探針卡來作為將測試器連接於半導體晶片之機構。探針卡於其中一面上具備複數個探針，其等分別接觸半導體晶片上所設之複數個接合焊墊之探針區域。繼而，經由探針，藉由測試器來計測半導體晶片之主面上所形成之積體電路之電氣特性。上述檢查係對複數個半導體晶片(例如排列成4×8之半導體晶片)同時進行，亦有時一次使1000~2000根探針分別接觸複數個接合焊墊。因此，探針亦多會偏離接合焊墊之探針區域之中心，於考慮到其偏移量之情形時，無法減小探針區域之接合焊墊所露出之開口部之面積。
然而，如本實施形態1般，藉由使探針區域BP1p中之接合焊墊BP1之周緣部與保護膜5之重疊寬度較窄，例如為2.5μm，可將接合焊墊BP1之上面所露出之開口部6之面積確保為較寬。再者，若使探針區域BP1p中之接合焊墊BP1之周緣部與保護膜5之重疊寬度更窄，則探針接觸接合焊墊BP1之周緣部之保護膜5之危險性亦會變得更低。然而，此時，由於在保護膜5上形成開口部6時之接合焊墊BP1與開口部6之對準偏差，在對保護 膜5進行蝕刻之同時，存在接合焊墊BP1之下層所形成之接合焊墊BP1周邊之層間絕緣膜亦會受到蝕刻之可能性。根據本發明者等人之研究結果可確認，若接合焊墊BP1之周緣部與保護膜5之重疊寬度為2.5μm，便不會引起上述加工不良之產生。
如此，根據本實施形態1，將接合焊墊BP1設為長方形狀，且以使接合焊墊BP1之打線接合區域BP1w中之保護膜5之重疊寬度寬於接合焊墊BP1之探針區域BP1p中之保護膜5之重疊寬度之方式，而於接合焊墊BP1上之保護膜5上形成開口部6。藉此，於接合焊墊BP1之打線接合區域BP1w中，將金屬球接合於該打線接合區域BP1w時，即使金屬球觸及接合焊墊BP1之周緣部，亦可防止保護膜5出現裂痕。又，於接合焊墊BP1之探針區域BP1p中，可將接合焊墊BP1所露出之開口部6設為探針不會接觸重疊於接合焊墊BP1之周緣部之保護膜5之寬度。藉由前者，不會產生裂痕，因此可防止水分經由裂痕浸入接合焊墊BP1，從而可防止接合焊墊BP1間之短路、內部配線間之短路、或接合焊墊BP1與內部配線等之短路等電氣不良。又，對於後者，可防止因探針接觸保護膜5所造成之保護膜5之破壞。
再者，至此為止，對在採用打線接合連接之BGA型半導體裝置中適用本案發明之情形進行了說明，但並不限定於此。例如，在採用將半導體晶片與配線基板經由凸塊電極而連接之倒裝晶片連接之半導體裝置中，亦可適用本案發明。
使用圖5及圖6，對採用倒裝晶片連接之面朝下接合構造之BGA型半導體裝置進行說明。圖5係表示採用倒裝晶片連接之BGA型半導體裝置之構成之平面圖，圖6係表示採用倒裝晶片連接之BGA型半導體裝置之構成 之剖面圖。再者，於圖5中，為說明接合焊墊之配置，記載了形成有接合焊墊之半導體晶片之主面，但實際上，如圖6所示，半導體晶片之主面係與配線基板之主面對向。
如圖5及圖6所示，接合焊墊BP1及開口部6之形狀係與使用上述圖3及圖4所說明者相同。亦即，各接合焊墊BP1具有長方形狀，在沿著半導體晶片3之邊之方向具有短邊，在與半導體晶片之邊交叉之方向具有其長邊。又，沿著長邊方向，1個接合焊墊BP1之表面區域被分為凸塊9B所連接之凸塊接合區域(與上述圖3所示之打線接合區域BP1w相同之區域)與探針區域(與上述圖3所示之探針區域BP1p相同之區域)。又，凸形狀之開口部6係以下述方式而形成，即：重疊於接合焊墊BP1之周緣部之保護膜5之寬度在凸塊接合區域與探針區域中彼此不同，凸塊接合區域中之保護膜5之重疊寬度寬於探針區域中之保護膜5之重疊寬度。
於採用此種倒裝晶片連接之面朝下接合構造之情形時，可以凸塊接合區域處於較半導體晶片3之邊更靠近核心區域3b之一側之方式(探針區域處於較半導體晶片3之核心區域3b更靠近邊之一側之方式)，來配置接合焊墊BP1。藉由將凸塊接合區域配置於靠近半導體晶片3之核心區域3b之一側，較之將探針區域配置於靠近半導體晶片3之核心區域3b之一側之情形，可縮短電性連接接合焊墊BP1與核心區域3b上所形成之積體電路之電路配線之長度，從而可減小因電路配線所引起之電感。
再者，於本實施形態1中所述之特徵，係以適用於BGA封裝之情形為例進行說明，但並不限定於此，亦可適用於QFP(Quad Flat Package)、SOP(Small Outline Package)及CSP(Chip Size Package)等其他封裝中。
(實施形態2)本實施形態2係為上述實施形態1之接合焊墊BP1之變形 例，接合焊墊及開口部之形狀、以及接合焊墊之配置與上述實施形態1中所說明者不同。使用圖7及圖8，對本實施形態2之接合焊墊之形狀及配置進行說明。圖7係將接合焊墊放大表示之主要部分平面圖，圖8係將接合焊墊之一部分放大表示之主要部分剖面圖(沿圖7之II-II'線之剖面圖)。
如圖7及圖8所示，與上述實施形態1同樣地，1個接合焊墊BP2之表面區域被分為打線接合區域BP2w與探針區域BP2p。然而，與上述實施形態1不同，打線接合區域BP2w之沿半導體晶片之邊之方向之長度(LB)，係形成為長於探針區域BP2p之沿半導體晶片之邊之方向之長度(LP)，且接合焊墊BP2具有凸形狀。進而，各接合焊墊BP2係沿半導體晶片之邊而在接合焊墊BP2之長邊方向上分別交替地(呈鋸齒狀)錯開而配置，且，以打線接合區域BP2w處於半導體晶片之邊側、核心區域側、半導體晶片之邊側之方式而使凸形狀交替地反轉而配置。
與半導體晶片之邊交叉之方向(長邊方向)之接合焊墊BP2之尺寸，可設為與上述實施形態1之接合焊墊BP1相同，作為接合焊墊BP2之尺寸，例如可設長邊方向之一邊為120μm，接合焊墊BP2之長邊方向之打線接合區域BP2w之尺寸例如為50μm，接合焊墊BP2之長邊方向之探針區域BP2p之尺寸例如為62.5μm。
又，與上述實施形態1同樣地，設沿著半導體晶片3之邊而呈鋸齒狀配置之鄰接之接合焊墊BP2之間距(P2)例如為65μm，鄰接之接合焊墊BP2之最小間隔例如為5μm時，沿半導體晶片之邊之方向(短邊方向)之接合焊墊BP2之尺寸例如可設為，打線接合區域BP2w之短邊方向之尺寸為65μm，探針區域BP2p之短邊方向之尺寸為60μm。再者，隔1個地配置之接合焊墊BP2之打線接合區域BP2w之間之間隔(S2)只要為最小間隔即5 μm即可，因此如圖7中虛線所示，可使打線接合區域BP2w之短邊方向之尺寸大於上述65μm。
接合焊墊BP2係與上述實施形態1同樣地，包含半導體晶片之多層配線層中之最上層配線，且藉由在以覆蓋多層配線層之方式而形成之保護膜5上對應於各個接合焊墊BP2所形成之開口部12而露出。又，保護膜5之開口部12係被設於接合焊墊BP2上，保護膜5以特定之寬度重疊於接合焊墊BP2之周緣部上，接合焊墊BP2之周緣部被保護膜5所覆蓋。
然而，與上述實施形態1不同地，本實施形態2之接合焊墊BP2中，上述開口部12之形狀係為長方形狀。因而，重疊於接合焊墊BP2之周緣部之保護膜5之寬度在打線接合區域BP2w與探針區域BP2p中彼此不同，打線接合區域BP2w中之保護膜5之重疊寬度寬於探針區域BP2p中之保護膜5之重疊寬度。作為開口部12之尺寸，例如可例示長邊方向之一邊為112.5μm，短邊方向之一邊為55μm。藉由上述接合焊墊BP2之尺寸及開口部12之尺寸，可將打線接合區域BP2w中之保護膜5之重疊寬度設為5μm，探針區域BP2p中之保護膜5之重疊寬度設為2.5μm。又，當使接合焊墊BP2之打線接合區域BP2w之短邊方向之尺寸大於65μm時，可使打線接合區域BP2w中之保護膜5之重疊寬度更大。例如當接合焊墊BP2之打線接合區域BP2w之短邊方向之尺寸為125μm時，可獲得35μm之打線接合區域BP2w中之保護膜5之重疊寬度。
如此，根據本實施形態2，藉由將接合焊墊BP2設為，打線接合區域BP2w之沿半導體晶片之邊之長度形成為長於探針區域BP2p之沿半導體晶片之邊之長度之凸形狀，並將接合焊墊BP2上之保護膜5上所形成之開口部12設為長方形狀，從而可使接合焊墊BP2之打線接合區域BP2w中之保 護膜5之重疊寬度寬於接合焊墊BP2之探針區域BP2p中之保護膜5之重疊寬度。藉此，於接合焊墊BP2之探針區域BP2p中，確保不與探針觸及接合焊墊BP2之周緣部之保護膜5接觸之開口部12之寬窄度，並且於接合焊墊BP2之打線接合區域BP2w中，即使接合線前端之金屬球觸及接合焊墊BP2之周緣部，亦可防止保護膜5上出現裂痕，因此可獲得與上述實施形態1同樣之效果。
進而，各接合焊墊BP2係沿著半導體晶片之邊而在接合焊墊BP2之長邊方向上分別交替地(呈鋸齒狀)錯開而配置，且，以打線接合區域BP2w處於半導體晶片之邊側、核心區域側、半導體晶片之邊側之方式而使凸形狀交替地反轉而配置。
藉由設為此種配置，在各個接合焊墊BP2之打線接合區域BP2w之間，確保相當於約1個探針區域BP2p之短邊方向之尺寸(寬度)之空間。並且，在該確保之空間中，可增大打線接合區域BP2w之短邊方向之尺寸，伴隨於此，可增大保護膜5之重疊寬度，因此可進一步提高裂痕耐性。
(實施形態3)近年來，出於環境保護及減少環境負載物質之觀點考慮，對於如上述圖2所示搭載半導體晶片3之配線基板2或構成密封半導體晶片3之樹脂密封體10之樹脂構件(樹脂材)，逐漸使用無鹵素型構件。具體而言，規定了電氣‧電子機器之廢棄物之收集及回收，進而，於應自分類回收之廢棄物中除外之物質中含有溴系難燃劑之塑膠，係由WEEE(Waste Electrical and Electronic Equipment，廢電子電機設備)指令所規定。因此，對於構成配線基板2或樹脂密封體10之樹脂構件(樹脂材)使用無鹵素型構件之要求在擴大。配線基板2中所使用之無鹵素型構件，係指氯之含有率為0.09重量%以下、溴之含有率為0.09重量%以下， 且氯與溴之總量為0.15重量%以下之材料。又，構成樹脂密封體10之樹脂構件(樹脂材)中所使用之無鹵素型構件，係指氯之含有率為0.09重量%以下、溴之含有率為0.09重量%以下，且銻之含有率為0.09重量%以下之材料。即，當於配線基板2及構成樹脂密封體10之樹脂構件(樹脂材)中使用無鹵素型構件時，須使用由上述WEEE指令所規定之材料。
然而，可知的是，當對封裝材料使用如上所述之無鹵素型構件時，與先前之封裝材料相比，例如半導體晶片之表面與樹脂構件(樹脂材)之接著性(密著性)會下降，有時會因水分浸入封裝內部而導致半導體裝置之耐濕性下降。
以下所說明之本實施形態3，係有關於一種接合焊墊，其具有下述效果，即，可防止保護膜之裂痕產生，並且即使於使用無鹵素型構件之情形時，亦可確保半導體裝置之耐濕性。
使用圖9及圖10，對本實施形態3之接合焊墊之形狀進行說明。圖9係將接合焊墊放大表示之主要部分平面圖，圖10係將接合焊墊之一部分放大表示之主要部分剖面圖(沿圖9之III-III'線之剖面圖)。
如圖9及圖10所示，與上述實施形態1同樣地，各接合焊墊BP3具有長方形狀，且沿著長邊方向，1個接合焊墊BP3之表面區域被分為打線接合區域BP3w與探針區域BP3p。
接合焊墊BP3例如包含以鋁膜為主材料之金屬膜，其厚度例如為0.85μm。又，當將沿半導體晶片3之邊而配置之鄰接之接合焊墊BP3之間距(P3)設為例如65μm時，作為接合焊墊BP3之尺寸，例如可例示長邊方向之一邊為120μm，短邊方向之一邊為60μm，作為鄰接之接合焊墊BP3之間隔，例如可例示5μm。又，接合焊墊BP3之長邊方向之打線接合區域 BP3w之尺寸例如為50μm，接合焊墊BP3之長邊方向之探針區域BP3p之尺寸例如為62.5μm。
接合焊墊BP3包含半導體晶片之多層配線層中之最上層配線，且自以覆蓋多層配線層之方式而形成之保護膜13上對應於各個接合焊墊BP3所形成之開口部6露出。
保護膜13係為例如將具有第1厚度之第1絕緣膜13a、具有厚於第1厚度之第2厚度之第2絕緣膜13b、及第3絕緣膜13c積層而成之構造。然而，於接合焊墊BP3之周緣部中，以覆蓋接合焊墊BP3之周緣部之方式，形成有第1絕緣膜13a與第2絕緣膜13b之積層膜，進而，以覆蓋該積層膜之接合焊墊BP3上之端部之方式，形成有第3絕緣膜13c。第1絕緣膜13a係例如藉由電漿CVD法而形成之氧化矽膜，其第1厚度例如為0.2μm左右。第2絕緣膜13b係例如藉由高密度電漿CVD法而形成之氧化矽膜，其第2厚度例如為0.9μm左右。第2絕緣膜13b之厚度並不限定於此，只要是可填埋鄰接之接合焊墊BP3之間之厚度即可。又，由於第2絕緣膜13b被期待填埋鄰接之接合焊墊BP3之間，因此較佳為被覆性較好之絕緣膜。第3絕緣膜13c例如係藉由電漿CVD法而形成之氮化矽膜，其厚度例如為0.6μm左右。第3絕緣膜13c具有防止來自外部之水分浸入之功能。
藉由以填埋鄰接之接合焊墊BP3之間之方式形成保護膜13，保護膜13自身對破壞之強度得以增加，從而於接合焊墊BP3之打線接合區域BP3w中，將接合線前端之金屬球接合於該打線接合區域BP3w時，例如即使採用於熱壓接中併用超聲波振動之釘頭式接合法，亦可抑制因超聲波振動所造成之出現在保護膜13上之裂痕及剝離等。
又，在使包含第1絕緣膜13a及第2絕緣膜13b之積層膜成膜，並以重 疊於接合焊墊BP3之周緣部之方式而於接合焊墊BP3上之積層膜上形成開口部6a之後，使第3絕緣膜13c成膜，並以覆蓋上述積層膜之端部之方式而於接合焊墊BP3上之第3絕緣膜13c上形成開口部6，藉此，積層膜完全被第3絕緣膜13c覆蓋，因此可提高半導體晶片之耐濕性。
於以覆蓋包含第1絕緣膜13a及第2絕緣膜13b之積層膜之方式而形成第3絕緣膜13c之情形時，於打線接合區域BP3w中，為了獲得金屬球與接合焊墊BP3之良好之接合，較佳為打線接合區域BP3w之面積較寬，又，於探針區域BP3p中，為了使探針不會與重疊於接合焊墊BP3之周緣部之保護膜13接觸，較佳為探針區域BP3p之面積較寬。因此，於本實施形態3中，與上述實施形態1同樣地，設打線接合區域BP3w中之接合焊墊BP3與保護膜13之重疊寬度為5μm，探針區域BP3p中之接合焊墊BP3與保護膜13之重疊寬度為2.5μm。因此，於打線接合區域BP3w中，例如設構成保護膜13之下部的包含第1絕緣膜13a及第2絕緣膜13b之積層膜之重疊寬度為2.5μm，構成保護膜13之上部之第3絕緣膜13c之重疊寬度為5μm，於探針區域BP3p中，例如設構成保護膜13之下部的包含第1絕緣膜13a及第2絕緣膜13b之積層膜之重疊寬度為1.25μm，構成保護膜13之上部之第3絕緣膜13c之重疊寬度為1.25μm。
如此，根據本實施形態3，可使接合焊墊BP3之打線接合區域BP3w中之保護膜13之重疊寬度寬於接合焊墊BP3之探針區域BP3p中之保護膜13之重疊寬度，除此以外，可以填埋鄰接之接合焊墊BP3之間之方式而形成保護膜13，從而可增加保護膜13自身對破壞之強度。藉此，於接合焊墊BP3之打線接合區域BP3w中，即使金屬球觸及接合焊墊BP3之周緣部，亦可較上述實施形態1進一步抑制保護膜13中之裂痕之產生。又，可 使開口部6以外之區域全部由具有防止水分自外部浸入之功能之第3絕緣膜13c所覆蓋，因此可較上述實施形態1進一步防止水分之浸入。藉此，即使在對半導體裝置使用無鹵素型構件，而導致例如半導體晶片之表面與樹脂構件(樹脂材)之接著性(密著性)下降，而有水分浸入之情形時，亦可確保半導體裝置之耐濕性。
再者，本實施形態3係作為對上述實施形態1之接合焊墊BP1及開口部6進行變形後之一例進行說明，但該變形例亦可適用於上述實施形態2所示之接合焊墊BP2及開口部12。
(實施形態4)本實施形態4係對可防止電源用接合焊墊中產生之保護膜之裂痕的電源用接合焊墊及開口部之形狀進行說明。
在說明本實施形態4之前，為使本實施形態4之電源用接合焊墊之形狀更為明確，使用圖11及圖12，對至今為止本發明者等人所研究之電源用接合焊墊之形狀進行簡單說明。圖11係將電源用接合焊墊放大表示之主要部分平面圖，圖12係將電源用接合焊墊之一部分放大表示之主要部分剖面圖(沿圖11之B-B'線之剖面圖)。
如圖11及圖12所示，本發明者等人所研究之電源用接合焊墊VB係為四邊形狀(例如125μm×120μm)，於該電源用接合焊墊VB之上層，形成有具有2個長方形狀之開口部(例如55μm×115μm)55之保護膜56。被分為打線接合區域VBw與探針區域VBp之電源用接合焊墊VB之表面區域，自2個開口部55分別露出。然而，於此種形狀之電源用接合焊墊VB中，例如當以於熱壓接中併用超聲波振動之釘頭式接合法，將接合線前端之金屬球接合於自2個開口部55露出之2個打線接合區域VBw中時，不僅在保護膜56重疊於電源用接合焊墊VB之周緣部之區域，而且在位於2個開口部55之 間之保護膜56上有時亦會產生裂痕57。
使用圖13及圖14，對本實施形態4之電源用接合焊墊之形狀進行說明。圖13係將電源用接合焊墊放大表示之主要部分平面圖，圖14係將電源用接合焊墊之一部分放大表示之主要部分剖面圖(沿圖13之IV-IV'線之剖面圖)。又，於圖15中，表示本實施形態4之電源用接合焊墊之變形例。
如圖13及圖14所示，本實施形態4之電源用接合焊墊VBP1，與將上述實施形態3中所說明之2個接合焊墊BP3連接之形狀大致相同。然而，於電源用接合焊墊VBP1中，其中一個探針區域BP4p與另一個探針區域BP4p相連接，但其中一個打線接合區域BP4w與另一個打線接合區域BP4w並未連接。
亦即，於電源用接合焊墊VBP1之上層，形成有具有使電源用接合焊墊VBP1之上面之一部分跨及打線接合區域BP4w及探針區域BP4p而露出之2個開口部6之保護膜13，電源用接合焊墊VBP1之打線接合區域BP4w及探針區域BP4p自2個開口部6分別露出。並且，僅於2個開口部6之間之電源用接合焊墊VBP1之打線接合區域BP4w中形成狹縫14。該狹縫14之寬度例如為5μm。
例如當採用在熱壓接中併用超聲波振動之釘頭式接合法而分別將金屬球接合於2個打線接合區域BP4w時，藉由如此般在其中一個打線接合區域BP4w與另一個打線接合區域BP4w之間設置狹縫14，可利用以狹縫14所切斷之部分來緩和超聲波振動對保護膜13造成之應力等，因此可防止位於2個開口部6之間之保護膜13上產生之裂痕。進而，與上述實施形態1同樣地，藉由將打線接合區域BP4w之重疊於電源用接合焊墊VBP1之周緣部之保護膜13之寬度設為例如5μm，亦可防止電源用接合焊墊VBP1之端部 側壁上產生之保護膜13之裂痕。藉由將探針區域BP4p之重疊於電源用接合焊墊VBP1之周緣部之保護膜13之寬度設為例如2.5μm，可防止因探針造成之電源用接合焊墊VBP1上之保護膜13之破壞。
將本實施形態4之電源用接合焊墊之變形例示於圖15。圖15係將電源用接合焊墊之一部分放大表示之主要部分剖面圖。
於上述圖14所示之電源用接合焊墊VBP1中，於其上依序堆積第1絕緣膜13a及第2絕緣膜13b而形成2層膜，於該2層膜上暫時形成開口部6a之後，於2層膜上形成第3絕緣膜13c，並完全覆蓋2層膜而於第3絕緣膜13c上形成開口部6。與此相對，於圖15所示之電源用接合焊墊VBP2中，於其上依序堆積第1絕緣膜13a、第2絕緣膜13b、及第3絕緣膜13c而形成3層膜之後，於該3層膜上形成開口部6。藉由採用電源用接合焊墊VBP2之構造，較之製造電源用接合焊墊VBP1之情形，可減少製造步驟數。
如此，根據本實施形態4，於電源用接合焊墊VBP1之打線接合區域BP4w中，將重疊於電源用接合焊墊VBP1之周緣部之寬度，設為即使接合線前端之金屬球觸及電源用接合焊墊VBP1之周緣部亦不會在保護膜13上出現裂痕之寬度，進而，於2個打線接合區域BP4w之間設置狹縫14，藉此，於電源用接合焊墊VBP1中，亦可抑制2個開口部6之間之保護膜13上之裂痕之產生。
以上，根據實施形態，對本發明者所完成之發明進行了具體說明，但本發明並不限定於上述實施形態，在不脫離其主旨之範圍內當然可進行各種變更。
[產業上之可利用性]
本發明可適用於搭載具有在打線接合連接或倒裝晶片連接等中所用 之接合焊墊之半導體晶片的半導體裝置。

Claims (21)

  1. 一種半導體裝置，其包含： 半導體晶片，其具有：第一主面(first main surface)，與上述第一主面為相反側之第二主面(second main surface)，延伸於第一方向之邊，及形成於上述第一主面且沿上述邊延伸之複數個接合焊墊； 各上述接合焊墊具有：第一邊及與上述第一邊為相反側之第二邊，且延伸於上述第一方向； 其中上述半導體晶片之上述第一主面被形成有複數個開口部的保護膜覆蓋， 各上述接合焊墊之上面(upper surface)之周緣部被上述保護膜覆蓋，且各上述接合焊墊之上述上面之上述周緣部以外的部分係自上述複數個開口部中之對應者露出； 各上述接合焊墊之上述上面被區分(sectioned)為接合區域及探針區域(probe region)； 於俯視時，在垂直於上述第一方向之第二方向上，上述保護膜與上述接合區域中之各上述接合焊墊之上述周緣部之重疊寬度係較上述保護膜與上述探針區域中之各上述接合焊墊之上述周緣部之重疊寬度寬； 於俯視時，接觸線(contact trace)沿上述第二方向形成於上述探針區域中。
  2. 如請求項1之半導體裝置，其中於俯視時，上述保護膜中之開口部具有凸形狀。
  3. 如請求項2之半導體裝置，其更包括： 配線基板，其具有： 表面(obverse surface)，其形成有複數條接合引線，及 背面(back surface)，其與上述表面為相反側； 焊墊區域，其形成有上述複數個接合焊墊，且於上述半導體晶片之上述第一主面上，沿上述半導體晶片之周圍配置有上述複數個接合焊墊；及 核心區域，其形成有積體電路，且於上述焊墊區域之內側配置有該積體電路；且 使上述配線基板之上述表面與上述半導體晶片之上述第二主面對向地，於上述配線基板之上述表面上搭載上述半導體晶片， 上述接合焊墊與上述接合引線藉由接合線而電性連接， 以上述接合區域較上述探針區域更靠近上述半導體晶片之上述邊之方式而配置上述接合焊墊。
  4. 如請求項2之半導體裝置，其中於俯視時，在上述第一方向上，上述保護膜與上述接合區域中之各上述接合焊墊之上述周緣部之重疊寬度係較上述保護膜與上述探針區域中之各上述接合焊墊之上述周緣部之重疊寬度寬。
  5. 如請求項3之半導體裝置，其中上述接合線為金線，上述接合焊墊係包含鋁膜為主材料之金屬膜。
  6. 如請求項5之半導體裝置，其中上述保護膜配置於相鄰之上述接合焊墊之間。
  7. 如請求項6之半導體裝置，其中上述保護膜包含形成有複數個絕緣膜之積層膜，且最上層之上述絕緣膜係為氮化矽膜。
  8. 如請求項7之半導體裝置，其中於俯視時，在上述第二方向上，上述保護膜與上述接合區域中之各上述接合焊墊之周緣部之重疊寬度寬於2.5 μm。
  9. 如請求項8之半導體裝置，其中於俯視時，在上述第二方向上，上述保護膜與上述接合區域中之各上述接合焊墊之周緣部之重疊寬度為5 μm，且在上述第二方向上，上述保護膜與上述探針區域中之各上述接合焊墊之周緣部之重疊寬度為2.5 μm。
  10. 如請求項9之半導體裝置，其中 上述保護膜係由具有第1厚度之第1絕緣膜、上述第1絕緣膜上之具有較上述第1厚度厚之第2厚度之第2絕緣膜、及上述第2絕緣膜之上之最上層之第3絕緣膜所構成， 各上述接合焊墊之周緣部係由包含上述第1絕緣膜及上述第2絕緣膜之積層膜所覆蓋，且 上述第3絕緣膜進而覆蓋上述接合焊墊上之上述第1絕緣膜及上述第2絕緣膜之端部。
  11. 如請求項10之半導體裝置，其中上述第3絕緣膜與各上述接合焊墊之重疊寬度為2.5 μm。
  12. 如請求項11之半導體裝置，其中上述半導體晶片、上述接合線、及上述配線基板之上述表面之一部分係藉由包含絕緣性樹脂之樹脂密封體而密封。
  13. 如請求項12之半導體裝置，其中上述配線基板及構成上述樹脂密封體之樹脂構件係為無鹵素型(halogen free)構件。
  14. 如請求項13之半導體裝置，其中於上述配線基板之上述背面，具備焊錫球(solder ball)。
  15. 如請求項1之半導體裝置，其更包括： 配線基板，其具有形成有複數條接合引線之表面； 焊墊區域，其形成有上述接合焊墊，且於上述半導體晶片之上述第一主面上，沿上述半導體晶片之周圍配置有上述接合焊墊；及 核心區域，其形成有積體電路，且於上述焊墊區域之內側配置有該積體電路；且 使上述配線基板之上述表面與上述半導體晶片之上述第一主面對向地，於上述配線基板之上述表面上搭載上述半導體晶片， 上述接合焊墊與上述接合引線藉由凸塊而電性連接， 上述接合焊墊係以上述探針區域較上述接合區域更靠近上述半導體晶片之上述邊之方式而配置。
  16. 如請求項15之半導體裝置，其中上述積體電路包括CPU、DSP、RAM、PLL及DLL。
  17. 一種半導體裝置，其包含： 半導體晶片，其具有：主面，該主面上沿著延伸於第一方向之邊形成有複數個接合焊墊；及 配線構件，其具有：頂面(top surface)，該頂面之上搭載有上述半導體晶片，且電性連接於該半導體晶片； 其中各上述接合焊墊之上面之周緣部被形成有複數個開口部之絕緣膜覆蓋，且各上述接合焊墊之上述上面之上述周緣部以外的部分係自上述複數個開口部中之對應者露出； 各上述接合焊墊之上述上面被區分為接合區域及探針區域； 於俯視時，在垂直於上述第一方向之第二方向上，上述絕緣膜與上述接合區域中之各上述接合焊墊之上述周緣部之重疊寬度係較上述絕緣膜與上述探針區域中之各上述接合焊墊之上述周緣部之重疊寬度寬； 於俯視時，接觸線沿上述第二方向形成於上述探針區域中。
  18. 如請求項17之半導體裝置，其中於俯視時，自各接合焊墊之上述探針區域之上述絕緣膜之上述開口部露出之部分之面積係較自各接合焊墊之上述接合區域之上述絕緣膜之上述開口部露出之部分之面積大。
  19. 如請求項17之半導體裝置，其中 上述半導體晶片經由複數個金屬導體(metal conductors)電性連接於上述配線構件；且 上述複數個金屬導體接合於對應之接合焊墊之上述接合區域。
  20. 如請求項19之半導體裝置，其中 使上述半導體晶片之上述主面與上述配線構件之上述頂面於相同方向對向地，於上述配線構件之上述頂面上搭載上述半導體晶片；且 上述複數個金屬導體係金屬線(metal wires)。
  21. 如請求項19之半導體裝置，其中於俯視時，各接合焊墊之上述接合區域係較該接合焊墊之上述探針區域更靠近上述半導體晶片之上述邊。
TW106121861A 2009-05-20 2010-04-20 Semiconductor device TWI646644B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-121857 2009-05-20
JP2009121857A JP5160498B2 (ja) 2009-05-20 2009-05-20 半導体装置

Publications (2)

Publication Number Publication Date
TW201733061A TW201733061A (zh) 2017-09-16
TWI646644B true TWI646644B (zh) 2019-01-01

Family

ID=43103961

Family Applications (3)

Application Number Title Priority Date Filing Date
TW099112370A TWI548051B (zh) 2009-05-20 2010-04-20 Semiconductor device
TW105120867A TWI596724B (zh) 2009-05-20 2010-04-20 Semiconductor device
TW106121861A TWI646644B (zh) 2009-05-20 2010-04-20 Semiconductor device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW099112370A TWI548051B (zh) 2009-05-20 2010-04-20 Semiconductor device
TW105120867A TWI596724B (zh) 2009-05-20 2010-04-20 Semiconductor device

Country Status (4)

Country Link
US (4) US8946705B2 (zh)
JP (1) JP5160498B2 (zh)
CN (3) CN101894816B (zh)
TW (3) TWI548051B (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115321B2 (en) * 2009-04-30 2012-02-14 Lsi Corporation Separate probe and bond regions of an integrated circuit
JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
JP5618873B2 (ja) * 2011-03-15 2014-11-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2013062328A (ja) * 2011-09-12 2013-04-04 Toshiba Corp 半導体装置
JP5926988B2 (ja) 2012-03-08 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US9111847B2 (en) * 2012-06-15 2015-08-18 Infineon Technologies Ag Method for manufacturing a chip package, a method for manufacturing a wafer level package, a chip package and a wafer level package
WO2013010512A2 (en) * 2012-10-22 2013-01-24 Spreadtrum Communications (Shanghai) Co., Ltd. Apparatus and method of electrical testing for flip chip
CN103107128B (zh) * 2013-01-14 2014-12-17 武汉新芯集成电路制造有限公司 一种三维芯片结构的金属键合的方法
JP6149503B2 (ja) * 2013-05-17 2017-06-21 住友電気工業株式会社 半導体装置
JP5858952B2 (ja) * 2013-05-20 2016-02-10 三菱電機株式会社 半導体装置の製造方法
JP6235353B2 (ja) * 2014-01-22 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6279339B2 (ja) * 2014-02-07 2018-02-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6215755B2 (ja) 2014-04-14 2017-10-18 ルネサスエレクトロニクス株式会社 半導体装置
JP6522980B2 (ja) * 2015-02-18 2019-05-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9881870B2 (en) * 2015-12-30 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN109166838A (zh) * 2018-08-29 2019-01-08 上海华虹宏力半导体制造有限公司 顶层金属键合垫的引出结构及其制造方法
CN109719381A (zh) * 2019-02-21 2019-05-07 巴中市特兴智能科技有限公司 一种自动焊接键合金线的工艺方法
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
KR20210066181A (ko) 2019-11-28 2021-06-07 엘지디스플레이 주식회사 표시 장치
US11043435B1 (en) * 2020-05-18 2021-06-22 Innogrit Technologies Co., Ltd. Semiconductor die with hybrid wire bond pads
TWI836611B (zh) * 2022-09-19 2024-03-21 華東科技股份有限公司 晶墊具保護層的晶片封裝結構

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200515519A (en) * 2003-10-29 2005-05-01 Taiwan Semiconductor Mfg Co Ltd Bonding pad structure
US20060186405A1 (en) * 2005-02-08 2006-08-24 Nec Electronics Corporation Semiconductor device and manufacturing process therefor
TW200802643A (en) * 2006-06-14 2008-01-01 Novatek Microelectronics Corp Chip structure

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0220034A (ja) * 1988-07-07 1990-01-23 Matsushita Electron Corp 半導体装置
JPH0379055A (ja) 1989-08-23 1991-04-04 New Japan Radio Co Ltd 半導体素子
JP3022819B2 (ja) * 1997-08-27 2000-03-21 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
JP3843624B2 (ja) 1998-11-27 2006-11-08 松下電器産業株式会社 半導体集積回路装置及び半導体集積回路装置の組立方法
JP2001338955A (ja) 2000-05-29 2001-12-07 Texas Instr Japan Ltd 半導体装置及びその製造方法
KR100868419B1 (ko) * 2001-06-07 2008-11-11 가부시끼가이샤 르네사스 테크놀로지 반도체장치 및 그 제조방법
JP2003142485A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP4065799B2 (ja) * 2003-03-12 2008-03-26 株式会社ルネサステクノロジ 超音波接合装置および方法
JP4803966B2 (ja) * 2004-03-31 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2006303452A (ja) * 2005-03-25 2006-11-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US20070075396A1 (en) * 2005-09-30 2007-04-05 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
KR100727490B1 (ko) * 2005-12-08 2007-06-13 삼성전자주식회사 본딩 영역과 프로빙 영역을 구분하기 위한 식별표시가구비된 반도체 장치 및 그 제조방법
JP5050384B2 (ja) * 2006-03-31 2012-10-17 富士通セミコンダクター株式会社 半導体装置およびその製造方法
JP4951276B2 (ja) 2006-05-29 2012-06-13 ルネサスエレクトロニクス株式会社 半導体チップおよび半導体装置
US7397127B2 (en) * 2006-10-06 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding and probing pad structures
JP5064158B2 (ja) * 2007-09-18 2012-10-31 新光電気工業株式会社 半導体装置とその製造方法
JP2009218264A (ja) * 2008-03-07 2009-09-24 Elpida Memory Inc 半導体装置
JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
JP5443827B2 (ja) * 2009-05-20 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200515519A (en) * 2003-10-29 2005-05-01 Taiwan Semiconductor Mfg Co Ltd Bonding pad structure
US20060186405A1 (en) * 2005-02-08 2006-08-24 Nec Electronics Corporation Semiconductor device and manufacturing process therefor
TW200802643A (en) * 2006-06-14 2008-01-01 Novatek Microelectronics Corp Chip structure

Also Published As

Publication number Publication date
US8946705B2 (en) 2015-02-03
TWI548051B (zh) 2016-09-01
TWI596724B (zh) 2017-08-21
TW201637161A (zh) 2016-10-16
CN101894816A (zh) 2010-11-24
US20100295043A1 (en) 2010-11-25
CN103943580A (zh) 2014-07-23
US20180040521A1 (en) 2018-02-08
JP5160498B2 (ja) 2013-03-13
TW201104816A (en) 2011-02-01
JP2010272622A (ja) 2010-12-02
CN106024744A (zh) 2016-10-12
US20150137125A1 (en) 2015-05-21
US20170018470A1 (en) 2017-01-19
CN101894816B (zh) 2014-06-11
US10163740B2 (en) 2018-12-25
US9824944B2 (en) 2017-11-21
TW201733061A (zh) 2017-09-16

Similar Documents

Publication Publication Date Title
TWI646644B (zh) Semiconductor device
US20230178498A1 (en) Semiconductor device
US7391114B2 (en) Electrode pad section for external connection
JP3701542B2 (ja) 半導体装置およびその製造方法
US8742584B2 (en) Semiconductor device
US20160027754A1 (en) Semiconductor device
US8067950B2 (en) Semiconductor device including chip
CN108461411B (zh) 封装结构
US7834351B2 (en) Semiconductor device
JP2011222738A (ja) 半導体装置の製造方法
JP5732493B2 (ja) 半導体装置
JP3559554B2 (ja) 半導体装置およびその製造方法
TWI467723B (zh) 半導體封裝件及其製法
TWI642159B (zh) 封裝結構
JP5331934B2 (ja) 半導体装置
CN106158798A (zh) 一种芯片结构及其封装方法
US11694950B2 (en) Semiconductor package
JP2012124426A (ja) 半導体装置、及びその製造方法
US6748576B2 (en) Active trace rerouting
JPH0936172A (ja) 半導体装置及びその製造方法
JP2004014900A (ja) 半導体装置および半導体装置のパッケージ方法
JP2000294693A (ja) 半導体装置用中継基板及び半導体装置