MXPA04011463A - Estructura mejorada de vias apiladas en portadores de dispositivos electronicos multicapa. - Google Patents
Estructura mejorada de vias apiladas en portadores de dispositivos electronicos multicapa.Info
- Publication number
- MXPA04011463A MXPA04011463A MXPA04011463A MXPA04011463A MXPA04011463A MX PA04011463 A MXPA04011463 A MX PA04011463A MX PA04011463 A MXPA04011463 A MX PA04011463A MX PA04011463 A MXPA04011463 A MX PA04011463A MX PA04011463 A MXPA04011463 A MX PA04011463A
- Authority
- MX
- Mexico
- Prior art keywords
- vias
- conductive
- electronic device
- conductive layers
- axis
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Connecting Device With Holders (AREA)
Abstract
Se describe una estructura de vias apiladas (200) adaptada para transmitir senales de alta frecuencia o corriente de alta intensidad a traves de las capas conductivas de un portador de dispositivos electronicos. La estructura de vias apiladas comprende al menos tres pistas conductivas (205a, 205b, 205c) que pertenecen a tres capas conductivas adyacentes (110a, 110b, 110c) separadas por capas dielectricas (120), alineadas de acuerdo con el eje z. Las conexiones entre estos pistas conductivas se hacen con al menos dos vias (210, 215) entre cada capa conductiva. Las vias conectas a un lado de un pista conductiva se encuentran dispuestas de tal modo que no se encuentran alineadas con las conectadas en el otro lado de acuerdo con el eje z. En una modalidad preferida, la forma de estas pistas conductivas alineadas se observa como un disco o un anillo anular y se utilizan cuatro vias para conectar dos capas conductivas adyacentes. Estas cuatro vias se encuentran dispuestas simetricamente en cada una de dichas pistas conductivas. La posicion de las vias entre una primera y una segunda capas conductivas adyacentes y entre una segunda y una tercera capas conductivas adyacentes forma un angulo de 45¦ de acuerdo con el eje z.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02368053 | 2002-05-23 | ||
PCT/EP2003/012647 WO2004017687A1 (en) | 2002-05-23 | 2003-04-18 | Improved structure of stacked vias in multiple layer electronic device carriers |
Publications (1)
Publication Number | Publication Date |
---|---|
MXPA04011463A true MXPA04011463A (es) | 2005-07-01 |
Family
ID=31725517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MXPA04011463A MXPA04011463A (es) | 2002-05-23 | 2003-04-18 | Estructura mejorada de vias apiladas en portadores de dispositivos electronicos multicapa. |
Country Status (10)
Country | Link |
---|---|
US (1) | US7319197B2 (es) |
EP (1) | EP1506701B1 (es) |
JP (1) | JP4056525B2 (es) |
KR (1) | KR100702554B1 (es) |
CN (1) | CN100370887C (es) |
AT (1) | ATE367077T1 (es) |
AU (1) | AU2003276277A1 (es) |
DE (1) | DE60314868T2 (es) |
MX (1) | MXPA04011463A (es) |
WO (1) | WO2004017687A1 (es) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004214657A (ja) | 2003-01-07 | 2004-07-29 | Internatl Business Mach Corp <Ibm> | プリント回路板製造用水溶性保護ペースト |
US7652896B2 (en) * | 2004-12-29 | 2010-01-26 | Hewlett-Packard Development Company, L.P. | Component for impedance matching |
US20080067665A1 (en) * | 2006-09-20 | 2008-03-20 | Azniza Binti Abd Aziz | Via structure |
US7649265B2 (en) * | 2006-09-29 | 2010-01-19 | Intel Corporation | Micro-via structure design for high performance integrated circuits |
US7531373B2 (en) | 2007-09-19 | 2009-05-12 | Micron Technology, Inc. | Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry |
US8242593B2 (en) * | 2008-01-27 | 2012-08-14 | International Business Machines Corporation | Clustered stacked vias for reliable electronic substrates |
CN101562951B (zh) * | 2008-04-18 | 2011-05-11 | 欣兴电子股份有限公司 | 线路板及其制作方法 |
JP5397007B2 (ja) * | 2009-05-14 | 2014-01-22 | 富士通株式会社 | プリント配線板および電子部品パッケージ |
US8735734B2 (en) * | 2009-07-23 | 2014-05-27 | Lexmark International, Inc. | Z-directed delay line components for printed circuit boards |
US8198547B2 (en) | 2009-07-23 | 2012-06-12 | Lexmark International, Inc. | Z-directed pass-through components for printed circuit boards |
KR101161971B1 (ko) * | 2010-07-21 | 2012-07-04 | 삼성전기주식회사 | 다층 회로 기판 및 다층 회로 기판의 제조 방법 |
KR101696644B1 (ko) * | 2010-09-15 | 2017-01-16 | 삼성전자주식회사 | 3차원 수직 배선을 이용한 rf 적층 모듈 및 이의 배치 방법 |
US9078374B2 (en) | 2011-08-31 | 2015-07-07 | Lexmark International, Inc. | Screening process for manufacturing a Z-directed component for a printed circuit board |
US8943684B2 (en) * | 2011-08-31 | 2015-02-03 | Lexmark International, Inc. | Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board |
US8790520B2 (en) | 2011-08-31 | 2014-07-29 | Lexmark International, Inc. | Die press process for manufacturing a Z-directed component for a printed circuit board |
US8752280B2 (en) | 2011-09-30 | 2014-06-17 | Lexmark International, Inc. | Extrusion process for manufacturing a Z-directed component for a printed circuit board |
US8658245B2 (en) | 2011-08-31 | 2014-02-25 | Lexmark International, Inc. | Spin coat process for manufacturing a Z-directed component for a printed circuit board |
US9009954B2 (en) | 2011-08-31 | 2015-04-21 | Lexmark International, Inc. | Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material |
JP5765633B2 (ja) * | 2011-12-22 | 2015-08-19 | 株式会社フジクラ | プリント配線板及びその製造方法 |
TWI449475B (zh) * | 2012-01-09 | 2014-08-11 | Novatek Microelectronics Corp | 電路板 |
US8822838B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for reducing radiated emissions |
US8822840B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for controlling transmission line impedance |
US8830692B2 (en) | 2012-03-29 | 2014-09-09 | Lexmark International, Inc. | Ball grid array systems for surface mounting an integrated circuit using a Z-directed printed circuit board component |
US8912452B2 (en) | 2012-03-29 | 2014-12-16 | Lexmark International, Inc. | Z-directed printed circuit board components having different dielectric regions |
TW201431450A (zh) * | 2013-01-29 | 2014-08-01 | Hon Hai Prec Ind Co Ltd | 印刷電路板 |
CN103974519B (zh) * | 2013-01-29 | 2017-02-08 | 江苏传艺科技股份有限公司 | 印刷电路板 |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9871017B2 (en) * | 2016-01-04 | 2018-01-16 | Infineon Technologies Ag | Multi-level chip interconnect |
JP6674016B2 (ja) * | 2016-03-24 | 2020-04-01 | 京セラ株式会社 | 印刷配線板およびその製造方法 |
JP6730960B2 (ja) * | 2017-05-24 | 2020-07-29 | 日本特殊陶業株式会社 | 配線基板 |
US10916519B2 (en) | 2018-06-08 | 2021-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing semiconductor package with connection structures including via groups |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
JP6869209B2 (ja) * | 2018-07-20 | 2021-05-12 | 日本特殊陶業株式会社 | 配線基板 |
US10727190B2 (en) * | 2018-12-27 | 2020-07-28 | Tektronix, Inc. | Compound via RF transition structure in a multilayer high-density interconnect |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US11776899B2 (en) * | 2020-05-11 | 2023-10-03 | Mediatek Inc. | Via array design for multi-layer redistribution circuit structure |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US20240074053A1 (en) * | 2022-08-25 | 2024-02-29 | Nvidia Corporation | Clustered microvia structure for a high-density interface pcb |
JP7448060B1 (ja) | 2023-03-27 | 2024-03-12 | Toto株式会社 | 静電チャック |
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JPH0797705B2 (ja) | 1989-07-17 | 1995-10-18 | 日本電気株式会社 | 多層セラミツク基板 |
JPH03142896A (ja) | 1989-10-27 | 1991-06-18 | Fujitsu Ltd | 多層回路基板 |
JP2767645B2 (ja) * | 1990-03-07 | 1998-06-18 | 富士通株式会社 | 多層配線基板の製造方法 |
JP2503725B2 (ja) * | 1990-05-18 | 1996-06-05 | 日本電気株式会社 | 多層配線基板 |
JPH06326471A (ja) | 1993-05-17 | 1994-11-25 | Sony Corp | 多層配線基板 |
US5378927A (en) * | 1993-05-24 | 1995-01-03 | International Business Machines Corporation | Thin-film wiring layout for a non-planar thin-film structure |
JPH088393A (ja) | 1994-06-23 | 1996-01-12 | Fujitsu Ltd | 半導体装置 |
US5699613A (en) * | 1995-09-25 | 1997-12-23 | International Business Machines Corporation | Fine dimension stacked vias for a multiple layer circuit board structure |
JPH1174651A (ja) * | 1997-03-13 | 1999-03-16 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JP3961092B2 (ja) * | 1997-06-03 | 2007-08-15 | 株式会社東芝 | 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法 |
JP3562568B2 (ja) * | 1999-07-16 | 2004-09-08 | 日本電気株式会社 | 多層配線基板 |
US6362438B1 (en) * | 1999-12-15 | 2002-03-26 | Intel Corporation | Enhanced plated-through hole and via contact design |
US7091424B2 (en) * | 2002-10-10 | 2006-08-15 | International Business Machines Corporation | Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers |
-
2003
- 2003-04-18 EP EP03787806A patent/EP1506701B1/en not_active Expired - Lifetime
- 2003-04-18 DE DE60314868T patent/DE60314868T2/de not_active Expired - Lifetime
- 2003-04-18 AT AT03787806T patent/ATE367077T1/de not_active IP Right Cessation
- 2003-04-18 WO PCT/EP2003/012647 patent/WO2004017687A1/en active IP Right Grant
- 2003-04-18 CN CNB038115107A patent/CN100370887C/zh not_active Expired - Lifetime
- 2003-04-18 AU AU2003276277A patent/AU2003276277A1/en not_active Abandoned
- 2003-04-18 JP JP2004528511A patent/JP4056525B2/ja not_active Expired - Fee Related
- 2003-04-18 US US10/515,511 patent/US7319197B2/en not_active Expired - Lifetime
- 2003-04-18 MX MXPA04011463A patent/MXPA04011463A/es active IP Right Grant
- 2003-04-18 KR KR1020047017762A patent/KR100702554B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP4056525B2 (ja) | 2008-03-05 |
DE60314868D1 (de) | 2007-08-23 |
KR20050009998A (ko) | 2005-01-26 |
EP1506701B1 (en) | 2007-07-11 |
KR100702554B1 (ko) | 2007-04-04 |
DE60314868T2 (de) | 2008-03-13 |
ATE367077T1 (de) | 2007-08-15 |
AU2003276277A1 (en) | 2004-03-03 |
CN100370887C (zh) | 2008-02-20 |
WO2004017687A1 (en) | 2004-02-26 |
EP1506701A1 (en) | 2005-02-16 |
US20050156319A1 (en) | 2005-07-21 |
CN1656861A (zh) | 2005-08-17 |
JP2005527122A (ja) | 2005-09-08 |
US7319197B2 (en) | 2008-01-15 |
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