JP4056525B2 - 積層型ビア構造体 - Google Patents
積層型ビア構造体 Download PDFInfo
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- JP4056525B2 JP4056525B2 JP2004528511A JP2004528511A JP4056525B2 JP 4056525 B2 JP4056525 B2 JP 4056525B2 JP 2004528511 A JP2004528511 A JP 2004528511A JP 2004528511 A JP2004528511 A JP 2004528511A JP 4056525 B2 JP4056525 B2 JP 4056525B2
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- conductive
- conductive path
- vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Connecting Device With Holders (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Description
第1の導電層に属す第1の導電路と第2の導電層に属す第2の導電路とを接続する、電子装置キァリア中の積層型ビア構造体であって、前記第1の導電層および前記第2の導電層は少なくとも1つの第3の導電層によって分離されており、前記導電層群の各々の間には誘電体層が配置されており、
前記少なくとも1つの第3の導電層に属す第3の導電路であって、前記第3の導電路は前記導電層群と垂直な軸に従って前記第1の導電路および前記第2の導電路の少なくとも一部分と位置合わせされている、第3の導電路と、
前記第1の導電路と前記第3の導電路との間に配置された少なくとも2つのビアを備えた第1のビアの組と、
前記第2の導電路と前記第3の導電路との間に配置された少なくとも2つのビアを備えた第2のビアの組とを備え、
前記第3の導電路は前記第1のビアの組および前記第2のビアの組によって前記第1の導電路および前記第2の導電路に接続されており、前記第1のビアの組のビアと前記第2のビアの組のビアとは未位置合わせである、
積層型ビア構造体。
105 コア
110a 導電層
110b 導電層
110c 導電層
115 表面層
120 誘電体層
125−1 はんだボール
125−5 はんだボール
130 盲管スルーホール
135 導電路
140 導電路
145 ビア
150 ビア
155 ビア
135’ 導電路
140’ 導電路
145’ ビア
150’ ビア
155’ ビア
200 積層型ビア構造体
205a 第1の導電路
205b 環状リング
205c 導電路
210 ビア
215 ビア
300a 導電層
300b 導電層
300c 導電層
305−1 導電路
305−2 導電路
310 導電路
315−1 部分環状リング
315−2 部分環状リング
320−1 ビア
320−2 ビア
325−1 導電路
325−2 導電路
330−1 ビア
330−2 ビア
335−1 導電路
335−2 導電路
340 導電路
345−1 部分環状リング
345−2 部分環状リング
345’−1 導電路
345’−2 導電路
400 コア
405a−1 付加導電層
405b−1 付加導電層
405a−2 付加導電層
405b−2 付加導電層
405c−1 外部導電層
405c−2 外部導電層
410 誘電体材料
415−1 積層型ビア構造体
415−2 積層型ビア構造体
420 埋め込みスルーホール
425 はんだボール
430 導電路
435−1 金属ランド
435−2 金属ランド
440−1 ホール
440−2 ホール
445−1 導電路
445−2 導電路
450−1 ビア
450−2 ビア
455−1 銅ランド
500−1 環状リング
500−2 環状リング
505−1 ビア
505−2 ビア
505−3 ビア
510−1 ビア
510−2 ビア
510−3 ビア
515−1 ビア
515−2 ビア
515−3 ビア
Claims (7)
- 第1の導電層(110a)に属す、第1の導電路(205a)と第2の導電層(110c)に属す、第2の導電路(205c)とを接続する、電子装置キァリア中の積層型ビア構造体(200)であって、前記第1の導電層および前記第2の導電層は少なくとも1つの第3の導電層(100b)によって分離されており、前記導電層群の各々の間には誘電体層(120)が配置されており、
前記少なくとも1つの第3の導電層に属す、切り欠きまたは、突部を設けた環状リング形状の第3の導電路(205b)であって、前記第3の導電路は前記導電層群と垂直な軸を基準にして前記第1の導電路および前記第2の導電路の少なくとも一部分と位置合わせされている、第3の導電路と、
前記第1の導電路と前記第3の導電路との間に配置された少なくとも2つのビアを備えた第1のビアの組(210)と、
前記第2の導電路と前記第3の導電路との間に配置された少なくとも2つのビアを備えた第2のビアの組(215)とを備え、
前記第3の導電路は前記第1のビアの組および前記第2のビアの組によって前記第1の導電路および前記第2の導電路に接続されており、前記第1のビアの組のビアと前記第2のビアの組のビアとは未位置合わせである、
積層型ビア構造体。 - 前記第1のビアの組または前記第2のビアの組が4つのビアを備えている、
請求項1に記載の積層型ビア構造体。 - 前記第1のビアの組または前記第2のビアの組の隣接する2つのビアと、前記第3の導電路ならびに前記第1の導電路および前記第2の導電路の前記位置合わせされた部分の中心とがなす角が90°に等しい、
請求項2に記載の積層型ビア構造体。 - 前記第1のビアの組の1つのビアと、前記第2のビアの組の最近接するビアと、前記第3の導電路ならびに前記第1の導電路および前記第2の導電路の前記位置合わせされた部分の中心とがなす角が45°に等しい、
請求項3に記載の積層型ビア構造体。 - 前記第1のビアの組または前記第2のビアの組の前記ビア群は前記第3の導電路ならびに前記第1の導電路および前記第2の導電路の前記位置合わせされた部分の中心に対して等距離の場所にある、
請求項1乃至請求項4のうちの1項に記載の積層型ビア構造体。 - 前記第1の導電路または前記第2の導電路ははんだボールに接続しうるように適合している、
請求項1乃至請求項5のうちの1項に記載の積層型ビア構造体。 - 前記第1の導電路または前記第2の導電路は閉管スルーホールに接続しうるように適合している、
請求項1乃至請求項6のうちの1項に記載の積層型ビア構造体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02368053 | 2002-05-23 | ||
PCT/EP2003/012647 WO2004017687A1 (en) | 2002-05-23 | 2003-04-18 | Improved structure of stacked vias in multiple layer electronic device carriers |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005527122A JP2005527122A (ja) | 2005-09-08 |
JP4056525B2 true JP4056525B2 (ja) | 2008-03-05 |
Family
ID=31725517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004528511A Expired - Fee Related JP4056525B2 (ja) | 2002-05-23 | 2003-04-18 | 積層型ビア構造体 |
Country Status (10)
Country | Link |
---|---|
US (1) | US7319197B2 (ja) |
EP (1) | EP1506701B1 (ja) |
JP (1) | JP4056525B2 (ja) |
KR (1) | KR100702554B1 (ja) |
CN (1) | CN100370887C (ja) |
AT (1) | ATE367077T1 (ja) |
AU (1) | AU2003276277A1 (ja) |
DE (1) | DE60314868T2 (ja) |
MX (1) | MXPA04011463A (ja) |
WO (1) | WO2004017687A1 (ja) |
Families Citing this family (41)
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US20080067665A1 (en) * | 2006-09-20 | 2008-03-20 | Azniza Binti Abd Aziz | Via structure |
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CN103974519B (zh) * | 2013-01-29 | 2017-02-08 | 江苏传艺科技股份有限公司 | 印刷电路板 |
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- 2003-04-18 AT AT03787806T patent/ATE367077T1/de not_active IP Right Cessation
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CN100370887C (zh) | 2008-02-20 |
KR100702554B1 (ko) | 2007-04-04 |
DE60314868D1 (de) | 2007-08-23 |
JP2005527122A (ja) | 2005-09-08 |
KR20050009998A (ko) | 2005-01-26 |
CN1656861A (zh) | 2005-08-17 |
ATE367077T1 (de) | 2007-08-15 |
EP1506701A1 (en) | 2005-02-16 |
AU2003276277A1 (en) | 2004-03-03 |
MXPA04011463A (es) | 2005-07-01 |
WO2004017687A1 (en) | 2004-02-26 |
DE60314868T2 (de) | 2008-03-13 |
US20050156319A1 (en) | 2005-07-21 |
US7319197B2 (en) | 2008-01-15 |
EP1506701B1 (en) | 2007-07-11 |
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