DE60314868D1 - Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern - Google Patents

Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern

Info

Publication number
DE60314868D1
DE60314868D1 DE60314868T DE60314868T DE60314868D1 DE 60314868 D1 DE60314868 D1 DE 60314868D1 DE 60314868 T DE60314868 T DE 60314868T DE 60314868 T DE60314868 T DE 60314868T DE 60314868 D1 DE60314868 D1 DE 60314868D1
Authority
DE
Germany
Prior art keywords
conductive
contact holes
improved structure
construction elements
multilayer electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314868T
Other languages
English (en)
Other versions
DE60314868T2 (de
Inventor
Michele Castriotta
Stefano Oggioni
Gianluca Rogiani
Mauro Spreafico
Giorgio Viero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE60314868D1 publication Critical patent/DE60314868D1/de
Application granted granted Critical
Publication of DE60314868T2 publication Critical patent/DE60314868T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Connecting Device With Holders (AREA)
DE60314868T 2002-05-23 2003-04-18 Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern Expired - Lifetime DE60314868T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02368053 2002-05-23
EP02368053 2002-05-23
PCT/EP2003/012647 WO2004017687A1 (en) 2002-05-23 2003-04-18 Improved structure of stacked vias in multiple layer electronic device carriers

Publications (2)

Publication Number Publication Date
DE60314868D1 true DE60314868D1 (de) 2007-08-23
DE60314868T2 DE60314868T2 (de) 2008-03-13

Family

ID=31725517

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314868T Expired - Lifetime DE60314868T2 (de) 2002-05-23 2003-04-18 Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern

Country Status (10)

Country Link
US (1) US7319197B2 (de)
EP (1) EP1506701B1 (de)
JP (1) JP4056525B2 (de)
KR (1) KR100702554B1 (de)
CN (1) CN100370887C (de)
AT (1) ATE367077T1 (de)
AU (1) AU2003276277A1 (de)
DE (1) DE60314868T2 (de)
MX (1) MXPA04011463A (de)
WO (1) WO2004017687A1 (de)

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US7652896B2 (en) * 2004-12-29 2010-01-26 Hewlett-Packard Development Company, L.P. Component for impedance matching
US20080067665A1 (en) * 2006-09-20 2008-03-20 Azniza Binti Abd Aziz Via structure
US7649265B2 (en) * 2006-09-29 2010-01-19 Intel Corporation Micro-via structure design for high performance integrated circuits
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
US8242593B2 (en) * 2008-01-27 2012-08-14 International Business Machines Corporation Clustered stacked vias for reliable electronic substrates
CN101562951B (zh) * 2008-04-18 2011-05-11 欣兴电子股份有限公司 线路板及其制作方法
JP5397007B2 (ja) * 2009-05-14 2014-01-22 富士通株式会社 プリント配線板および電子部品パッケージ
US8735734B2 (en) * 2009-07-23 2014-05-27 Lexmark International, Inc. Z-directed delay line components for printed circuit boards
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
KR101161971B1 (ko) * 2010-07-21 2012-07-04 삼성전기주식회사 다층 회로 기판 및 다층 회로 기판의 제조 방법
KR101696644B1 (ko) * 2010-09-15 2017-01-16 삼성전자주식회사 3차원 수직 배선을 이용한 ｒｆ 적층 모듈 및 이의 배치 방법
US9078374B2 (en) 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
US8943684B2 (en) * 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
US8790520B2 (en) 2011-08-31 2014-07-29 Lexmark International, Inc. Die press process for manufacturing a Z-directed component for a printed circuit board
US8752280B2 (en) 2011-09-30 2014-06-17 Lexmark International, Inc. Extrusion process for manufacturing a Z-directed component for a printed circuit board
US8658245B2 (en) 2011-08-31 2014-02-25 Lexmark International, Inc. Spin coat process for manufacturing a Z-directed component for a printed circuit board
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
JP5765633B2 (ja) * 2011-12-22 2015-08-19 株式会社フジクラ プリント配線板及びその製造方法
TWI449475B (zh) * 2012-01-09 2014-08-11 Novatek Microelectronics Corp 電路板
US8822838B2 (en) 2012-03-29 2014-09-02 Lexmark International, Inc. Z-directed printed circuit board components having conductive channels for reducing radiated emissions
US8822840B2 (en) 2012-03-29 2014-09-02 Lexmark International, Inc. Z-directed printed circuit board components having conductive channels for controlling transmission line impedance
US8830692B2 (en) 2012-03-29 2014-09-09 Lexmark International, Inc. Ball grid array systems for surface mounting an integrated circuit using a Z-directed printed circuit board component
US8912452B2 (en) 2012-03-29 2014-12-16 Lexmark International, Inc. Z-directed printed circuit board components having different dielectric regions
TW201431450A (zh) * 2013-01-29 2014-08-01 Hon Hai Prec Ind Co Ltd 印刷電路板
CN103974519B (zh) * 2013-01-29 2017-02-08 江苏传艺科技股份有限公司 印刷电路板
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9871017B2 (en) * 2016-01-04 2018-01-16 Infineon Technologies Ag Multi-level chip interconnect
JP6674016B2 (ja) * 2016-03-24 2020-04-01 京セラ株式会社 印刷配線板およびその製造方法
JP6730960B2 (ja) * 2017-05-24 2020-07-29 日本特殊陶業株式会社 配線基板
US10916519B2 (en) 2018-06-08 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing semiconductor package with connection structures including via groups
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
JP6869209B2 (ja) * 2018-07-20 2021-05-12 日本特殊陶業株式会社 配線基板
US10727190B2 (en) * 2018-12-27 2020-07-28 Tektronix, Inc. Compound via RF transition structure in a multilayer high-density interconnect
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11776899B2 (en) * 2020-05-11 2023-10-03 Mediatek Inc. Via array design for multi-layer redistribution circuit structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US20240074053A1 (en) * 2022-08-25 2024-02-29 Nvidia Corporation Clustered microvia structure for a high-density interface pcb
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Also Published As

Publication number Publication date
JP4056525B2 (ja) 2008-03-05
KR20050009998A (ko) 2005-01-26
EP1506701B1 (de) 2007-07-11
MXPA04011463A (es) 2005-07-01
KR100702554B1 (ko) 2007-04-04
DE60314868T2 (de) 2008-03-13
ATE367077T1 (de) 2007-08-15
AU2003276277A1 (en) 2004-03-03
CN100370887C (zh) 2008-02-20
WO2004017687A1 (en) 2004-02-26
EP1506701A1 (de) 2005-02-16
US20050156319A1 (en) 2005-07-21
CN1656861A (zh) 2005-08-17
JP2005527122A (ja) 2005-09-08
US7319197B2 (en) 2008-01-15

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