KR980006256A - 감결합 캐패시터가 삽입된 인쇄 회로 기판 및 감결합 캐패시터 생성 방법 - Google Patents

감결합 캐패시터가 삽입된 인쇄 회로 기판 및 감결합 캐패시터 생성 방법 Download PDF

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KR980006256A
KR980006256A KR1019970014421A KR19970014421A KR980006256A KR 980006256 A KR980006256 A KR 980006256A KR 1019970014421 A KR1019970014421 A KR 1019970014421A KR 19970014421 A KR19970014421 A KR 19970014421A KR 980006256 A KR980006256 A KR 980006256A
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conductive foil
dielectric material
coated
electronic circuit
circuit package
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존 엠 라우퍼
콘스탄티노스 파파토마스
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제프리 엘. 포맨
인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/43—Electric condenser making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/43—Electric condenser making
    • Y10T29/435—Solid dielectric type

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  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

전자 회로 패키지 내에 삽입될 캐패시터를 생성하기 위한 방법이 제공되는데, 이 방법은 제1도전체 호일을 선택하고, 유전 물질을 선택하며, 상기 제1도전체 호일의 적어도 한 측면 상에 상기 유전 물질을 코팅하고, 제2도전체 호일로, 코팅된 호일을 유전 물질의 코팅막 상부에 적층하는 단계들을 포함한다. 또한, 본 발명에 따라 제조된 적어도 1개의 삽입형 캐패시터를 포함하는 전자회로 패키지가 제공된다.

Description

감결합 캐패시터가 삽입된 인쇄 회로 기판 및 감결합 캐패시터 생성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 다층 인쇄 회로 기판의 단층(single layer)을 도외시하는 도면.

Claims (23)

  1. 전자회로 패키지 내에 삽입된 캐패시터를 생성하는 방법에 있어서, 제1도전체 호일(a first conductor foil)을 선택하는 단계; 상기 제1도전체 호일 내에 클리어런스 홀(clearance holes)을 한정하는 단계; 유전 물질을 선택하는 단계; 상기 제1도전체 호일의 적어도 한 측면 상에 상기 유전 물질을 코팅하는 단계; 및 클리어런스 홀을 갖는 제2도전체 호일로 코팅된 호일을 상기 유전 물질의 코팅막(coating)상부에 적측하는 단계를 포함하는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  2. 제1항에 있어서, 상기 제1 및 제2도전체 호일들은 구리 재료로 만들어지는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  3. 제1항에 있어서, 상기 제1도전체 호일 상에 상기 유전 물질을 코팅하는 단계는 롤러, 드로우(draw), 파우더(powder), 또는 커튼 코팅(curtain coating), 정전기 또는 전기 이동 피착(electrostatic or electrophoretic deposition),스크린 프린팅, 스프레잉(spraying) 딥핑(dipping) 또는 건식 필름의 전사(transfer)에 의해 상기 유전 물질을 도포하는 단계를 더 포함하는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  4. 제1항에 있어서, 상기 제1도전체 호일 상에 코팅된 상기 유전 물질층은 두께가 0.0001 - 0.0003인 전자회로 패키지 내에 삽입된 캐패시터 생성방법
  5. 제1항에 있어서, 상기 제1도전체 호일의 양측면은 상기 유전 물질로 코팅되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  6. 제1항에 있어서, 상기 제2도전체 호일의 적어도 한 측면은 상기 유전물질로 코팅되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  7. 제1항에 있어서, 상기 제1 및 제2도전체 호일들 내의 클리어런스 홀들은 드릴링에 의해 정의되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  8. 제1항에 있어서, 상기 제1 및 제2도전체 호일들 내의 클리어런스 홀들은 애칭에 의해 정의되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  9. 제1항에 있어서, 상기 제1 및 제2도전체 호일들 내의 클리어런스 홀들은 펀칭되는(punched) 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  10. 전자 회로 패키지에 있어서, 적층(lamination) 및 회로화(circuitization)에 의해 각각 제조된 제1 코어 및 제2 코어 ; 및 상기 제 1코어와 상기 제2 코어 사이에 끼워진 1개 이상의 삽입형 캐패시터를 포함하고, 상기 삽입형 캐패시터 각각은 적어도 한 측면의 유전 물질로 코팅된 제1도전체 호일; 및 상기 제1도전체 호일 상의 상기 유전 물질의 코팅막 상부에 있는 제2도전체 호일을 포함하는 전자 회로 패키지
  11. 제10항에 잇어서, 상기 제2도전체 호일의 적어도 한 측면은 상기 유전 물질로 코팅되는 전자 회로 패키지
  12. 제10항에 있어서, 상기 제1도전체 호일의 양측면은 상기 유전 물질로 코팅되는 전자 회로 패키지
  13. 전자회로 패키지 내에 삽입된 캐패시터를 생성하는 방법에 있어서, 제1도전체 호일을 선택하는 단계; 상기 제1도전체 호일 내에 클리어런스 홀을 정의하는 단계; 미립자 및 다기능 에폭시 매트릭스(particulate and multifunctional epoxy matrix)로 이루어진 유전 물질을 선택하는 단계; 상기 제1도전체 호일의 제1전압측 상에 그리고 제2도전체 호일의 제2정압측 상에 상기 유전 물질을 롤러 코팅(roller coating)하는 단계; 처리된(treated) 제3도저체 호일을 그라운드 프레인 클리어런스 홀 패턴으로 드릴링하는 단계; 미리 제조된 다른 코어가 있는 스택(stack with other pre-fabricated cores) 내에 상기 코팅된 제1도전체 호일 및 상기 코팅된 제2도전체 호일을 상기 들릴된 제3도전체 호일과 함께 쌓는 단계; 및 상기 스택을 적층시키는 단계를 포함하는 전자회로 패키지 내에 삽입된 캐패시터 생성방법
  14. 제13항에 있어서, 상기 제1도전체 호일 및 상기 제2도전체 호일을 구리로 만들어지는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  15. 제13항에 있어서, 상기 유전 물질은 약 0.00015두께로 도포되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  16. 제13항에 있어서, 상기 코팅된 제1도전체 호일 및 상기 코팅된 제2도 전체 호일은 코팅된 다음 그리고 상기 스택 내에 적층되기 전에 약 140℃로 오븐 내에서 약 5분동안 건조되는 전자 회로 패키지 내에 삽입된 캐패시터 생성방법
  17. 제13항에 있어서, 상기 드릴된 제3도전체 호일은 구리로 만들어지는 전자회로 캐피지 내에 삽입된 캐패시터 생성방법
  18. 제13항에 있어서, 상기 유전 물질은 테플론(Teflon), 시안네이트 에스테르(cyanate ester), BT-에폭시 및 폴리이미드를 포함하는 그룹으로부터 선택되는 전자회로 패키지 내에 삽입된 캐패시터 생성방법
  19. 인쇄회로 기판에 있어서, 적층 및 회로화에 의해 각각 제조된 제1코어 및 제2코어; 제1도전체 호일; 제2도전체 호일; 상기 제1도전체 호일 및 상기 제2도전체 호일 각각의 적어도 한 측면 상에 코팅된 유전 물질; 및 그라운드 플레인 클리어런스 홀 패턴으로 드릴된 제3도전체 호일을 포함하는 인쇄회로 기판
  20. 제19항에 있어서, 상기 제1도전체 호일 및 상기 제2도전체 호일은 구리로 만들어지는 인쇄회로기판
  21. 제19항에 있어서, 상기 유전 물질은 약 0.0015두께로 도포되는 인쇄회로기판
  22. 제19항에 있어서, 상기 들릴된 제3도전체 호일은 구리로 만들어지는 인쇄회로기판
  23. 제19항에 있어서, 상기 유전 물질은 테플론, 시안네이트 에스테르, BT-에포시 및 폴리이미드를 포함하는 그룹으로부터 선택되는 인쇄회로기판
KR1019970014421A 1996-06-12 1997-04-18 감결합 캐패시터가 삽입된 인쇄 회로 기판 및 감결합 캐패시터 제조방법 KR100247717B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8/662,164 1996-06-12
US08/662,164 US5796587A (en) 1996-06-12 1996-06-12 Printed circut board with embedded decoupling capacitance and method for producing same
US08/662,164 1996-06-12

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KR980006256A true KR980006256A (ko) 1998-03-30
KR100247717B1 KR100247717B1 (ko) 2000-03-15

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US (2) US5796587A (ko)
EP (1) EP0813355B1 (ko)
JP (1) JP3400677B2 (ko)
KR (1) KR100247717B1 (ko)
CN (1) CN1105484C (ko)
DE (1) DE69715523T2 (ko)
MY (1) MY117854A (ko)
TW (1) TW330370B (ko)

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US6343001B1 (en) 1996-06-12 2002-01-29 International Business Machines Corporation Multilayer capacitance structure and circuit board containing the same
US20040109298A1 (en) * 1998-05-04 2004-06-10 Hartman William F. Dielectric material including particulate filler
US6616794B2 (en) * 1998-05-04 2003-09-09 Tpl, Inc. Integral capacitance for printed circuit board using dielectric nanopowders
US6608760B2 (en) * 1998-05-04 2003-08-19 Tpl, Inc. Dielectric material including particulate filler
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EP0813355A2 (en) 1997-12-17
DE69715523T2 (de) 2003-05-28
DE69715523D1 (de) 2002-10-24
KR100247717B1 (ko) 2000-03-15
US5796587A (en) 1998-08-18
US6256850B1 (en) 2001-07-10
EP0813355B1 (en) 2002-09-18
MY117854A (en) 2004-08-30
CN1173803A (zh) 1998-02-18
TW330370B (en) 1998-04-21
JPH1056249A (ja) 1998-02-24
JP3400677B2 (ja) 2003-04-28
CN1105484C (zh) 2003-04-09
EP0813355A3 (en) 1999-04-14

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