EP0813355B1 - Printed circuit board with embedded decoupling capacitance and method for producing same - Google Patents
Printed circuit board with embedded decoupling capacitance and method for producing same Download PDFInfo
- Publication number
- EP0813355B1 EP0813355B1 EP97304050A EP97304050A EP0813355B1 EP 0813355 B1 EP0813355 B1 EP 0813355B1 EP 97304050 A EP97304050 A EP 97304050A EP 97304050 A EP97304050 A EP 97304050A EP 0813355 B1 EP0813355 B1 EP 0813355B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductor foil
- dielectric material
- coated
- foil
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000011888 foil Substances 0.000 claims description 48
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 39
- 239000004020 conductor Substances 0.000 claims description 38
- 239000003989 dielectric material Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000003475 lamination Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 4
- 239000000843 powder Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920006362 Teflon® Polymers 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 239000004809 Teflon Substances 0.000 claims description 2
- 238000007766 curtain coating Methods 0.000 claims description 2
- 238000007598 dipping method Methods 0.000 claims description 2
- 238000001652 electrophoretic deposition Methods 0.000 claims description 2
- 238000004924 electrostatic deposition Methods 0.000 claims description 2
- 238000007761 roller coating Methods 0.000 claims description 2
- 238000007650 screen-printing Methods 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 238000012546 transfer Methods 0.000 claims description 2
- 229920002844 BT-Epoxy Polymers 0.000 claims 1
- 239000004643 cyanate ester Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 28
- 239000011889 copper foil Substances 0.000 description 17
- 239000010408 film Substances 0.000 description 9
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 229920002799 BoPET Polymers 0.000 description 2
- 229910001374 Invar Inorganic materials 0.000 description 2
- 239000005041 Mylar™ Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 150000001913 cyanates Chemical class 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
- Y10T29/435—Solid dielectric type
Definitions
- the present invention relates to a printed circuit board with embedded decoupling capacitance and method for producing same.
- Electronic circuits contain many (sometimes millions) of components such as resistors,capacitors, inductors, diodes, electro-mechanical switches, and transistors.
- High density packaging of electronic components is particularly important to allow fast access to large amounts of data in computers.
- High density electronic circuit packages also are important in high frequency devices and communications devices.
- the components are connected to form circuits and circuits are connected to form functioning devices.
- the connections perform power and signal distribution.
- some layers of the package serve as power planes and other layers serve as signal planes, depending on the operational requirements of the device.
- the devices require mechanical support and structural protection.
- the circuits themselves require electrical energy to function.
- the functioning devices produce heat, or thermal energy which must be dissipated so that the devices do not stop functioning.
- the heat produced by the power-consuming components can be such that performance and reliability of the devices is adversely impacted.
- the adverse impact arises from electrical problems such as increased resistivity and mechanical problems such as thermal stress caused by increased heat.
- High density packages necessarily involve increased wiring density and thinner dielectric coatings between layers in a multi-layer electronic circuit package.
- the layers in a multi-layer package are electrically connected by vias and through-holes.
- the term "via” is used for a conductive pathway between adjacent layers in a multi-layer electronic circuit package.
- the term "through-hole” is used for a conductive pathway that extends to a non-adjacent layer.
- the through-holes are increasingly narrow in diameter and the through-holes in each layer must be aligned precisely.
- Electronic circuit packages such as chips, modules, circuit cards, circuit boards, and combinations of these, thus must meet a number of requirements for optimum performance.
- the package must be structurally sturdy enough to support and protect the components and the wiring.
- the package must be capable of dissipating heat and must have a coefficient of thermal expansion that is compatible with that of the components.
- the package should be inexpensive to produce and easy to manufacture.
- a signal changes from one binary level to another. This change is ideally transmitted as a "step function.”
- this ideal step function becomes distorted because of resistance, capacitance, inductance, and transmission line effects in the transmission line and in other transmission lines in the package.
- this step function whether ideal or distorted, gives rise to still other distortions and spurious signals, i.e., noise, and induced signals on other lines in the circuit package. Thus, it is necessary to filter noise out of digital circuits.
- Filtering may be accomplished in digital circuit packages by providing internal RC filter circuits of appropriate RC time constant and band pass characteristics, and thereby capacitively coupling, or decoupling, signal lines with, for example, power lines, ground lines, or other signal lines.
- an integral buried capacitor comprising a first electrode connected by a wire to a first signal core and a second electrode connected by a wire to a second signal core.
- the second electrode at least partially overlaps the first electrode but is separated from it by a thin film of dielectric material.
- the two electrodes and the thin film of dielectric material define the integral buried capacitor.
- Lucas a method for forming a capacitor element internally within a printed circuit board. Lucas discloses arranging uncured dielectric sheets with conductive foils laminated to either side and incorporated as a layer in a printed circuit board.
- the method of Lucas requires that clearance holes in the conductive foils be defined by etching through a patterned photoresist material on each foil individually.
- the present invention allows a multitude of foils to be stacked together and drilled or punched simultaneously, hence creating a lower cost package. Additionally, the Lucas method is subject to reliability problems of plane to plane shorting due to dendritic copper plating along the glass fibers of the thin dielectric material.
- the non-glass dielectric of the present invention does not contain any defined dendritic copper paths.
- a method for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
- the present invention facilitates provision of a printed circuit board with decoupled ground and power busses to provide proper switching stimulus.
- the invention also facilitates provision of printed circuit boards with very high decoupling capacitance values.
- the invention provides methods of fabrication of printed circuit boards with integrated decoupling capacitance.
- the invention relates to printed circuit boards having very high integrated decoupling capacitances which are created by multi-layering pre-drilled or pre-etched conductor foils that have been coated with a dielectric material.
- the pre-drilled or pre-etched conductor foils are in the form of either voltage or ground planes. After coating with a dielectric material, the foils are stacked up such that voltage and ground planes alternate. The alternating stack then is laminated together with other signal planes to form the desired multi-layer circuit board.
- the capacitor provided is embedded into the electronic circuit package, reducing or eliminating the need for surface-mount capacitors.
- the embedded capacitors decouple the ground and power busses to provide proper switching stimulus.
- Figure 1 is a depiction of a single layer of a multi-layer printed circuit board of the present invention.
- Figure 2 is a depiction of a second alternative embodiment of a single layer of a multi-layer printed circuit board of the present invention.
- the present invention is of a printed circuit board with embedded decoupling capacitance and a method for producing same.
- printed circuit boards having very high integrated decoupling capacitances are created by the multi-layering within the printed circuit board of pre-drilled or pre-etched conductor foils that have been coated with a dielectric material.
- the pre-drilled or pre-etched conductor foils are in the form of voltage or ground planes. After coating with a dielectric material, they are stacked up in alternate fashion (i.e. voltage/ground/voltage) and laminated together with other signal planes to create the final multi-layer circuit board.
- the conductor foil is of a copper material.
- suitable conductor foils include, but are not limited to, copper-Invar-copper, Invar, aluminum, and copper pre-laminated to a dielectric.
- the dielectric coating may be any type of dielectric material from standard liquid epoxy, polyimide, Teflon, cyanate resins, powdered resin materials, or filled resin systems exhibiting enhanced dielectric constants.
- Coating of the dielectric material onto the conductor foil is performed with any number of methods known in the industry such as roller, draw, powder or curtain coating, electrostatic or electrophoretic deposition, screen printing, spraying, dipping or transfer of a dry film. Any of these coating methods is capable of providing uniformly thin (0.0001" - 0.003") (2,54 - 76 ⁇ m) films. Once multi-layer laminated, the thickness of these coated films is not limited by a glass cloth material.
- an Advanced Solder Mask (ASM) dry film material was used to form a composite multi-layer printed circuit board with an integral capacitive stack-up in accordance with the present invention.
- ASM Advanced Solder Mask
- Conventional signal-signal and signal-voltage cores were fabricated through means of lamination and circuitization. These circuitized cores were subjected to a copper oxide process to enhance composite lamination adhesion.
- copper foil/dielectric structures in accordance with the present invention were pre-fabricated as follows:
- Figure 1 shows the printed circuit board constructed as described in Example 1.
- the three copper sheets that were drilled are labeled, 10, 12, and 14, respectively. Copper sheets 10 and 14 were drilled in a ground plane clearance hole pattern. Copper sheet 12 was drilled in a voltage plane clearance hole pattern.
- a sheet of ASM dry film 16 was then laminated to the top surface of copper sheet 10.
- ASM dry film sheets 18 and 20 were laminated on the top and bottom surfaces, respectively, of copper sheet 12.
- ASM dry film sheet 22 was laminated to the bottom surface of copper sheet 14.
- Circuitized core 24 has a signal plane 28 on the top surface and an etched copper foil sheet 30 on the bottom surface.
- the copper foil sheet 30 is etched in a voltage pattern.
- Two layers of epoxy glass 36 and 38, and a copper foil sheet 40 and 42 enclose the top and bottom outer surfaces of the entire printed circuit board.
- each capacitive plane has a dielectric material in between two conductive metal (copper) sheets.
- the resultant structure has two capacitance planes in parallel.
- the resultant structure has a thickness of (0.001") 25 ⁇ m, dielectric constant of 40, and a capacitance value of 18 nano-Farads per square inch of board area.
- Figure 2 shows the printed circuit board constructed as described in Example 2.
- the two cores are numbered 52 and 54.
- Core 52 has signal plane 56 on the top surface and etched copper voltage plane 58 on the bottom surface.
- Core 54 has etched copper voltage plane 60 on the top, and signal plane 62 on the bottom. Both etched copper voltage planes 58 and 60 are coated with dielectric material to form layers 64 and 66, respectively.
- the dielectric material as described above, is a filled resin system of BaTiO3 powder, a multifunctional epoxy resin, and MEK solvent. The dielectric material was applied by roller coating. In between the dielectric material layers 64 and 66 is a double treated copper foil sheet 68 drilled in a ground plane clearance hole pattern.
- the outer surfaces of the printed circuit board are formed by two layers of epoxy glass 70, 72 and a copper foil sheet 74 and 76.
- the printed circuit board in Figure 2 has two capacitive planes 78, 80 in parallel with each other.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US662164 | 1996-06-12 | ||
US08/662,164 US5796587A (en) | 1996-06-12 | 1996-06-12 | Printed circut board with embedded decoupling capacitance and method for producing same |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0813355A2 EP0813355A2 (en) | 1997-12-17 |
EP0813355A3 EP0813355A3 (en) | 1999-04-14 |
EP0813355B1 true EP0813355B1 (en) | 2002-09-18 |
Family
ID=24656638
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97304050A Expired - Lifetime EP0813355B1 (en) | 1996-06-12 | 1997-06-11 | Printed circuit board with embedded decoupling capacitance and method for producing same |
Country Status (8)
Country | Link |
---|---|
US (2) | US5796587A (ko) |
EP (1) | EP0813355B1 (ko) |
JP (1) | JP3400677B2 (ko) |
KR (1) | KR100247717B1 (ko) |
CN (1) | CN1105484C (ko) |
DE (1) | DE69715523T2 (ko) |
MY (1) | MY117854A (ko) |
TW (1) | TW330370B (ko) |
Families Citing this family (72)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2734447B2 (ja) * | 1995-09-14 | 1998-03-30 | 日本電気株式会社 | 多層プリント基板 |
US6343001B1 (en) | 1996-06-12 | 2002-01-29 | International Business Machines Corporation | Multilayer capacitance structure and circuit board containing the same |
US20040109298A1 (en) * | 1998-05-04 | 2004-06-10 | Hartman William F. | Dielectric material including particulate filler |
US6616794B2 (en) * | 1998-05-04 | 2003-09-09 | Tpl, Inc. | Integral capacitance for printed circuit board using dielectric nanopowders |
US6608760B2 (en) * | 1998-05-04 | 2003-08-19 | Tpl, Inc. | Dielectric material including particulate filler |
JP3201345B2 (ja) * | 1998-05-13 | 2001-08-20 | 日本電気株式会社 | 多層プリント配線板 |
US6137192A (en) | 1998-05-15 | 2000-10-24 | Energenius, Inc. | Embedded backup energy storage unit |
SE513875C2 (sv) | 1998-06-15 | 2000-11-20 | Ericsson Telefon Ab L M | Elektrisk komponent samt ett flerlagrigt kretskort |
US6326677B1 (en) | 1998-09-04 | 2001-12-04 | Cts Corporation | Ball grid array resistor network |
SE513341C2 (sv) | 1998-10-06 | 2000-08-28 | Ericsson Telefon Ab L M | Arrangemang med tryckta kretskort samt metod för tillverkning därav |
US6215649B1 (en) * | 1998-11-05 | 2001-04-10 | International Business Machines Corporation | Printed circuit board capacitor structure and method |
US6574090B2 (en) | 1998-11-05 | 2003-06-03 | International Business Machines Corporatiion | Printed circuit board capacitor structure and method |
US6005777A (en) * | 1998-11-10 | 1999-12-21 | Cts Corporation | Ball grid array capacitor |
US6214445B1 (en) * | 1998-12-25 | 2001-04-10 | Ngk Spark Plug Co., Ltd. | Printed wiring board, core substrate, and method for fabricating the core substrate |
KR100431307B1 (ko) * | 1998-12-29 | 2004-09-18 | 주식회사 하이닉스반도체 | 캐패시터 내장형 칩 사이즈 패키지 및 그의 제조방법 |
US6274224B1 (en) | 1999-02-01 | 2001-08-14 | 3M Innovative Properties Company | Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article |
US6542379B1 (en) * | 1999-07-15 | 2003-04-01 | International Business Machines Corporation | Circuitry with integrated passive components and method for producing |
US6407720B1 (en) * | 1999-07-19 | 2002-06-18 | The United States Of America As Represented By The Secretary Of The Navy | Capacitively loaded quadrifilar helix antenna |
CN101232775B (zh) | 1999-09-02 | 2010-06-09 | 伊比登株式会社 | 印刷布线板及其制造方法 |
US6724638B1 (en) | 1999-09-02 | 2004-04-20 | Ibiden Co., Ltd. | Printed wiring board and method of producing the same |
JP3608990B2 (ja) * | 1999-10-19 | 2005-01-12 | 新光電気工業株式会社 | 多層回路基板およびその製造方法 |
US6441313B1 (en) | 1999-11-23 | 2002-08-27 | Sun Microsystems, Inc. | Printed circuit board employing lossy power distribution network to reduce power plane resonances |
US6367678B1 (en) * | 2000-04-18 | 2002-04-09 | Ballado Investments Inc. | Process for stacking layers that form a multilayer printed circuit |
US6970362B1 (en) | 2000-07-31 | 2005-11-29 | Intel Corporation | Electronic assemblies and systems comprising interposer with embedded capacitors |
US6611419B1 (en) | 2000-07-31 | 2003-08-26 | Intel Corporation | Electronic assembly comprising substrate with embedded capacitors |
US6657849B1 (en) | 2000-08-24 | 2003-12-02 | Oak-Mitsui, Inc. | Formation of an embedded capacitor plane using a thin dielectric |
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-
1996
- 1996-06-12 US US08/662,164 patent/US5796587A/en not_active Expired - Lifetime
- 1996-11-09 TW TW085113696A patent/TW330370B/zh active
-
1997
- 1997-04-18 KR KR1019970014421A patent/KR100247717B1/ko not_active IP Right Cessation
- 1997-05-20 MY MYPI97002207A patent/MY117854A/en unknown
- 1997-05-22 CN CN97113438A patent/CN1105484C/zh not_active Expired - Lifetime
- 1997-06-05 JP JP14758197A patent/JP3400677B2/ja not_active Expired - Lifetime
- 1997-06-11 EP EP97304050A patent/EP0813355B1/en not_active Expired - Lifetime
- 1997-06-11 DE DE69715523T patent/DE69715523T2/de not_active Expired - Fee Related
-
1998
- 1998-02-11 US US09/022,258 patent/US6256850B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0813355A2 (en) | 1997-12-17 |
DE69715523T2 (de) | 2003-05-28 |
DE69715523D1 (de) | 2002-10-24 |
KR100247717B1 (ko) | 2000-03-15 |
US5796587A (en) | 1998-08-18 |
US6256850B1 (en) | 2001-07-10 |
MY117854A (en) | 2004-08-30 |
CN1173803A (zh) | 1998-02-18 |
TW330370B (en) | 1998-04-21 |
JPH1056249A (ja) | 1998-02-24 |
KR980006256A (ko) | 1998-03-30 |
JP3400677B2 (ja) | 2003-04-28 |
CN1105484C (zh) | 2003-04-09 |
EP0813355A3 (en) | 1999-04-14 |
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