KR970008324A - 중간층 리쏘그래피 - Google Patents

중간층 리쏘그래피 Download PDF

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KR970008324A
KR970008324A KR1019960028361A KR19960028361A KR970008324A KR 970008324 A KR970008324 A KR 970008324A KR 1019960028361 A KR1019960028361 A KR 1019960028361A KR 19960028361 A KR19960028361 A KR 19960028361A KR 970008324 A KR970008324 A KR 970008324A
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layer
patterned
barc
photoresist
forming
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KR1019960028361A
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KR100420910B1 (ko
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리차드 알렉산더 차프만
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윌리엄 이.힐러
텍사스 인스트루먼츠 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Optics & Photonics (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Weting (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

등방성 또는 부분적 등방성 에치는 에치스톱 또는 희생적인 층으로서 또한 작용하는 매립 무반사 코팅을 가지고 라인 폭이 줄어든 패턴된 포토레지스트 (213,214)를 생성하기 위해서 리쏘그래픽 패턴된 포토레지스트(211,212)를 축소시킨다. 축소된 라인 폭 패턴(213,214)은 폴리실리콘(206) 또는 금속 또는 절연체 또는 강유 전체와 같은 아래에 있는 물질의 후속적인 이방성 에칭을 위한 에치 마스크를 제공한다.

Description

중간층 리쏘그래피
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2h도는 포토레지스트 패터닝의 제1양호한 실시 방법을 나타내는 정면단면 및 평면도.

Claims (8)

  1. 리쏘그래피 방법에 있어서, (a) 패턴될 하부층을 제공하는 단계; (b) 상기 하부층 위에 중간층을 형성하는 단계; (c) 상기 중간층 위에 방사선 감지 상부층을 형성하는 단계; (d) 패턴된 상부층을 형성하기 위해 방사선으로 상기 상부층을 패터닝하는 단계; (e) 상기 패턴된 상부층 아래에 제1패턴된 중간층을 형성하기 위해 상기 중간층의 노출된 부분들을 제거하는 단계, (f) 제2패턴된 중간층을 형성하기 위해 상기 패턴된 상부층 아래의 상기 제1의 패턴된 중간층의 부분들을 제거하는 단계, (g) 적어도 마스크의 일부분으로 상기 제2패턴된 중간층을 사용하여 상기 하부층의 일부를 제거하는 단계를 포함하는 것을 특징으로 하는 리쏘그래피 방법.
  2. 제1항에 있어서, (a) 상기 중간층은 TiN으로 만들어지고, (b) 상기 상부층은 포토레지스트로 만들어지는 것을 특징으로 하는 리쏘그래피 방법.
  3. 제2항에 있어서, (a)상기 제1패턴된 중간층의 부분들을 제거하는 상기 단계는 플라즈마 에칭에 의해 이루어지는 것을 특징으로 하는 리쏘그래피 방법.
  4. 제3항에 있어서, (a)상기 하부층은 폴리실리콘이고, (b)상기 하부층의 부분들을 제거하는 상기 단계는 이방성 플라스마 에칭에 의해 이루어지는 것을 특징으로 하는 리쏘그래피 방법.
  5. 서브리쏘그래팩 패터닝 방법에 있어서, (a) 패턴될 하부층을 제공하는 단계, (b) 상기 제1파장의 방사선을 흡수하는 층인 매립 무반사 코팅(BARC)층을 형성하는 단계, (c) 상기 제1파장을 갖는 방사선에 의해 노출될 수 있는 포토레지스트층을 상기 BARC층 위에 형성하는 단계, (d) W의 최소 라인 폭을 갖는 포토레지스트의 패턴된 층을 형성하기 위해 상기 제1파장을 포함하는 방사선으로 상기 포토레지스트층을 패터닝하는 단계, (e) W의 최소라인 폭을 갖는 제1패턴된 BARC층을 형성하기 위해 포토레지스트의 상기 패턴된 층을 사용하여 상기 BARC층을 이방성 에칭하는 단계, (f) 상기 하부층 상에 W-2△W의 최소 라인 폭을 갖는 제2패턴된 BARC층을 형성하기 위해 상기 하부층의 표면을 따르는 방향으로 상기 제1패턴된 BARC층의 모든 노출된 표면으로부터 라인 폭 양△W를 제거하도록 상기 제1패턴된 BARC층을 등방성 에칭하는 단계, 및 (g) 에치마스크로서 상기 제2패턴된 BARC층을 사용하여 상기 하부층을 이방성 에칭하는 단계를 포함하는 것을 특징으로 하는 서브리쏘그래피 패터닝 방법.
  6. (a) 상기 BARC층은 TiN으로 이루어진 것을 특징으로 하는 서브리쏘그래피 패터닝 방법.
  7. 리쏘그래방법에 있어서, (a)패턴될 하부층을 제공하는 단계, (b) 제1파장의 방사선을 흡수하는 층인 매립 무반사 코팅(BARC)층을 상기 매립 무반사 코팅(BARC)층을 상기 하부층 위에 형성하는 단계, (c) 상기 제1파장을 갖는 방사선으로 누출될 수 있는 포토레지스트층을 상기 BARC층 위에 형성하는 단계, (d) W의 최소 라인 폭을 갖는 포토레지스트의 패턴된 층을 형성하기 위해 상기 제1파장을 포함하는 방사선으로 상기 포토레지스트층을 패터닝하는 단계, (e) 포토레지스트의 상기 패턴된 층 아래에 W의 최소 라인 폭을 갖는 패턴된 BARC층을 형성하기 위해 포토레지스트의 상기 패턴된 층을 사용하여 상기 BARC층을 이방성 에칭하는 단계, (f) 에치 마스크로서 상기 패턴된 BARC층 및 포토레지스트의 패턴된 층을 사용하여 상기 하부층을 이방성 에칭하는 단계, (g) 포토레지스트의 상기 패턴된 층을 벗겨내는 단계, 및 (h) 상기 패턴된 BARC층을 제거하는 단계를 포함하며, 상기 벗겨서 남은 잉여물이 상기 패턴된 BARC층을 제거하는 상기 단계로 리프트 오프되는 것을 특징으로 하는 리쏘그래피 방법.
  8. 제5항에 있어서, (a) 상기 BARC층은 TiN으로 이루어지는 것을 특징으로 하는 리쏘그래피 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960028361A 1995-07-14 1996-07-13 중간층리소그래피 KR100420910B1 (ko)

Applications Claiming Priority (2)

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US116695P 1995-07-14 1995-07-14
US60/001,166 1995-07-14

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KR970008324A true KR970008324A (ko) 1997-02-24
KR100420910B1 KR100420910B1 (ko) 2004-05-17

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US (1) US5976769A (ko)
EP (1) EP0753764B1 (ko)
JP (1) JPH09251988A (ko)
KR (1) KR100420910B1 (ko)
DE (1) DE69624413T2 (ko)
TW (1) TW332893B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101295889B1 (ko) * 2009-12-01 2013-08-12 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5965461A (en) * 1997-08-01 1999-10-12 Advanced Micro Devices, Inc. Controlled linewidth reduction during gate pattern formation using a spin-on barc
JP3165093B2 (ja) * 1997-11-13 2001-05-14 松下電子工業株式会社 半導体装置およびその製造方法
US6287975B1 (en) * 1998-01-20 2001-09-11 Tegal Corporation Method for using a hard mask for critical dimension growth containment
US6221776B1 (en) * 1998-05-05 2001-04-24 Cypress Semiconductor Corp. Anti-reflective coating used as a disposable etch stop
JP2000012687A (ja) * 1998-06-23 2000-01-14 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6209193B1 (en) * 1998-08-24 2001-04-03 International Business Machines Corporation Method of making read sensor with self-aligned low resistance leads
US6162587A (en) * 1998-12-01 2000-12-19 Advanced Micro Devices Thin resist with transition metal hard mask for via etch application
US6362111B1 (en) * 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
JP2000208488A (ja) * 1999-01-12 2000-07-28 Kawasaki Steel Corp エッチング方法
JP2001015479A (ja) * 1999-06-29 2001-01-19 Toshiba Corp 半導体装置の製造方法
US6130155A (en) * 1999-07-02 2000-10-10 Promos Technologies, Inc. Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating
DE19937995C2 (de) * 1999-08-11 2003-07-03 Infineon Technologies Ag Verfahren zur Strukturierung einer organischen Antireflexionsschicht
US6722376B2 (en) * 1999-12-10 2004-04-20 Micron Technology, Inc. Polysilicon etch useful during the manufacture of a semiconductor device
US6365516B1 (en) 2000-01-14 2002-04-02 Advanced Micro Devices, Inc. Advanced cobalt silicidation with in-situ hydrogen plasma clean
US6492275B2 (en) 2000-01-21 2002-12-10 Advanced Micro Devices, Inc. Control of transistor performance through adjustment of spacer oxide profile with a wet etch
US20020086547A1 (en) * 2000-02-17 2002-07-04 Applied Materials, Inc. Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask
US6261936B1 (en) 2000-06-07 2001-07-17 Advanced Micro Devices, Inc. Poly gate CD passivation for metrology control
US6283131B1 (en) * 2000-09-25 2001-09-04 Taiwan Semiconductor Manufacturing Company In-situ strip process for polysilicon etching in deep sub-micron technology
US6482726B1 (en) * 2000-10-17 2002-11-19 Advanced Micro Devices, Inc. Control trimming of hard mask for sub-100 nanometer transistor gate
US20020155389A1 (en) 2000-10-24 2002-10-24 Bharath Rangarajan Inverse resist coating process
JP4530552B2 (ja) * 2001-01-29 2010-08-25 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20020187434A1 (en) * 2001-05-25 2002-12-12 Blatchford James W. Process for device fabrication in which the size of lithographically produced features is subsequently reduced
EP1328013A1 (en) * 2002-01-11 2003-07-16 Infineon Technologies AG Method of forming a line structure in a layer of a semiconductor wafer
US6774044B2 (en) * 2002-01-14 2004-08-10 Taiwan Semiconductor Manufacturing Co., Ltd Reducing photoresist shrinkage via plasma treatment
FR2840453B1 (fr) * 2002-06-04 2005-06-24 St Microelectronics Sa Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor
US6923920B2 (en) * 2002-08-14 2005-08-02 Lam Research Corporation Method and compositions for hardening photoresist in etching processes
US6991893B2 (en) * 2002-10-31 2006-01-31 Intel Corporation Controlling resist profiles through substrate modification
JP2004172311A (ja) * 2002-11-19 2004-06-17 Renesas Technology Corp 半導体装置の製造方法
KR20040061616A (ko) * 2002-12-31 2004-07-07 동부전자 주식회사 비휘발성 메모리 장치의 제조 방법
US7262070B2 (en) * 2003-09-29 2007-08-28 Intel Corporation Method to make a weight compensating/tuning layer on a substrate
US7343666B2 (en) 2004-06-30 2008-03-18 Hitachi Global Storage Technologies Netherlands B.V. Methods of making magnetic write heads with use of linewidth shrinkage techniques
US20060096081A1 (en) * 2004-06-30 2006-05-11 Hitachi Global Storage Technologies Methods of making magnetic write heads with use of a resist channel shrinking solution having corrosion inhibitors
US20060169968A1 (en) * 2005-02-01 2006-08-03 Thomas Happ Pillar phase change memory cell
US7517796B2 (en) * 2005-02-17 2009-04-14 Sandisk 3D Llc Method for patterning submicron pillars
JP2007035939A (ja) * 2005-07-27 2007-02-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR100685903B1 (ko) * 2005-08-31 2007-02-26 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100720481B1 (ko) * 2005-11-28 2007-05-22 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
TW200741959A (en) * 2006-04-20 2007-11-01 Min-Chang Dong A die and method fabricating the same
US8039309B2 (en) * 2007-05-10 2011-10-18 Texas Instruments Incorporated Systems and methods for post-circuitization assembly
KR101025741B1 (ko) * 2008-09-02 2011-04-04 주식회사 하이닉스반도체 수직 채널 트랜지스터의 활성필라 제조방법
US8980753B2 (en) * 2010-09-21 2015-03-17 United Mircroelectronics Corp. Metal gate transistor and method for fabricating the same
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
JP5682290B2 (ja) * 2010-12-20 2015-03-11 東京エレクトロン株式会社 炭素含有薄膜のスリミング方法及び酸化装置
CN103681293B (zh) * 2012-09-10 2016-04-20 中芯国际集成电路制造(上海)有限公司 自对准双重图形化方法
CN103681234B (zh) * 2012-09-10 2016-03-16 中芯国际集成电路制造(上海)有限公司 自对准双重图形的形成方法
US20150368557A1 (en) * 2014-06-23 2015-12-24 Hyosan Lee Metal etchant compositions and methods of fabricating a semiconductor device using the same
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820611A (en) * 1987-04-24 1989-04-11 Advanced Micro Devices, Inc. Titanium nitride as an antireflection coating on highly reflective layers for photolithography
US5106786A (en) * 1989-10-23 1992-04-21 At&T Bell Laboratories Thin coatings for use in semiconductor integrated circuits and processes as antireflection coatings consisting of tungsten silicide
US5126289A (en) * 1990-07-20 1992-06-30 At&T Bell Laboratories Semiconductor lithography methods using an arc of organic material
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
US5439847A (en) * 1993-11-05 1995-08-08 At&T Corp. Integrated circuit fabrication with a raised feature as mask
US5525542A (en) * 1995-02-24 1996-06-11 Motorola, Inc. Method for making a semiconductor device having anti-reflective coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101295889B1 (ko) * 2009-12-01 2013-08-12 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법

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US5976769A (en) 1999-11-02
TW332893B (en) 1998-06-01
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