KR950021347A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR950021347A
KR950021347A KR1019940035333A KR19940035333A KR950021347A KR 950021347 A KR950021347 A KR 950021347A KR 1019940035333 A KR1019940035333 A KR 1019940035333A KR 19940035333 A KR19940035333 A KR 19940035333A KR 950021347 A KR950021347 A KR 950021347A
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South Korea
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oxide film
forming
semiconductor substrate
isolation region
film
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KR1019940035333A
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KR100192629B1 (ko
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히데토시 고이케
가즈나리 이시마루
히로시 고조보리
후미토모 마츠오카
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사토 후미오
가부시기가이샤 도시바
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Publication of KR100192629B1 publication Critical patent/KR100192629B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은, 매립소자분리영역의 에지부분에서의 전계의 집중을 완화할 수 있는 매립소자분리영역의 형성방법을 제공하는 것이다.
본 발명에 있어서는, 실리콘 기판(11)상에 제1산화막(12)과 다결정 실리콘막(13)및 제2산화막(14)을 순차 형성하고, 실리콘 기판(11)에 매립소자분리영역으로 되는 도랑부(16)를 형성한다. 제1산화막(12)을 사이드 에칭한 후, 열산화법을 이용하여 제3산화막(17)을 형성한다. 그 산화시에 실리콘 기판(11)의 코너가 둥그렇게 된다. 다음에, 도랑부(16)에 제4산화막(18)을 매립하고, 그 후 에치백을 실시하여 매립소자분리영역을 형성한다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 제1실시예를 도시한 제1공정 단면도.
제2도는 본 발명에 따른 제1실시예를 도시한 제2공정 단면도.
제3도는 본 발명에 따른 제1실시예를 도시한 제3공정 단면도.
제4도는 본 발명에 따른 제1실시예를 도시한 제4공정 단면도.
제5도는 본 발명에 따른 제1실시예를 도시한 제5공정 단면도.
제6도는 본 발명에 따른 제1실시예를 도시한 제6공정 단면도.
제7도는 본 발명에 따른 제1실시예를 도시한 제7공정 단면도.
제8도는 본 발명의 방법에 의해 형성된 소자분리영역을 갖춘 반도체 기판과, 그것을 이용해 형성된 MOSFET의 게이트 산화막 및 게이트 전극층부분을 도시한 단면도.

Claims (2)

  1. 반도체 기판에 매립소자분리영역을 형성함에 있어서, 상기 반도체 기판상에 제1산화막을 형성하는 공정과, 이 제1산화막상에 반도체막 및 제2산화막을 순차 형성하는 공정, 이 제2산화막과 상기 반도체막 및 상기 제1산화막을 선택적으로 제거하는 공정, 상기 반도체 기판을 에칭하여 도랑부를 형성하는 공정, 상기 제1산화막에 사이드 에칭을 실시하여 상기 반도체 기판의 각부를 노출시키는 공정 및, 상기 도랑부를 포함하는 전면에 제3산화막을 형성함과 더불어 상기 각부를 둥그렇게 하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  2. 반도체 기판에 매립소자분리영역을 형성함에 있어서, 상기 반도체 기판상에 제1산화막을 형성하는 공정과, 이 제1산화막상에 반도체막 및 제2산화막을 순차 형성하는 공정, 이 제2산화막과 상기 반도체막 및 상기 제1산화막을 선택적으로 제거하는 공정, 상기 제1산화막을 사이드 에칭하는 공정, 상기 반도체 기판을 에칭하여 도랑부를 형성함과 더불어 상기 반도체 기판의 각부를 노출시키는 공정 및, 상기 도랑부를 포함하는 전면에 제3산화막을 형성함과 더불어 상기 각부를 둥글게 하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940035333A 1993-12-20 1994-12-20 반도체장치의 제조방법 KR100192629B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-320576 1993-12-20
JP5320576A JP2955459B2 (ja) 1993-12-20 1993-12-20 半導体装置の製造方法

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KR950021347A true KR950021347A (ko) 1995-07-26
KR100192629B1 KR100192629B1 (ko) 1999-06-15

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US (1) US5578518A (ko)
EP (1) EP0660391A3 (ko)
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US5578518A (en) 1996-11-26
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