WO1999044223A2

WO1999044223A2 - Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing

Info

Publication number: WO1999044223A2
Application number: PCT/US1999/004375
Authority: WO
Inventors: Michael F. Chisholm; David D. Daniel; Brynne K. Chisholm
Original assignee: Lsi Logic Corporation
Priority date: 1998-02-27
Filing date: 1999-02-26
Publication date: 1999-09-02
Also published as: WO1999044223A3

Abstract

A shallow trench isolation (STI) process active devices avoids creating corner effects and sub-threshold kinks by a process which does not include additional steps or additional processing time. A predetermined material, such as polysilicon or doped polysilicon, is selected for a mask layer. The material reacts to form the same isolation material to a greater depth than the isolation material formed as a passivating trench layer at a silicon substrate, under simultaneous thermochemical reaction conditions. A relatively thicker protective layer is formed by the simultaneous reacition, and the protective layer projects the upper corners of the trench layer from removal when a padding layer is removed. The end result is a rounded protective corner which prevents the corner effect and the undesirable sub-threshold voltage-current non-linearities or kinks.

Description

PROCESS OF SHALLOW TRENCH ISOLATING ACTIVE DEVICES

TO AVOID SUB-THRESHOLD KINKS ARISING FROM CORNER EFFECTS

WITHOUT ADDITIONAL PROCESSING

This invention relates to an improved process of shallow trench isolating active circuit devices to avoid sub-threshold kinks arising from a corner effect caused by a basic prior art shallow trench isolation (STI) process, without requiring additional process steps or processing time beyond that of the basic STI process, and without requiring the typical additional processing steps and processing time required in known prior art processes which avoid the corner effect problem. 1. Background of the Invention

Integrated circuit designs utilize many interconnected active circuit devices, e.g. transistors, formed upon a single silicon substrate or chip. Integrated circuits are becoming more complex, and integrated circuit designers continually strive to achieve higher degrees of functionality by forming greater numbers of active devices on the same-sized substrate. To achieve increased levels of functionality, the size of each individual active device is made smaller, and the devices are positioned closer together. As more active devices are located closer together, the need for isolation between those active devices on the substrate becomes more important. An ideally isolated active device operates free of any interference or influence from neighboring devices. To isolate the active devices on the substrate, several prior art processes have been employed. One such process is called Localized Oxidation of Silicon (LOCOS) . LOCOS involves the selective growth of silicon dioxide on and in the silicon substrate in the area between active devices. The silicon dioxide is an electrical insulator which acts as an isolating material to prevent interference and influence between active devices. To selectively locate or grow the silicon dioxide isolation barriers using a LOCOS process, a silicon nitride mask layer is formed on the silicon substrate where the active devices are to be formed. The silicon nitride mask layer protects the silicon substrate so that oxidation of the silicon into silicon dioxide occurs only in the isolation barrier regions and not where the active devices are formed.

The higher densities of active devices have made the LOCOS process unsatisfactory due to a problem known as "encroachment," sometimes called "bird's beak."

Encroachment generally relates to the intrusion of the silicon dioxide into the silicon at and below the edges of the silicon nitride mask. The encroachment consumes areas of silicon intended to be used by the active devices, thus reducing the space available for the active device and adversely influencing the performance characteristics of the active device. With smaller areas allotted for the active devices, the amount of space consumed by the encroachment becomes more significant, thus causing a substantial adverse impact on the performance of the active devices.

A process called shallow trench isolation (STI) has been developed as an alternative to LOCOS to avoid the problem of encroachment. STI involves etching shallow slots or trenches into the silicon substrate and later filling the trenches with isolating material, such as silicon dioxide. The trenches are filled with silicon dioxide and located between neighboring active devices to isolate the active devices. The STI process creates substantially uniform boundaries between the active devices, thus avoiding the LOCOS encroachment problems.

The typical STI process is best understood by reference to the accompanying drawing Figs. 1-7 which show steps in a basic STI process. Two improvements to the basic STI process are shown in Figs. 9 to 11 and 12 to 14. As shown in Fig. 1, the basic STI process begins with a silicon substrate 20, upon which a "padding" layer 24 of silicon dioxide is formed. A mask layer 22 of silicon nitride is formed on the padding layer 24 of silicon dioxide. The padding layer 24 reduces physical stress between the silicon substrate 20 and the mask layer 22. The next step shown in Fig. 2 involves etching a trench 26 through the silicon nitride mask layer 22 and the silicon dioxide padding layer 24 and into the silicon substrate 20, using an exposed area formed in the mask layer 22 to control the location of the trench 26. The trench 26 will ultimately separate and isolate neighboring active devices formed on the substrate 20.

Once the trench 26 has been etched, a thin trench or passivating layer of silicon dioxide is formed into the silicon substrate on the bottom 30 and side walls 32 and 34 of the trench 26 as shown in Fig. 3. The trench layer 28, formed by the side walls 32 and 34 and the bottom 30, passivates the substrate, helps isolate the active devices from one another, and improves the performance of the active devices. The thin silicon dioxide layer 28 is formed conventionally, in a thermal oxidizing ambient environment of a temperature typically about 900-1000 degrees Celsius. The thermal oxidizing ambient environment causes the silicon substrate 20 to oxidize resulting in the layer-like consumption of the silicon substrate 20 as silicon dioxide, which extends the layer 28 to a predetermined depth. Due to inaccuracies associated with the etching process, the bottom 30 and side walls 32 and 34 of the trench 26 are not perfectly smooth and contain small imperfections, divots and the like. The oxidation of the thin layer 28 of silicon dioxide tends to smooth out the side walls 32 and 34 and bottom 30 of the silicon substrate 20, eliminating those rough areas. Because the thin layer 28 and the padding layer 24 are both silicon dioxide, the two layers 24 and 28 essentially merge and integrate with one another, as shown in Fig. 3. Since silicon dioxide will not grow on or into the silicon nitride layer 22, side walls 35 of the silicon nitride layer 22 remain relatively flush with the side walls 32 and 34 of the newly formed silicon dioxide layer 28 as shown in Fig. 3.

Once the thermal oxidation of the silicon substrate 20 into the silicon dioxide layer 28 is complete, the trench 26 is substantially filled with silicon dioxide 36 using plasma deposition, as shown in Fig. 4. Ultimately, after the active devices are formed on the substrate 20 adjoining each side wall 32 and 34, the silicon dioxide 36 in the trench 26 also provides electrical isolation between the active devices. Since filling the trench 26 involves plasma deposition, none of the silicon substrate 20 is consumed.

The deposition of the silicon dioxide 36 typically results in a relatively small amount of silicon dioxide (not shown) deposited on an upper surface 37 of the adjoining silicon nitride layer 22, as shown in Fig. 4. Chemical mechanical polishing (CMP) is used to smooth the upper surface 37 and the upper surface of the deposited silicon dioxide 36 to remove any silicon dioxide from the upper surface 37 of the silicon nitride layer 22 and to obtain more precise lithographic control in subsequent steps .

With its upper surface 37 clear of silicon dioxide, the silicon nitride mask layer 22 is removed using a wet etch process, resulting in a configuration shown in Fig. 5. The wet etch process is highly selective and removes primarily the silicon nitride 22, although an upper portion of the deposited silicon dioxide 36 is also typically removed. The next step shown in Fig. 6 involves removing the padding layer 24 to expose the silicon substrate 20 so that the active devices can be formed on the silicon substrate 20 on opposite lateral sides of the deposited silicon dioxide 36. The padding layer 24 is removed using an isotropic etching process resulting in the configuration shown in Fig. 6. The isotropic etching process generally removes all the padding layer 24 on the upper horizontal surface of the silicon substrate 20, as well as some of the top surface of the deposited silicon dioxide 36. Unfortunately, the isotropic etching process also removes some of the silicon dioxide layer 28 formed between the silicon substrate 20 and the silicon dioxide 36 at the upper ends or corner areas of the side walls 32 and 34, thus exposing corners 38 of the silicon substrate 20 shown in Fig. 6.

The next step is to add a gate metal layer 40 on the silicon substrate 20 to start to form active devices 41 on opposite sides of the silicon dioxide 36 as shown in Fig. 7. The process of adding the gate metal layer 40 causes metal to form into the corners 38 between the substrate 20 and the silicon dioxide 36, as shown. The presence of gate metal 40 in the corners 38 detracts from the desired operational characteristics of the active devices 41 and makes the operating characteristics of the active devices 41 difficult to predict.

Each active device 41 should have an ideal operational current-voltage characteristic as represented by the curve 42 shown in Fig. 8. As the voltage increases beyond a characteristic threshold voltage (V_τ) of the active device, the change in the magnitude of the current conducted by the device does not vary substantially with increasing voltage. The region beyond V_τ is known as the pinch-off or saturation region. When the voltage on the active device is below a predetermined turn-on voltage (V₀) , the device is not turned on and the change in current conducted by the device with respect to change in voltage is relatively minimal. As the applied voltage varies between the turn-on voltage V₀ and the threshold voltage V_τ, the ideal current conduction through the device should vary substantially linearly with respect to voltage as shown by curve 42. Linear characteristics in this region between V₀ and V_τ, known as the sub-threshold region, are important to integrated circuit designers, and are often exploited in order to achieve specific circuit functionality.

When the gate layer metal 40 forms in the corners 38, as shown in Fig. 7, the operational characteristics of the active device within the sub-threshold region (V₀ to V_τ) do not follow the linear curve 42 (Fig. 8) . Instead, the operational characteristics are nonlinear as represented by the dashed line curve 44 shown in Fig. 8. Essentially, the additional metal 40 creates a small, second active device in the corners 38 (Fig. 7) . The second device has its own turn-on voltage and threshold voltage, and when it turns on, the resulting combined characteristics are different from those of the ideal active device. The result is a nonlinear operational region, represented by the dashed curve 44, known as a "sub-threshold kink." This sub-threshold kink replaces the ideal linear curve 42. This sub-threshold kink is well known in the art, and is sometimes referred to as the "corner effect" or "edge effect."

One prior art process to correct the corner effect problem is illustrated in Figs. 9 to 11. This prior art process involves the additional step of forming a layer 46 of excess silicon dioxide after the layer 22 of silicon nitride has been removed as shown in Fig. 5, but before the silicon dioxide padding 24 is removed as shown in Fig. 6. Then the excess silicon dioxide layer 46 and the padding layer 24 are removed simultaneously using the dry etch process. However, due to the thickness of the combined layers 24 and 26 at the upper surface of the silicon substrate 20 adjacent to the deposited silicon dioxide 36, a small portion of silicon dioxide is not removed and remains next to the deposited silicon dioxide 36, thereby forming a rounded edge 47 as shown in Fig. 10. The rounded edge 47 results because the amount of silicon dioxide in the layers 24 and 46 adjacent to the deposited silicon dioxide 36 is substantial enough that the dry etching does not remove it. The rounded edge 47 prevents the exposed corners 38 of the upper edges or pores of the side walls 32 and 34 (Fig. 6) from forming.

The next step involves placing a layer 48 of gate metal on top of the silicon substrate 20 as shown in Fig. 11. Since the exposed corners 38 (Fig. 6) are not created because of the rounded edges 47, there is no gate metal directly between the silicon substrate 20 and the deposited silicon dioxide 36, as there is in the layer 40 of gate metal shown in Fig. 7. Consequently, no secondary devices are created and the current-voltage characteristics of the active device are more predictable and similar to those of the ideal active device shown by curve 42 in Fig. 8.

Although effective in avoiding the problems of the sub-threshold kinks resulting from the corner effect, the prior art process represented by Figs. 9 to 11 requires the additional processing step of forming the excess layer 46 (Fig. 9) . To remove the excess layer 46 along with the padding layer 24 may also require additional or longer etching. Each additional or longer process step increases the manufacturing cost of the integrated circuit .

Another prior art process to correct the corner effect problem is illustrated in Figs. 12 to 14. This prior art process involves creating an offset side wall 50 in the silicon nitride mask layer 22, as shown in Fig. 12, after forming the trench in the step shown in Fig. 2. Forming the offset side wall 50 requires that some of the nitride mask layer 22 be removed to offset the side wall 50 back from the trench 26 in the silicon substrate 20 and the padding layer 24. The offset side wall 50 is preferably formed using a selective etching process after the trench 26 has been formed.

Once the offset side wall 50 in the silicon nitride mask layer 22 has been formed, the trench layer 28 of silicon dioxide is formed inside the trench 26, as shown in Fig. 13. The layer 28 of silicon dioxide is formed in the manner discussed previously in connection with Fig. 3. The trench 26, including the space between the offset side walls 50, is then filled with silicon dioxide 52, as shown in Fig. 13, using the plasma deposition process discussed in connection with Fig. 4. The deposited silicon dioxide 52 forms natural shoulders 54 that contact the side walls 50 of the mask layer 22 and overhang the padding layer 24 at the edges of the trench 26, as shown in Fig. 13.

Following removal of the nitride layer 22 in the manner previously discussed in conjunction with Fig. 5, the silicon dioxide 52 of the shoulders 54 remains overhanging the edges of the padding layer 24 adjacent to the trench, as shown in Fig. 14. The shoulders 54 of silicon dioxide 52 prevent the upper ends of the side walls 32 and 34 of the layer 28 of silicon dioxide from being etched away when the padding layer 24 is removed, thus preventing the corners 38 from forming as shown in

Fig. 6. Instead, the shoulders 54 and top portion of the silicon dioxide 52 are partially consumed when the padding layer 24 is removed, leaving the rounded edges 47 as shown in Fig. 10. Thereafter, the gate metal layer 48 is added, as described in connection with Fig. 11. The drawbacks associated with the prior art process in Figs. 12 to 14 is that the selective etching process used to offset the side walls 50 of the silicon nitride mask layer 22 from the trench 26 adds an additional process step and also tends to etch the exposed silicon substrate 20 in the trench 26 (Fig. 12). Unfortunately, the etching process to offset the side wall 50 is difficult to control and therefore the silicon substrate 20 often becomes damaged during the process. Damaging the substrate 20 typically causes defective or poorly functioning active devices because the layer 28 of silicon dioxide is not integrally uniform due to the damaged silicon substrate 20. Thus, although the prior process shown in Figs. 12 to 14 prevents the corner effect problems, the excess process steps and the risk of faulty or poorly functioning active devices generally make this process undesirable for use.

It is with respect to this and other considerations relative to the problem of sub-threshold kinks caused by the corner effect that the present invention has evolved. 2. Summary of the Invention

One aspect of the present invention relates to an improved shallow trench isolation process for active devices in an integrated circuit which avoids creating active devices which suffer from sub-threshold kinks due to a corner effect. Another aspect of the present invention relates to an improved shallow trench isolation process which avoids creating corner effects without adding additional steps to the basic fabrication process. A further aspect of the present invention relates to an improved shallow trench isolation process which avoids damaging the silicon substrate and therefore creating faulty or poorly functioning active devices while avoiding corner effects in the active devices. In accordance with these and other aspects, the improved process of the present invention relates to shallow trench isolating active devices in a substrate without creating corner effects by a process which includes the basic steps of: forming a padding layer on the substrate; forming a mask layer of predetermined material on the padding layer; forming a trench through the mask layer, the padding layer and into the substrate; forming a trench layer of isolation material at the substrate within the trench; depositing isolating material in the trench; removing the mask layer; and removing the padding layer. In addition however, the inventive process further includes the steps of: selecting the predetermined material of the mask layer to form isolation material to a greater depth than isolation material is formed at the substrate under simultaneous reaction conditions; and simultaneously reacting the substrate and the predetermined material to form the trench layer and a protective layer which is relatively thicker than the trench layer and which overhangs the trench layer above the padding layer. An upper corner area of the trench layer is protected against removal when removing the padding layer by the relatively thicker protective layer.

Preferably, the reaction is a thermochemical oxidizing reaction, the substrate is silicon, and the predetermined material is polysilicon or doped polysilicon. The relatively thicker protective layer, the padding layer and the trench layer are preferably of the same silicon dioxide which integrates and merges these layers together. Removing a portion of the relatively thicker protective layer preferably creates a relatively rounded edge which protects the trench layer during removal of the padding layer.

The improved steps of the present invention are neither additions to or modifications of the basic process steps, except insofar as the predetermined material is changed from silicon nitride. The protection afforded by the thicker overhanging protective layer occurs as a result of the more rapid and deeper oxidation the polysilicon compared to the oxidation of the silicon. Therefore, no additional time is required to achieve the protection of the deeper overhanging layer. The protection afforded by the rounded edge of the protective layer occurs naturally and simultaneously with the removal of the padding layer. Therefore, no additional steps beyond those of the basic process are required, but yet the protection of the rounded corner is achieved without the additional steps used in the prior art processes to obtain the rounded corner. A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of presently preferred embodiment of the invention, and to the appended claims.

3. Brief Description of the Drawings

Figs. 1 to 7 are partial side view illustrations of typical basic prior art steps employed to form shallow trench isolation between active devices on a silicon substrate.

Fig. 8 is graph of an idealized current-voltage characteristic curve of an ideally isolated active device and a superimposed graph of a typical sub-threshold kink or nonlinear region of the current-voltage characteristic of an actual device isolated by the basic prior art shallow trench isolation process shown in Figs. 1-7.

Figs. 9 to 11 are partial side view illustrations of prior art steps employed to avoid creating an active device with a corner effect shown in Fig. 6 and the resulting sub-threshold kink or nonlinear region of the current-voltage characteristic shown in Fig. 8.

Figs. 12 to 14 are partial side view illustrations of prior art steps which are alternatives to those shown in Figs. 9 to 11 to avoid creating an active device with a corner effect shown in Fig. 6 and the resulting sub- threshold kink or nonlinear region of the current-voltage characteristic shown in Fig. 8.

Figs. 15 to 19 are partial side view illustrations of the new and improved steps employed to form shallow trench isolation between active devices on a silicon substrate and to avoid creating an active device with a corner effect shown in Fig. 6, and to avoid the resulting sub-threshold kink or nonlinear region of the current- voltage characteristic shown in Fig. 8, in accordance with the present invention. 4. Detailed Description

The present inventive shallow trench isolation (STI) process is shown in Figs. 15 to 19. The present inventive STI process begins as shown in Fig. 15 with the silicon substrate 20 upon which the padding layer 24 of silicon dioxide is formed. A mask layer 56 of polysilicon is formed on top of the padding layer 24. The padding layer 24 reduces the stress between the silicon substrate 20 and the polysilicon mask layer 56. The configuration shown in Fig. 14 is similar to the prior art configuration shown in Fig. 1, except that the mask layer 56 of the present invention is formed of polysilicon, rather than silicon nitride. As is discussed below, the polysilicon mask layer 56 advantageously oxidizes or reacts into an deeper depth of silicon dioxide when the silicon dioxide trench layer 28 is formed, and of additional thicker depth of the silicon dioxide in the mask layer 56 is sufficient to prevent the corner effect when the padding layer 24 is removed. The trench 26 is thereafter etched into the silicon dioxide padding layer 24 and the silicon substrate 20 as shown in Fig. 16, using the polysilicon layer 56 as a mask. The trench 26 is formed in the same manner discussed previously in connection with Fig. 2. The trench creates the bottom 30 and side walls 32 and 34 in the substrate 20.

Next, the configuration shown in Fig. 16 is exposed to a thermal oxidizing thermochemical ambient environment. The thermal oxidizing ambient environment creates the thin trench layer 28 of silicon dioxide within the silicon substrate 20 in the trench 26 at the bottom 30 and side walls 32 and 34, and simultaneously creates a thicker protective layer 58 of silicon dioxide into the polysilicon mask layer 56, as shown in Fig. 17. The polysilicon material of the mask layer 56 is sufficiently similar to the silicon substrate 20 so that both the silicon and the polysilicon oxidize resulting in the layers 28 and 58 of silicon dioxide, respectively. However, the crystalline structure of the polysilicon mask layer 56 oxidizes into the silicon dioxide more rapidly and more deeply than the silicon 20 oxidizes into silicon dioxide layer 28. As a result, the layer 58 of silicon dioxide formed into the polysilicon mask layer 56 is thicker than the trench layer 28 of silicon dioxide formed into the substrate 20, as shown in Fig. 17. Although formed at different rates and to different depths, the layers 24, 28 and 58 merge and integrate together since they are all silicon dioxide. As will be understood from the following discussion, the thicker protective layer 58 of silicon dioxide formed into the polysilicon mask layer 56 is sufficient to prevent the corner effect. Although polysilicon may be used to form the mask layer 56, other materials capable of having a greater oxidation rate and depth than the silicon substrate, but still capable of oxidizing into silicon dioxide simultaneously with the formation of the layers 28 and 58, may also be used in accordance with the present invention. Examples of such predetermined materials which achieve a differential oxidizing or reacting effect included doped polysilicon such as phosphorus impregnated polysilicon film.

The next step involves plasma depositing the silicon dioxide 36 inside the trench 26, as shown in Fig. 18. Once the silicon dioxide 36 is deposited within the trench 26, chemical mechanical polishing (CMP) is applied to the upper horizontal surfaces of the configuration to remove any silicon dioxide (not shown) deposited on the upper horizontal surfaces. The CMP assists in performing subsequent lithographic steps during the process.

Thereafter the thicker layer 58 of silicon dioxide formed into the polysilicon mask layer 56 and an upper portion of the deposited silicon dioxide 36 are removed, resulting in the configuration shown in Fig. 18. The vertical portions of the thicker layer 58 remain adjacent to the deposited silicon dioxide 36 after the horizontal portions of the thicker layer 58 have been removed.

Next, the remaining mask layer 56 of polysilicon is removed using a wet etch process. The wet etch process has a high selectivity to remove primarily only the polysilicon layer 56 and leave the vertical portions of the thicker layer 58 of silicon dioxide adjacent to the vertical sides of the deposited silicon dioxide 36, as shown in Fig. 19. The thicker vertical portion of the layer 58 overhangs and merges with the edge of the padding layer 24 adjoining the deposited silicon dioxide 36.

Thereafter, the padding layer 24 is removed using an isotropic etch process as discussed above in connection with Fig. 6. However, the vertical portions of the thicker protective layer 58 of silicon dioxide are sufficiently thick to prevent the wet etching from reaching the thin layer 28 of silicon dioxide between the silicon substrate 20 and the deposited silicon dioxide 36. As a result, no corners 38 (Fig. 6) become exposed, but instead the silicon dioxide from the thicker layer 58 remains to create the rounded edge 47 as shown in Fig. 10.

The depth of the thicker protective layer 58 should be at least equal to, and preferably slightly greater than, the vertical dimension between the upper surface of the substrate 20 and the upper surface of the deposited isolating material 36. With these dimensions, the wet etching used to remove the padding layer 24 (Fig. 6) will result in none of the trench layer 28 of silicon dioxide being removed at the upper edge or corner 38 (Fig. 6) of the side walls 32 between the isolating deposited material 36 and the substrate 20. Under such circumstances, the upper surface of the deposited silicon dioxide 36 will also remain at or above the level of the upper surface of the substrate 20. In other words, the laterally outward exposed sides of the thicker layer 58 shown in Fig. 19 will not be removed any more quickly or to a greater extent than the upper surface of the deposited silicon dioxide 36 will be removed.

The next step involves placing the layer 48 of gate metal on top of the silicon substrate 20 as shown and previously discussed in connection with Fig. 11. Since the corners 38 (Fig. 6) are not exposed, there is no gate metal directly between the silicon substrate 20 and the deposited silicon dioxide 36, as there is in the layer 40 of gate metal shown in Fig. 7. Consequently, no secondary devices are created, and the current-voltage characteristics of the active device are more predictable and similar to those of the ideal active device shown by curve 42 in Fig . 8 .

As noted above, the polysilicon material 56 has a different crystalline structure as compared to the silicon substrate 20, and this difference in crystalline structure causes the resulting layers 58 of silicon dioxide to have a different depth or thickness compared to the layer 28 of silicon dioxide which is formed simultaneously. The oxidation time period needed to form the thicker silicon dioxide layer 58 is no greater than that required to form the thinner silicon dioxide layer

28 to its desired depth. By selecting the material to be used for the mask layer 56 (Figs. 15-18), control over the differential in oxidation rate and depth of the mask layer material 56 compared to the substrate material 20 is achieved, and the thickness of the protective layer 58 is thereby controlled to ensure that no corner effects occur in the completed active device.

The present inventive process comprises the same number of steps employed by the basic prior art STI technique described in connection with Figs. 1-7.

Furthermore, the time to accomplish the number of steps is not significantly longer than the time to accomplish the prior art steps, because of the greater rate of oxidation attributable to the polysilicon mask layer 56 (Fig. 17) compared to that of the silicon substrate.

Despite requiring the same number of steps as the basic process and requiring no more time than the basic process, the present inventive process does not result in the creation of the detrimental corner effect. Furthermore, the improved process of the present invention is achieved by performing a lesser number of steps than those required by the prior art technique (Figs. 9 to 11 and 12 to 14), but the improved process of the present invention still results in the protective rounded edge 47 (Fig. 10) . Thus, the improved process of the present invention achieves the same benefits, i.e. the protective rounded edge 47 (Fig. 10) , as the prior art processes, but by use of a simpler and less complex process. The simplicity of the present inventive process compares with that of the basic prior art process (Figs. 1-7) which was not capable of avoiding the detrimental sub-threshold kink effects associated with the corner effect .

A presently preferred embodiment of the present invention has been described with a degree of particularity. This description is of a preferred example of implementing the invention, and is not necessarily intended to limit the scope of the invention. The scope of the invention is defined by the following claims.

Claims

The invention claimed is:

1. A process of shallow trench isolating active devices in a substrate which includes the steps of: forming a padding layer on the substrate; forming a mask layer of predetermined material on the padding layer; forming a trench through the mask layer, the padding layer and into the substrate; forming a trench layer of isolation material at the substrate within the trench; depositing isolating material in the trench; removing the mask layer; and removing the padding layer; said process further including the improved steps of: selecting the predetermined material of the mask layer to form isolation material to a greater depth than the trench layer of isolation material is formed at substrate under simultaneous reaction conditions; simultaneously reacting the substrate and the predetermined material to form the trench layer and a protective layer respectively, the protective layer forming to a depth at least as thick as the trench layer and at a location which overhangs the trench layer above the padding layer; and protecting an upper corner area of the trench layer against removal by the relatively thicker protective layer when removing the padding layer.

2. A process as defined in claim 1 wherein the protective layer, the padding layer and the trench layer are of the same material.

3. A process as defined in claim 2 wherein the protective layer, the padding layer and the trench layer integrate and merge together.

4. A process as defined in claim 1 wherein the protective layer is at least as thick as a dimension between an upper surface of the substrate and an upper surface of the isolating material deposited in the trench, before the padding layer is removed.

5. A process as defined in claim 1 wherein the improvements further include the step of: removing a portion of the protective layer to create a relatively rounded edge above the trench layer during removal of the padding layer.

6. A process as defined in claim 5 further comprising the step of depositing a layer of gate material over the rounded edge.

7. A process as defined in claim 1 wherein the substrate is substantially silicon and the predetermined material is substantially polysilicon.

8. A process as defined in claim 7 wherein the protective layer, the padding layer and the trench layer are substantially silicon dioxide.

9. A process as defined in claim 1 wherein the substrate is substantially silicon and the predetermined material is substantially doped polysilicon.

10. A process as defined in claim 1 wherein the substrate is substantially silicon and the predetermined material is phosphorus impregnated polysilicon.

11. A process as defined in claim 1 wherein the reaction is a chemical oxidation.

12. A process as defined in claim 1 wherein the reaction occurs in a thermal oxidizing ambient environment .

13. A process as defined in claim 1 wherein the deposited protective material is substantially silicon dioxide .

14. A process as defined in claim 1 wherein the active device is a transistor.

15. A process of shallow trench isolating transistors in a silicon substrate which includes the steps of: forming a padding layer of silicon dioxide on the silicon substrate; forming a mask layer of predetermined material on the padding layer; forming a trench through the mask layer, the padding layer and into the substrate; forming a trench layer of silicon dioxide into the substrate within the trench; depositing isolating silicon dioxide material in the trench; removing the mask layer; and removing the padding layer; said process further including the improves steps of: selecting the predetermined material of the mask layer to oxidize into silicon dioxide to a greater depth than the trench layer is oxidized into silicon substrate under simultaneous oxidizing conditions; and simultaneously thermochemically oxidizing a silicon dioxide trench layer into the silicon substrate and a silicon dioxide protective layer into the predetermined material, the protective layer forming to relatively thicker depth than the depth of the trench layer due to the thermochemical oxidizing characteristics of the selected predetermined material, the protective layer also forming at a location which overhangs the trench layer at the trench layer.

16. A process as defined in claim 15, further comprising the step of: protecting upper ends of the trench layer against removal by the relatively thicker overhanging protective layer of silicon dioxide during removal of the padding layer.

17. A process as defined in claim 15 wherein the predetermined material is selected from the group consisting of substantially polysilicon and doped polysilicon.

18. A process as defined in claim 15 wherein the relatively thicker protective layer, the padding layer and the trench layer integrate and merge together.

19. A process as defined in claim 15 further including the steps of: removing a portion of the relatively thicker silicon dioxide protective layer to create a relatively rounded edge of silicon dioxide above the trench layer during removal of the padding layer; and depositing a layer of gate metal on the silicon substrate and the rounded edge.

20. A semiconductor structure formed during a process of shallow trench isolating active devices in a substrate, comprising: a substrate formed of substrate material; a padding layer formed on the substrate; a mask layer formed on the padding layer, the mask layer formed of a predetermined material which thermochemically reacts to form isolation material to a greater depth than the substrate material forms isolation material under similar thermochemical reactions; a trench formed into the mask layer, the padding layer and the substrate; a trench layer of isolation material formed by a thermochemical reaction at the substrate in the trench; and a protective layer of isolation material formed simultaneously with the trench layer by the thermochemical reaction at the predetermined material of the mask layer, the protective layer having a greater depth than the trench layer.