KR940004726A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

Info

Publication number
KR940004726A
KR940004726A KR1019920015206A KR920015206A KR940004726A KR 940004726 A KR940004726 A KR 940004726A KR 1019920015206 A KR1019920015206 A KR 1019920015206A KR 920015206 A KR920015206 A KR 920015206A KR 940004726 A KR940004726 A KR 940004726A
Authority
KR
South Korea
Prior art keywords
layer
conductive layer
conductive
forming
semiconductor
Prior art date
Application number
KR1019920015206A
Other languages
English (en)
Other versions
KR950009283B1 (ko
Inventor
신헌종
송윤흡
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920015206A priority Critical patent/KR950009283B1/ko
Priority to JP20518793A priority patent/JP3408842B2/ja
Publication of KR940004726A publication Critical patent/KR940004726A/ko
Application granted granted Critical
Publication of KR950009283B1 publication Critical patent/KR950009283B1/ko
Priority to US08/736,490 priority patent/US5717253A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

도전 또는 비도전성의 하부막질상에 불순물 함유하는 제1반도체 도전층을 형성하고 이 위에 버퍼층을 형성하고 다시 그 위에 제2의 반도체 도전층을 형성하는 단계, 상기 제2의 반도체 도전층 위에 내화 금속층을 형성하고 열처리하는 단계를 포함하여 상기 제1도전층상에 실리사이드층을 형성하며 실리사이데이션시 상기 버퍼층은 제1도전층의 구성물질이 제2도전층으로 이동하는 것을 억제하는 것을 특징으로 하는 반도체 장치의 제조방법에 관한 것.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 (a)∼(d)는 본 발명의 제1실시예에 따른 실리사이드 형성공정을 설명하는 제조공정도.
제2도는 (a)∼(c)는 본 발명의 제2실시예에 따른 실리사이드 형성공정을 설명하는 제조공정도.

Claims (9)

  1. 도전 또는 비도전성의 하부막질상에 불순물을 함유하는 제1반도체 도전층을 형성하고 이 위에 버퍼층을 형성하고 다시 그 위에 제2의 반도체 도전층을 형성하는 단계와, 상기 제2의 반도체 도전층 위에 내화금속층을 형성하고 열처리하는 단계를 포함하여 상기 제1도전층상에 실리사이드층을 형성하며, 실리사이데이션시 상기 버퍼층은 제1도전층의 구성물질이 제2도전층으로 이동하는 것을 억제하는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 제1도전층은 불순물이 함유된 다결정 실리콘층, 버퍼층은 TiN 또는 SiO2, 제2도전층은 불순물이 포함안된 다결정 실리콘층 내화금속층은 Ti인 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제2항에 있어서 상기 버퍼층은 질소분자 또는 이온을 이온주입방법으로 제1도전층에 형성됨을 특징으로 하는 반도체장치의 제조방법.
  4. 제2항에 있어서, 상기 제2도전층은 비정질 실리콘층임을 특징으로 하는 반도체장치의 제조방법.
  5. 도전 또는 비도전성의 하부막질상에 불순물을 함유한 제1반도체 도전층을 형성하고 이 위에 버퍼층 및 제2의 반도체층을 형성하는 단계와, 실리사이드화 할 메탈과 실리콘을 공히 스퍼터링하고 열처리하고 상기 제2반도체층을 실리사이드층으로 하는 단계를 포함하여 실리사이드를 형성하는 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제5항에 있어서, 상기 제1도전층은 불순물이 함유된 다결정 실리콘층, 버퍼층은 TiN 또는 SiO2, 제2도전층은 불순물이 포함안된 다결정 실리콘층 내화 금속층은 Ti인 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제6항에 있어서, 상기 버퍼층은 질소분자 또는 이온을 이온주입방법으로 제1도전층에 형성됨을 특징으로 하는 반도체장치의 제조방법.
  8. 제6항에 있어서, 상기 제1도전층은 비정질 실리콘층임을 특징으로 하는 반도체장치의 제조방법.
  9. 제5항에 있어서, 상기 제2반도체층 형성단계후, 실리사이드 타겟으로부터 직접 스퍼터링, 열처리로 상기 제2도전층을 실리사이드화 하는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920015206A 1992-08-24 1992-08-24 반도체장치의 제조방법 KR950009283B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920015206A KR950009283B1 (ko) 1992-08-24 1992-08-24 반도체장치의 제조방법
JP20518793A JP3408842B2 (ja) 1992-08-24 1993-08-19 半導体装置およびその製造方法
US08/736,490 US5717253A (en) 1992-08-24 1996-10-24 Structure for forming an improved quality silicidation layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015206A KR950009283B1 (ko) 1992-08-24 1992-08-24 반도체장치의 제조방법

Publications (2)

Publication Number Publication Date
KR940004726A true KR940004726A (ko) 1994-03-15
KR950009283B1 KR950009283B1 (ko) 1995-08-18

Family

ID=19338377

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920015206A KR950009283B1 (ko) 1992-08-24 1992-08-24 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US5717253A (ko)
JP (1) JP3408842B2 (ko)
KR (1) KR950009283B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100504188B1 (ko) * 1997-12-30 2005-10-19 매그나칩 반도체 유한회사 반도체장치의 게이트전극 제조방법
KR100510442B1 (ko) * 1997-11-24 2005-10-21 삼성전자주식회사 이중층실리사이드의형성방법및정합실리사이드를구비하는모스트랜지스터

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844297A (en) * 1995-09-26 1998-12-01 Symbios, Inc. Antifuse device for use on a field programmable interconnect chip
US6004869A (en) * 1997-04-25 1999-12-21 Micron Technology, Inc. Method for making a low resistivity electrode having a near noble metal
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
US6117793A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Using silicide cap as an etch stop for multilayer metal process and structures so formed
KR100313943B1 (ko) * 1999-04-22 2001-11-15 김영환 반도체 소자의 게이트 전극 형성 방법
KR100370156B1 (ko) * 2000-08-01 2003-01-30 주식회사 하이닉스반도체 반도체 소자의 제조방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07114214B2 (ja) * 1987-08-03 1995-12-06 三菱電機株式会社 半導体装置
EP0704883A3 (en) * 1988-02-11 1997-07-09 Sgs Thomson Microelectronics Refractory metal silicide cap, to protect multi-layer polycide structures
JP2675572B2 (ja) * 1988-03-31 1997-11-12 株式会社東芝 半導体集積回路の製造方法
US5237192A (en) * 1988-10-12 1993-08-17 Mitsubishi Denki Kabushiki Kaisha MESFET semiconductor device having a T-shaped gate electrode
US5075761A (en) * 1989-05-31 1991-12-24 Sgs-Thomson Microelectronics, Inc. Local interconnect for integrated circuits
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5243220A (en) * 1990-03-23 1993-09-07 Kabushiki Kaisha Toshiba Semiconductor device having miniaturized contact electrode and wiring structure
JP2675713B2 (ja) * 1991-05-10 1997-11-12 株式会社東芝 半導体装置及びその製造方法
US5313084A (en) * 1992-05-29 1994-05-17 Sgs-Thomson Microelectronics, Inc. Interconnect structure for an integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510442B1 (ko) * 1997-11-24 2005-10-21 삼성전자주식회사 이중층실리사이드의형성방법및정합실리사이드를구비하는모스트랜지스터
KR100504188B1 (ko) * 1997-12-30 2005-10-19 매그나칩 반도체 유한회사 반도체장치의 게이트전극 제조방법

Also Published As

Publication number Publication date
US5717253A (en) 1998-02-10
JP3408842B2 (ja) 2003-05-19
JPH06163457A (ja) 1994-06-10
KR950009283B1 (ko) 1995-08-18

Similar Documents

Publication Publication Date Title
EP0723286A3 (en) Field-effect transistor and manufacture method thereof
TW349247B (en) Process for producing semiconductor element
KR900019239A (ko) 집적회로용 로칼인터커넥트
JPH0855982A (ja) 半導体デバイス及びその製造方法
KR950004410A (ko) 반도체장치의 게이트형성방법
KR940004726A (ko) 반도체 장치의 제조방법
KR960035824A (ko) 타이타늄 카본 나이트라이드 게이트전극 형성방법
KR960005801A (ko) 반도체 장치 제조방법
KR970024304A (ko) 박막 트랜지스터 제조방법
KR960030328A (ko) 반도체 장치의 금속층 형성방법
KR960009013A (ko) 타이타늄 나이트라이드(TiN) 게이트전극 형성방법
KR100348780B1 (ko) 실리콘박막을결정화하는방법
GB2167899A (en) Method of manufacturing thin film transistors
KR940010194A (ko) 반도체장치의 배선층 형성방법
KR940007995A (ko) 반도체장치의 제조방법
JP3055201B2 (ja) 半導体装置の製造方法
JPH04186734A (ja) 半導体装置の製造方法
KR19990081207A (ko) 박막 트랜지스터 및 그 제조방법
KR940018922A (ko) 반도체 소자의 금속배선 방법
KR970072211A (ko) 저저항 금속 규화물층을 가지는 반도체 장치 제조 방법
EP0394590A3 (en) Field effect transistors and method of making a field effect transistor
US6787436B1 (en) Silicide-silicon contacts for reduction of MOSFET source-drain resistances
KR950021113A (ko) 반도체 소자의 게이트 전극 형성 방법
KR19980065681A (ko) 실리사이드층의 비저항을 줄일 수 있는 반도체 장치 제조방법
JPH04120736A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100729

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee