KR920015494A - 수지 봉지형 반도체 집적 회로 - Google Patents
수지 봉지형 반도체 집적 회로 Download PDFInfo
- Publication number
- KR920015494A KR920015494A KR1019920000832A KR920000832A KR920015494A KR 920015494 A KR920015494 A KR 920015494A KR 1019920000832 A KR1019920000832 A KR 1019920000832A KR 920000832 A KR920000832 A KR 920000832A KR 920015494 A KR920015494 A KR 920015494A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor integrated
- encapsulated semiconductor
- wiring layer
- integrated circuit
- interlayer insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 239000011347 resin Substances 0.000 title claims 3
- 229920005989 resin Polymers 0.000 title claims 3
- 239000010410 layer Substances 0.000 claims 4
- 239000011229 interlayer Substances 0.000 claims 3
- 238000002161 passivation Methods 0.000 claims 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도는 본 발명의 한 실시예를 개략적으로 나타내는 평면도, 제1B도는 제 1A도의 X-X선에 있어서 확대단면도, 제2도는 배선층이 슬라이드를 일으키는 폭의 상한과 반도체 칩의 한 모서리에서의 거리 관계를 나타내는 그래프, 제3도는 본 발명의 한 실시예의 변형을 개략적으로 나타내는 평면도이다.
Claims (3)
- 층간절연막을 가지는 방형상의 반도체칩과, 상기 층간절연막에 선택적으로 피착되고, 상기 반도체 칩의 한 모서리에서의 거리에 따라 합계폭이 불연속적으로 끼우게 되는 배선층 및 상기 한 모서리에서의 거리에 따라 상기 배선층을 폭방향으로 복수의 부분에 구절하는 수단에서 되는 전원 배선 또는 접지 배선과, 상기 배선층이 설치된 층간절연막을 피복하는 패시베이션막을 가지는 수지 봉지형 반도체 집적 회로.
- 제1항에 있어서, 상기 배선층을 구절하는 수단은 폭이상기 패시 베이션 막두께의 적어도 2배 슬릿인 수지 봉지형 반도체 집적 회로.
- 제1항에 있어서, 상기 패시베이션막을 실리콘 옥시나이드라이드막 또는 질화 실리콘막인 수지 봉지형 반도체 집적 회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP547091 | 1991-01-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920015494A true KR920015494A (ko) | 1992-08-27 |
KR950012657B1 KR950012657B1 (en) | 1995-10-19 |
Family
ID=11612132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92000832A KR950012657B1 (en) | 1991-01-22 | 1992-01-22 | Resin sealed semiconductor integrated circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US5289036A (ko) |
EP (2) | EP1587143A1 (ko) |
KR (1) | KR950012657B1 (ko) |
DE (1) | DE69233550T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100353091B1 (ko) * | 1999-08-30 | 2002-09-16 | 넥스콘 테크놀러지 주식회사 | 무광원 스케닝방법 및 그 장치 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05175191A (ja) * | 1991-10-22 | 1993-07-13 | Mitsubishi Electric Corp | 積層導電配線 |
TW264385B (ko) * | 1993-05-14 | 1995-12-01 | Taiho Pharmaceutical Co Ltd | |
KR0149061B1 (ko) * | 1993-09-17 | 1998-10-01 | 세끼자와 다다시 | 스파이크 노이즈 억제용 cmos ic 장치와 그 제조 방법 |
WO1995017007A1 (en) * | 1993-12-14 | 1995-06-22 | Oki America, Inc. | Efficient routing method and resulting structure for integrated circuits |
US6300688B1 (en) * | 1994-12-07 | 2001-10-09 | Quicklogic Corporation | Bond pad having vias usable with antifuse process technology |
KR0170316B1 (ko) * | 1995-07-13 | 1999-02-01 | 김광호 | 반도체 장치의 패드 설계 방법 |
US5712510A (en) * | 1995-08-04 | 1998-01-27 | Advanced Micro Devices, Inc. | Reduced electromigration interconnection line |
US5689139A (en) * | 1995-09-11 | 1997-11-18 | Advanced Micro Devices, Inc. | Enhanced electromigration lifetime of metal interconnection lines |
JP2755239B2 (ja) * | 1995-11-25 | 1998-05-20 | 日本電気株式会社 | 半導体装置用パッケージ |
JP3500308B2 (ja) | 1997-08-13 | 2004-02-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 集積回路 |
US5959360A (en) * | 1998-05-22 | 1999-09-28 | United Microelectronics Corp. | Interconnect structure employing equivalent resistance paths to improve electromigration resistance |
US5963831A (en) * | 1998-05-22 | 1999-10-05 | United Microelectronics Corp. | Method of making an interconnect structure employing equivalent resistance paths to improve electromigration resistance |
JP2000294639A (ja) * | 1999-04-09 | 2000-10-20 | Oki Electric Ind Co Ltd | 半導体装置 |
WO2002001632A2 (en) * | 2000-06-27 | 2002-01-03 | Infineon Technologies Ag | Interconnection for accomodating thermal expansion for low elastic modulus dielectrics |
US6828223B2 (en) * | 2001-12-14 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co. | Localized slots for stress relieve in copper |
US20030122258A1 (en) * | 2001-12-28 | 2003-07-03 | Sudhakar Bobba | Current crowding reduction technique using slots |
US6987323B2 (en) * | 2002-02-05 | 2006-01-17 | Oki Electric Industry Co., Ltd. | Chip-size semiconductor package |
US6940108B2 (en) * | 2002-12-05 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Slot design for metal interconnects |
US6818996B2 (en) * | 2002-12-20 | 2004-11-16 | Lsi Logic Corporation | Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps |
JP3661695B2 (ja) * | 2003-07-11 | 2005-06-15 | 株式会社デンソー | 半導体装置 |
US7388279B2 (en) * | 2003-11-12 | 2008-06-17 | Interconnect Portfolio, Llc | Tapered dielectric and conductor structures and applications thereof |
US7466021B2 (en) * | 2003-11-17 | 2008-12-16 | Interconnect Portfolio, Llp | Memory packages having stair step interconnection layers |
US7199035B2 (en) * | 2004-06-28 | 2007-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect junction providing reduced current crowding and method of manufacturing same |
US20060072257A1 (en) * | 2004-09-30 | 2006-04-06 | International Business Machines Corporation | Device and method for reducing dishing of critical on-chip interconnect lines |
US7253528B2 (en) * | 2005-02-01 | 2007-08-07 | Avago Technologies General Ip Pte. Ltd. | Trace design to minimize electromigration damage to solder bumps |
US8299775B2 (en) * | 2005-06-23 | 2012-10-30 | International Business Machines Corporation | Current-aligned auto-generated non-equiaxial hole shape for wiring |
JP2007129018A (ja) | 2005-11-02 | 2007-05-24 | Nec Electronics Corp | 半導体装置 |
JP4731456B2 (ja) | 2006-12-19 | 2011-07-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP5153015B2 (ja) * | 2008-07-02 | 2013-02-27 | シャープ株式会社 | 面発光表示装置 |
US9177914B2 (en) | 2012-11-15 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pad structure over TSV to reduce shorting of upper metal layer |
FR3008524B1 (fr) * | 2013-07-12 | 2017-05-05 | Compagnie Ind Et Financiere Dingenierie Ingenico | Dispositif de paiement electronique presentant des moyens de blocage de l'acces a la memoire fiscale. |
JP2018026451A (ja) * | 2016-08-10 | 2018-02-15 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
CN110364506B (zh) * | 2019-07-04 | 2022-01-28 | 武汉理工大学 | 一种具有高稳定性的仿生集成电路 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5717146A (en) * | 1980-07-04 | 1982-01-28 | Fujitsu Ltd | Wiring for semiconductor element |
JPS5745259A (en) * | 1980-09-01 | 1982-03-15 | Hitachi Ltd | Resin sealing type semiconductor device |
JPS5772349A (en) * | 1980-10-23 | 1982-05-06 | Nec Corp | Semiconductor integrated circuit device |
US4475119A (en) * | 1981-04-14 | 1984-10-02 | Fairchild Camera & Instrument Corporation | Integrated circuit power transmission array |
JPS59167049A (ja) * | 1983-03-14 | 1984-09-20 | Nec Corp | 半導体装置 |
JPS6010645A (ja) * | 1983-06-30 | 1985-01-19 | Toshiba Corp | 樹脂封止型半導体装置 |
US4583111A (en) * | 1983-09-09 | 1986-04-15 | Fairchild Semiconductor Corporation | Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients |
JPS6059774A (ja) * | 1983-09-13 | 1985-04-06 | Matsushita Electronics Corp | 半導体装置 |
JPS61258449A (ja) * | 1985-05-13 | 1986-11-15 | Nec Corp | 半導体集積回路装置 |
JPS6245150A (ja) * | 1985-08-23 | 1987-02-27 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
DE3530578A1 (de) * | 1985-08-27 | 1987-03-05 | Siemens Ag | Struktur zur qualitaetspruefung einer substratscheibe aus halbleitermaterial |
EP0223698A3 (en) * | 1985-11-14 | 1987-11-19 | Thomson Components-Mostek Corporation | Hillock immunization mask |
JPS62174948A (ja) * | 1986-01-28 | 1987-07-31 | Mitsubishi Electric Corp | 半導体装置 |
JPS62224046A (ja) * | 1986-03-26 | 1987-10-02 | Hitachi Ltd | 半導体装置 |
JPH0815150B2 (ja) * | 1988-01-29 | 1996-02-14 | 株式会社日立製作所 | 樹脂封止型半導体装置の製造方法 |
JPH01225137A (ja) * | 1988-03-04 | 1989-09-08 | Toshiba Corp | 半導体集積回路装置 |
-
1992
- 1992-01-22 DE DE69233550T patent/DE69233550T2/de not_active Expired - Lifetime
- 1992-01-22 US US07/823,469 patent/US5289036A/en not_active Expired - Lifetime
- 1992-01-22 KR KR92000832A patent/KR950012657B1/ko not_active IP Right Cessation
- 1992-01-22 EP EP05014178A patent/EP1587143A1/en not_active Withdrawn
- 1992-01-22 EP EP92101021A patent/EP0499063B1/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100353091B1 (ko) * | 1999-08-30 | 2002-09-16 | 넥스콘 테크놀러지 주식회사 | 무광원 스케닝방법 및 그 장치 |
Also Published As
Publication number | Publication date |
---|---|
EP1587143A1 (en) | 2005-10-19 |
DE69233550T2 (de) | 2006-06-22 |
KR950012657B1 (en) | 1995-10-19 |
EP0499063B1 (en) | 2005-09-28 |
US5289036A (en) | 1994-02-22 |
DE69233550D1 (de) | 2006-02-09 |
EP0499063A2 (en) | 1992-08-19 |
EP0499063A3 (en) | 1992-10-14 |
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