KR920022431A - 반도체 장치용 패키지 - Google Patents
반도체 장치용 패키지 Download PDFInfo
- Publication number
- KR920022431A KR920022431A KR1019920005618A KR920005618A KR920022431A KR 920022431 A KR920022431 A KR 920022431A KR 1019920005618 A KR1019920005618 A KR 1019920005618A KR 920005618 A KR920005618 A KR 920005618A KR 920022431 A KR920022431 A KR 920022431A
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- South Korea
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- external terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 제1실시예에 관한 반도체장치용 패키지를 표시하는 것으로, 외부단자를 설치한 기판의 평면도이다.
제2도는 제1도의 외부단자를 설치한 기판의 측면도이다.
제3도는 배선상태를 표시한 제1도의 부분확대 평면도이다.
제4도는 이 발명의 제2의 실시예에 관한 반도체장치용 패키지를 표시하는 것으로 개체(蓋體)부분을 떼어낸 상태를 표시하는 평면도이다.
제5도는 제4도의 V-V선에 따른 단면도이다.
제6도는 제4도의 제2실시예의 기판에 개체부분을 장착한 상태를 표시하는 측면도이다.
제7도는 제6도의 제2실시예의 저면도이다.
Claims (2)
- 기판의 일면에 반도체집적회로가 탑재됨과 동시에 타면에 다수의 외부단자가 돌출설치되어, 상기 반도체집 적회로의 단자에 각기 별도로 접속된 탑재용 랜드부의 단자편이 상기 기판에 형성된 배선회로를 통해서 상기 외부단자에 각기 별도로 접속된 반도체장치용 패키지에 있어서, 상기 외부단자가 인접해 있는 것끼리의 간격을 상기 탑재용 랜드부에 가까울수록 넓게 해서 되는 반도체장치용 패키지.
- 기판의 일면에 반도체칩이 탑재됨과 동시에, 타면에 다수의 외부단자가 돌출 설치되어 상기 반도체칩의 단자에 각기 별도로 접속된 내부단자가 상기 기판에 형성된 배선회로를 통해서 상기 외부단자에 접속된 반도체 장치용 패키지에 있어서, 상기 외부단자가 인접해 있는 것끼리의 간격을 상기 내부단자에 가까울수록 넓게해서 되는 반도체장치용 패키지.※ 참고사항 ; 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3106985A JP2872825B2 (ja) | 1991-05-13 | 1991-05-13 | 半導体装置用パッケージ |
JP91-106985 | 1991-05-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920022431A true KR920022431A (ko) | 1992-12-19 |
KR950010861B1 KR950010861B1 (ko) | 1995-09-25 |
Family
ID=14447556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920005618A KR950010861B1 (ko) | 1991-05-13 | 1992-04-03 | 반도체장치용 패키지 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5324985A (ko) |
JP (1) | JP2872825B2 (ko) |
KR (1) | KR950010861B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100411862B1 (ko) * | 1999-02-10 | 2003-12-18 | 샤프 가부시키가이샤 | 배선기판 및 반도체장치 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5798909A (en) * | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
MY123146A (en) * | 1996-03-28 | 2006-05-31 | Intel Corp | Perimeter matrix ball grid array circuit package with a populated center |
JP3414645B2 (ja) * | 1998-06-26 | 2003-06-09 | 沖電気工業株式会社 | 半導体装置 |
US6664620B2 (en) | 1999-06-29 | 2003-12-16 | Intel Corporation | Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer |
US6285560B1 (en) | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
JP3407025B2 (ja) * | 2000-06-08 | 2003-05-19 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6815621B2 (en) * | 2000-10-02 | 2004-11-09 | Samsung Electronics Co., Ltd. | Chip scale package, printed circuit board, and method of designing a printed circuit board |
EP1376698A1 (en) * | 2002-06-25 | 2004-01-02 | STMicroelectronics S.r.l. | Electrically erasable and programable non-volatile memory cell |
US7196908B2 (en) * | 2003-06-05 | 2007-03-27 | International Business Machines Corporation | Dual pitch contact pad footprint for flip-chip chips and modules |
US8053349B2 (en) * | 2007-11-01 | 2011-11-08 | Texas Instruments Incorporated | BGA package with traces for plating pads under the chip |
GB0908355D0 (en) | 2009-05-15 | 2009-06-24 | Bailey Ralph Peter S | Wind turbine diffuser |
CN109932622A (zh) * | 2017-12-16 | 2019-06-25 | 神讯电脑(昆山)有限公司 | Type-c连接器的耐高压测试装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59161843A (ja) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | 半導体装置 |
US4677526A (en) * | 1984-03-01 | 1987-06-30 | Augat Inc. | Plastic pin grid array chip carrier |
US4733293A (en) * | 1987-02-13 | 1988-03-22 | Unisys Corporation | Heat sink device assembly for encumbered IC package |
-
1991
- 1991-05-13 JP JP3106985A patent/JP2872825B2/ja not_active Expired - Lifetime
-
1992
- 1992-04-03 KR KR1019920005618A patent/KR950010861B1/ko not_active IP Right Cessation
- 1992-05-01 US US07/877,194 patent/US5324985A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100411862B1 (ko) * | 1999-02-10 | 2003-12-18 | 샤프 가부시키가이샤 | 배선기판 및 반도체장치 |
Also Published As
Publication number | Publication date |
---|---|
KR950010861B1 (ko) | 1995-09-25 |
JPH04335555A (ja) | 1992-11-24 |
US5324985A (en) | 1994-06-28 |
JP2872825B2 (ja) | 1999-03-24 |
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