KR910003665A - 반도체 기억 회로 - Google Patents

반도체 기억 회로 Download PDF

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Publication number
KR910003665A
KR910003665A KR1019900008835A KR900008835A KR910003665A KR 910003665 A KR910003665 A KR 910003665A KR 1019900008835 A KR1019900008835 A KR 1019900008835A KR 900008835 A KR900008835 A KR 900008835A KR 910003665 A KR910003665 A KR 910003665A
Authority
KR
South Korea
Prior art keywords
voltage
semiconductor memory
test mode
memory circuit
field effect
Prior art date
Application number
KR1019900008835A
Other languages
English (en)
Other versions
KR930008416B1 (ko
Inventor
요우이찌 도비다
야스지 나까야마
Original Assignee
시기 모리야
미쓰비시뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910003665A publication Critical patent/KR910003665A/ko
Application granted granted Critical
Publication of KR930008416B1 publication Critical patent/KR930008416B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음.

Description

반도체 기억 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 한 실시예의 전기 회로도.

Claims (1)

1개의 절연게이트형 전계효과 트랜지스터와 1개의 용량으로 이루어지는 메모리셀을 복수 포 함하는 반도체 기억회로에 있어서, 상기 절연게이트형 전계효과 트랜지스터의 한쪽의 전극이 접속된 비트선에 전압을 부여하는 정전압 발생수단, 및 테스트 모드 검출회로를 포함하고, 해당 테스트 모드 검출회로가 테스트 모드를 검출한 것에 응답하여, 통상 사용시에 부여되는 전압보다도 높은 적어도 1개의 제1의 전압과 해당 제1의 전압보다도 낮은 적어도 1개의 제2의 전압을 상기 정전압발생수단으로부터, 발생시키는 제어수단을 구비한 반도체 기 억회로.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900008835A 1989-07-13 1990-06-15 반도체 기억 회로 KR930008416B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1180967A JPH0346188A (ja) 1989-07-13 1989-07-13 半導体記憶回路
JP1-180967 1989-07-13
JP89-180967 1989-07-13

Publications (2)

Publication Number Publication Date
KR910003665A true KR910003665A (ko) 1991-02-28
KR930008416B1 KR930008416B1 (ko) 1993-08-31

Family

ID=16092411

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900008835A KR930008416B1 (ko) 1989-07-13 1990-06-15 반도체 기억 회로

Country Status (4)

Country Link
US (1) US5523977A (ko)
JP (1) JPH0346188A (ko)
KR (1) KR930008416B1 (ko)
DE (1) DE4022153A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100341412B1 (ko) * 1998-02-25 2002-08-22 미쓰비시덴키 가부시키가이샤 메모리용량전환방법및그방법을적용하는반도체장치

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JP2945508B2 (ja) * 1991-06-20 1999-09-06 三菱電機株式会社 半導体装置
JP3282188B2 (ja) * 1991-06-27 2002-05-13 日本電気株式会社 半導体メモリ装置
US5377152A (en) 1991-11-20 1994-12-27 Kabushiki Kaisha Toshiba Semiconductor memory and screening test method thereof
JPH05144296A (ja) * 1991-11-20 1993-06-11 Toshiba Corp 半導体記憶装置の検査方法
JPH06349298A (ja) * 1993-04-14 1994-12-22 Nec Corp 半導体装置
JP2639319B2 (ja) * 1993-09-22 1997-08-13 日本電気株式会社 半導体装置
EP0691612A1 (en) * 1994-07-07 1996-01-10 International Business Machines Corporation A test circuit of embedded arrays in mixed logic and memory chips
JPH08153400A (ja) * 1994-11-29 1996-06-11 Mitsubishi Electric Corp Ｄｒａｍ
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5745432A (en) * 1996-01-19 1998-04-28 Sgs-Thomson Microelectronics, Inc. Write driver having a test function
US5848018A (en) * 1996-01-19 1998-12-08 Stmicroelectronics, Inc. Memory-row selector having a test function
US5923601A (en) * 1996-09-30 1999-07-13 Advanced Micro Devices, Inc. Memory array sense amplifier test and characterization
US5936892A (en) * 1996-09-30 1999-08-10 Advanced Micro Devices, Inc. Memory cell DC characterization apparatus and method
WO1998014955A1 (en) * 1996-09-30 1998-04-09 Advanced Micro Devices, Inc. Data retention test for static memory cell
US5930185A (en) * 1997-09-26 1999-07-27 Advanced Micro Devices, Inc. Data retention test for static memory cell
US6002622A (en) * 1998-02-19 1999-12-14 Micron Technology, Inc. Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
US6173425B1 (en) 1998-04-15 2001-01-09 Integrated Device Technology, Inc. Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams
JP2002245797A (ja) * 2001-02-16 2002-08-30 Mitsubishi Electric Corp 半導体集積回路
JP3910078B2 (ja) * 2001-05-11 2007-04-25 株式会社ルネサステクノロジ 半導体記憶装置および半導体記憶装置のテスト方法
US6763314B2 (en) 2001-09-28 2004-07-13 International Business Machines Corporation AC defect detection and failure avoidance power up and diagnostic system
US7298656B2 (en) * 2004-04-30 2007-11-20 Infineon Technologies Ag Process monitoring by comparing delays proportional to test voltages and reference voltages
JP2008123586A (ja) * 2006-11-09 2008-05-29 Toshiba Corp 半導体装置
CN112230112A (zh) * 2019-06-28 2021-01-15 中电海康集团有限公司 测试结构和测试方法

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
JPS5853775A (ja) * 1981-09-26 1983-03-30 Fujitsu Ltd Ｉｃメモリ試験方法
JPS61292755A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 半導体集積回路
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
JPS62229600A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 不揮発性半導体記憶装置
JPS6370451A (ja) * 1986-09-11 1988-03-30 Mitsubishi Electric Corp 半導体集積回路
KR0127680B1 (ko) * 1987-08-07 1998-04-03 미다 가쓰시게 반도체 기억장치
JPS6459696A (en) * 1987-08-29 1989-03-07 Matsushita Electronics Corp Dynamic-type memory
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100341412B1 (ko) * 1998-02-25 2002-08-22 미쓰비시덴키 가부시키가이샤 메모리용량전환방법및그방법을적용하는반도체장치

Also Published As

Publication number Publication date
JPH0346188A (ja) 1991-02-27
DE4022153C2 (ko) 1992-03-26
DE4022153A1 (de) 1991-01-24
US5523977A (en) 1996-06-04
KR930008416B1 (ko) 1993-08-31

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