JPS6459696A - Dynamic-type memory - Google Patents
Dynamic-type memoryInfo
- Publication number
- JPS6459696A JPS6459696A JP62214163A JP21416387A JPS6459696A JP S6459696 A JPS6459696 A JP S6459696A JP 62214163 A JP62214163 A JP 62214163A JP 21416387 A JP21416387 A JP 21416387A JP S6459696 A JPS6459696 A JP S6459696A
- Authority
- JP
- Japan
- Prior art keywords
- time
- condition
- storage information
- capacity
- trqts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
PURPOSE:To attain effective scanning in a short time by deteriorating the storage information holding characteristics of the data at the time of a refreshing action function. CONSTITUTION:At the time of the scanning of the refreshing action function, by setting a gate node phiTS of a transistor TrQTS at higher level than the external level, making the TrQTS into an ON-condition, and connecting the resistance of R<<r, a bit line precharging potential VBP is made higher than one half of the potential of a supply voltage. In the dynamic-type memory device with the constitution as mentioned above, first, at the time of waiting, TrQ1-Q3 are made into the ON-condition by a control signal phiP, and the bit lines BL and /BL are charged by the potential VBP=1/2VCC+alpha. At the time of the action, the TrQ1-Q3 become an OFF-condition, a word line WL is selected, a TrQ4 becomes the ON-condition, the line BL and a memory cell capacitor CS are connected, the accumulated charge of the storage information moves due to he capacity dividing of a bit line capacity CB and a capacity CS, a reading margin for one datum becomes smaller, and the storage information holding characteristic of the datum can be equivalently deteriorated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62214163A JPS6459696A (en) | 1987-08-29 | 1987-08-29 | Dynamic-type memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62214163A JPS6459696A (en) | 1987-08-29 | 1987-08-29 | Dynamic-type memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6459696A true JPS6459696A (en) | 1989-03-07 |
Family
ID=16651279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62214163A Pending JPS6459696A (en) | 1987-08-29 | 1987-08-29 | Dynamic-type memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6459696A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5523977A (en) * | 1989-07-13 | 1996-06-04 | Mitsubishi Denki Kabushiki Kaisha | Testing semiconductor memory device having test circuit |
JP2009158040A (en) * | 2007-12-27 | 2009-07-16 | Renesas Technology Corp | Semiconductor storage device |
JP2011165231A (en) * | 2010-02-04 | 2011-08-25 | Renesas Electronics Corp | Method, program, and apparatus for testing semiconductor memory |
-
1987
- 1987-08-29 JP JP62214163A patent/JPS6459696A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5523977A (en) * | 1989-07-13 | 1996-06-04 | Mitsubishi Denki Kabushiki Kaisha | Testing semiconductor memory device having test circuit |
JP2009158040A (en) * | 2007-12-27 | 2009-07-16 | Renesas Technology Corp | Semiconductor storage device |
JP2011165231A (en) * | 2010-02-04 | 2011-08-25 | Renesas Electronics Corp | Method, program, and apparatus for testing semiconductor memory |
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