KR890011091A - 불휘발성 반도체장치 - Google Patents
불휘발성 반도체장치 Download PDFInfo
- Publication number
- KR890011091A KR890011091A KR1019880017145A KR880017145A KR890011091A KR 890011091 A KR890011091 A KR 890011091A KR 1019880017145 A KR1019880017145 A KR 1019880017145A KR 880017145 A KR880017145 A KR 880017145A KR 890011091 A KR890011091 A KR 890011091A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- nonvolatile semiconductor
- semiconductor substrate
- silicon nitride
- connection hole
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 1실시예에 따른 EPROM셀을 도시해 놓은 단면도.
제3도는 실리콘질화물층 밑에 형성된 산화층의 두께와 전하손실 또는 전하보유특성 사이의 관계를 나타낸 특성곡선도.
* 도면의 주요부분에 대한 부호의 설명
101 : 반도체기판 102 : 플로우팅게이트전극
103 : 제어게이트전극 104 : 소오스 및 드레인영역
106 : 실리콘질화물층 107 : PSG층
108 : 금속배선층 109 : 접속구멍
Claims (4)
- 반도체기판(101)상에 형성됨과 더불어, 전하축적용 메모리셀(100)과, 배선층(108)과 상기 반도체기판(101)을 접속시키기 위한 접속구멍(109)을 갖춘 불휘발성 반도체장치에 있어서, 상기 메모리셀(100)과 접속구멍(109)주위의 반도체기판영역이 실리콘질화물층(106)으로 피복되어진 것을 특징으로 하는 불휘방성 반도체장치.
- 제1항에 있어서, 상기 실리콘질화물층(106)과 상기 반도체기판(101)사이에 두께가 1000Å이하인 산화층이 형성되어 있는 것을 특징으로 하는 불휘발성 반도체장치.
- 제1항에 있어서, 상기 메모리셀(100)에 플로우팅게이트전극(102)과 제어게이트전극(103)이 구비되어 있는 것을 특징으로 하는 불휘발성 반도체장치.
- 제1항에 있어서, 상기 접속구멍(109)주위에 형성된 실리콘질화물층(106)이 상기 반도체기판(101)에 직접 접촉되도록 된 것을 특징으로 하는 불휘발성 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32308487A JP2672537B2 (ja) | 1987-12-21 | 1987-12-21 | 不揮発性半導体装置の製造方法 |
JP62-323084 | 1987-12-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890011091A true KR890011091A (ko) | 1989-08-12 |
KR920001640B1 KR920001640B1 (ko) | 1992-02-21 |
Family
ID=18150902
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880017145A KR920001640B1 (ko) | 1987-12-21 | 1988-12-21 | 불휘발성 반도체장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5453634A (ko) |
JP (1) | JP2672537B2 (ko) |
KR (1) | KR920001640B1 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6017792A (en) * | 1994-09-06 | 2000-01-25 | Motorola, Inc. | Process for fabricating a semiconductor device including a nonvolatile memory cell |
US5840624A (en) * | 1996-03-15 | 1998-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd | Reduction of via over etching for borderless contacts |
JPH1140766A (ja) | 1997-07-16 | 1999-02-12 | Fujitsu Ltd | 半導体装置、dram、フラッシュメモリ、およびその製造方法 |
US6555865B2 (en) | 2001-07-10 | 2003-04-29 | Samsung Electronics Co. Ltd. | Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5530846A (en) * | 1978-08-28 | 1980-03-04 | Hitachi Ltd | Method for manufacturing fixed memory |
JPS5534444A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor device |
JPS5544742A (en) * | 1978-09-26 | 1980-03-29 | Fujitsu Ltd | Manufacture of semiconductor device |
US4364167A (en) * | 1979-11-28 | 1982-12-21 | General Motors Corporation | Programming an IGFET read-only-memory |
US4455568A (en) * | 1981-08-27 | 1984-06-19 | American Microsystems, Inc. | Insulation process for integrated circuits |
JPS5850771A (ja) * | 1981-09-21 | 1983-03-25 | Hitachi Ltd | 再書込み可能な高集積rom及びその製造方法 |
JPS60210851A (ja) * | 1984-04-05 | 1985-10-23 | Toshiba Corp | 半導体装置とその製造方法 |
EP0164605B1 (en) * | 1984-05-17 | 1990-02-28 | Kabushiki Kaisha Toshiba | Method of manufacturing nonvolatile semiconductor eeprom device |
JPS61154175A (ja) * | 1984-12-27 | 1986-07-12 | Toshiba Corp | 半導体記憶装置の製造方法 |
JPS61161720A (ja) * | 1985-01-10 | 1986-07-22 | Nec Corp | 半導体装置の製造方法 |
US4665426A (en) * | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
JPS61225871A (ja) * | 1985-03-30 | 1986-10-07 | Toshiba Corp | 半導体記憶装置の製造方法 |
JPS61290771A (ja) * | 1985-06-19 | 1986-12-20 | Matsushita Electronics Corp | 半導体記憶装置の製造方法 |
JPS6273774A (ja) * | 1985-09-27 | 1987-04-04 | Toshiba Corp | 半導体記憶装置の製造方法 |
JPS62125679A (ja) * | 1985-11-26 | 1987-06-06 | Nec Corp | Mos半導体記憶装置 |
US4789560A (en) * | 1986-01-08 | 1988-12-06 | Advanced Micro Devices, Inc. | Diffusion stop method for forming silicon oxide during the fabrication of IC devices |
JPS62188375A (ja) * | 1986-02-14 | 1987-08-17 | Hitachi Ltd | 半導体集積回路装置 |
JPH0620102B2 (ja) * | 1987-05-20 | 1994-03-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
-
1987
- 1987-12-21 JP JP32308487A patent/JP2672537B2/ja not_active Expired - Lifetime
-
1988
- 1988-12-21 KR KR1019880017145A patent/KR920001640B1/ko not_active IP Right Cessation
-
1994
- 1994-02-15 US US08/196,786 patent/US5453634A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2672537B2 (ja) | 1997-11-05 |
KR920001640B1 (ko) | 1992-02-21 |
JPH01164069A (ja) | 1989-06-28 |
US5453634A (en) | 1995-09-26 |
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