KR890003033A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR890003033A
KR890003033A KR1019880008710A KR880008710A KR890003033A KR 890003033 A KR890003033 A KR 890003033A KR 1019880008710 A KR1019880008710 A KR 1019880008710A KR 880008710 A KR880008710 A KR 880008710A KR 890003033 A KR890003033 A KR 890003033A
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KR
South Korea
Prior art keywords
semiconductor memory
gates
memory device
electrons
drain
Prior art date
Application number
KR1019880008710A
Other languages
English (en)
Other versions
KR960012167B1 (ko
Inventor
히데쯔구 우찌다
Original Assignee
고스기 노부미쓰
오끼뎅끼고오교오가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼뎅끼고오교오가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR890003033A publication Critical patent/KR890003033A/ko
Application granted granted Critical
Publication of KR960012167B1 publication Critical patent/KR960012167B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용없음

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 실시예에 관한 반도체 기억장치의 메모리셀을 표시하는 단면도. 제 2도는 종래의 플로우팅 게이트형 EEPROM의 단면도. 제 3 도는 제 2 도의 소거 및기입시의 인가전압 조건도

Claims (3)

  1. 반도체기판의 표면에 MOS트랜지스터의 소스와 드레인이 형성된 불휘발성의 메모리셀을 가지는 반도체 기억장치에 있어서 사기 소스와 드레인간에 절연막을 사이에 두고 제1, 제2, 제3의 게이트를 배설하고 그 양단의 제1과 제 3의 게이트에 소정전압을 인가하는 것에 의하여 중간의 제2의 게이트에 대하여 전자의 주입 및 끄집어내기를 행하도록한 것을 특징으로 하는 반도체 기억장치
  2. 제 1 항에 있어서, 상기 제1과 제3의 게이트 어느 한쪽의 형셩면적을 다른 쪽보다도 작게하는 것에 의하여 작은 쪽의 게이트로부터 전자의 주입 및 끄집어내기를 행하도록 한 반도체 기억장치
  3. 제 1 항에 있어서, 정보 읽어내기시에 있어서 전기 제1, 제3의 게이트 및 드레인에 정전압을 인가하도록한 반도체 기억장치
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008710A 1987-07-13 1988-07-13 반도체기억장치 KR960012167B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-174543 1987-07-13
JP62174543A JPS6418270A (en) 1987-07-13 1987-07-13 Semiconductor memory device

Publications (2)

Publication Number Publication Date
KR890003033A true KR890003033A (ko) 1989-04-12
KR960012167B1 KR960012167B1 (ko) 1996-09-16

Family

ID=15980384

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008710A KR960012167B1 (ko) 1987-07-13 1988-07-13 반도체기억장치

Country Status (3)

Country Link
US (1) US4907197A (ko)
JP (1) JPS6418270A (ko)
KR (1) KR960012167B1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2600301B2 (ja) * 1988-06-28 1997-04-16 三菱電機株式会社 半導体記憶装置およびその製造方法
US5231041A (en) * 1988-06-28 1993-07-27 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of an electrically programmable non-volatile memory device having the floating gate extending over the control gate
US5168335A (en) * 1988-07-15 1992-12-01 Texas Instruments Incorporated Electrically programmable, electrically erasable memory array cell with field plate
US5111430A (en) * 1989-06-22 1992-05-05 Nippon Telegraph And Telephone Corporation Non-volatile memory with hot carriers transmitted to floating gate through control gate
US5047816A (en) * 1990-08-21 1991-09-10 Vlsi Technology, Inc. Self-aligned dual-gate transistor
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5477068A (en) * 1992-03-18 1995-12-19 Rohm Co., Ltd. Nonvolatile semiconductor memory device
JPH06120515A (ja) * 1992-10-09 1994-04-28 Oki Electric Ind Co Ltd 半導体不揮発性メモリのデータ書き込み及びデータ消去方法
US5471422A (en) * 1994-04-11 1995-11-28 Motorola, Inc. EEPROM cell with isolation transistor and methods for making and operating the same
KR100309139B1 (ko) * 1994-12-16 2002-02-19 박종섭 비휘발성 메모리 소자 제조방법
KR100219117B1 (ko) * 1996-08-24 1999-09-01 구자홍 박막트랜지스터 액정표시장치 및 그 제조방법
US20040021170A1 (en) * 1999-03-24 2004-02-05 Caywood John M. Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6534816B1 (en) 1999-03-24 2003-03-18 John M. Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6384451B1 (en) 1999-03-24 2002-05-07 John Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
DE10138585A1 (de) * 2001-08-06 2003-03-06 Infineon Technologies Ag Speicherzelle
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141969A (en) * 1981-02-27 1982-09-02 Toshiba Corp Nonvolatile semiconductor memory
US4513397A (en) * 1982-12-10 1985-04-23 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
US4590503A (en) * 1983-07-21 1986-05-20 Honeywell Inc. Electrically erasable programmable read only memory
US4608591A (en) * 1983-08-17 1986-08-26 Rca Corporation Electrically alterable programmable nonvolatile floating gate memory device
US4752912A (en) * 1985-05-14 1988-06-21 Xicor, Inc. Nonvolatile electrically alterable memory and method

Also Published As

Publication number Publication date
JPS6418270A (en) 1989-01-23
US4907197A (en) 1990-03-06
KR960012167B1 (ko) 1996-09-16

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