KR850005160A - 적층형 반도체 기억장치 - Google Patents

적층형 반도체 기억장치 Download PDF

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Publication number
KR850005160A
KR850005160A KR1019840007999A KR840007999A KR850005160A KR 850005160 A KR850005160 A KR 850005160A KR 1019840007999 A KR1019840007999 A KR 1019840007999A KR 840007999 A KR840007999 A KR 840007999A KR 850005160 A KR850005160 A KR 850005160A
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KR
South Korea
Prior art keywords
transistor
drain
source
semiconductor memory
stacked semiconductor
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KR1019840007999A
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English (en)
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KR920010821B1 (ko
Inventor
히도시 구메 (외 5)
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미쓰다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼 (외 1)
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Publication of KR850005160A publication Critical patent/KR850005160A/ko
Application granted granted Critical
Publication of KR920010821B1 publication Critical patent/KR920010821B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

적층형 반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 실시예의 단면도.
제4도는 본 발명의 실시예의 회로도.
제5도A와 제5도B는 본 발명의 실시예의 제조공정을 도시한 단면도.

Claims (5)

  1. 기억용의 제1의 트랜지스터와, 정보 판정용의 제2의 트랜지스터와, 호출용의 제3의 트랜지스터를 가진 반도체 장치에 있어서, 제1의 트랜지스터의 드레인 또는 소오스를 제2의 트랜지스터의 게이트 전극에 접속하고, 제2의 트랜지스터의 드레인 또는 소오스를 제3의 트랜지스터의 소오스 또는 드레인에 접속하며, 상기 제1의 트랜지스터의 적어도 일부가 상기 제3의 트랜지스터의 상부에 마련되어 있는 것을 특징으로 하는 적층형 반도체 기억장치.
  2. 상기 제1의 트랜지스터의 소오스 또는 드레인을 상기 제3의 트랜지스터의 소오스 또는 드레인과 접속하고, 상기 제1의 트랜지스터의 드레인 또는 소오스를 제2의 트랜지스터의 게이트 전극에 접속하는 것은, 해당 게이트 전극과, 상기 드레인 또는 소오스 영역이 같은 공정으로 마련된 반도체층에 의해서 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항에 기재의 적층형 반도체 기억장치.
  3. 상기 제1의 트랜지스터의 소오스 또는 드레인을 상기 제3의 트랜지스터의 소오스 또는 드레인과 접속하고, 상기 제2, 제3의 게이트 전극은 같은 공정으로 되는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 적층형 반도체 기억장치.
  4. 상기 제1의 트랜지스터의 소오스 또는 드레인을 상기 제3의 트랜지스터의 소오스 또는 드레인과 접속한 영역을 정보의 출력, 입력부로 하고, 상기 제2의 트랜지스터의 소오스 또는 드레인을 기준전위로 하는 것을 특징으로 하는 특허청구의 범위 제2항 기재의 적층형 반도체 기억장치.
  5. 상기 제1의 트랜지스터의 소오스 또는 드레인을 상기 제3의 트랜지스터의 소오스 또는 드레인과 접속한 영역을 정보의 출력, 입력부로 하고, 상기 제2의 트랜지스터의 소오스 또는 드레인을 기준전위로 하는 것을 특징으로 하는 특허청구의 범위 제3항 기재의 적층형 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840007999A 1983-12-19 1984-12-15 적층형 반도체 기억장치 KR920010821B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58-237776 1983-12-19
JP58237776A JPS60130160A (ja) 1983-12-19 1983-12-19 半導体記憶装置

Publications (2)

Publication Number Publication Date
KR850005160A true KR850005160A (ko) 1985-08-21
KR920010821B1 KR920010821B1 (ko) 1992-12-17

Family

ID=17020258

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840007999A KR920010821B1 (ko) 1983-12-19 1984-12-15 적층형 반도체 기억장치

Country Status (6)

Country Link
US (1) US4633438A (ko)
EP (1) EP0147151B1 (ko)
JP (1) JPS60130160A (ko)
KR (1) KR920010821B1 (ko)
CA (1) CA1222821A (ko)
DE (1) DE3484955D1 (ko)

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KR101822962B1 (ko) 2010-02-05 2018-01-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
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Also Published As

Publication number Publication date
EP0147151A2 (en) 1985-07-03
EP0147151A3 (en) 1987-07-01
EP0147151B1 (en) 1991-08-21
DE3484955D1 (de) 1991-09-26
JPS60130160A (ja) 1985-07-11
CA1222821A (en) 1987-06-09
KR920010821B1 (ko) 1992-12-17
US4633438A (en) 1986-12-30

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