KR840005887A - 반도체 메모리 장치 - Google Patents

반도체 메모리 장치 Download PDF

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Publication number
KR840005887A
KR840005887A KR1019830003760A KR830003760A KR840005887A KR 840005887 A KR840005887 A KR 840005887A KR 1019830003760 A KR1019830003760 A KR 1019830003760A KR 830003760 A KR830003760 A KR 830003760A KR 840005887 A KR840005887 A KR 840005887A
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KR
South Korea
Prior art keywords
memory device
semiconductor memory
voltage
semiconductor region
semiconductor
Prior art date
Application number
KR1019830003760A
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English (en)
Other versions
KR910009548B1 (ko
Inventor
데스로 마스모도
Original Assignee
미쓰다 가쓰시게
가부시기 가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 미쓰다 가쓰시게, 가부시기 가이샤 히다찌세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840005887A publication Critical patent/KR840005887A/ko
Application granted granted Critical
Publication of KR910009548B1 publication Critical patent/KR910009548B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 메모리 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 메모리 셀의 구조를 도시한 단면도.
제2도는 제1도에 도시한 메모리 셀의 등가 회로도.
제3도는 스트레스 전압 VS와 프랫트 벤드 전압의 변화 △VFB와의 관계를 표시한 도표.

Claims (3)

  1. 다음과 같은 구성으로 된 반도체 메모리 장치. 스위칭 MISFET와 스토레이지 캐파시터의 직열 연결을 함유한 메모리 셀, 상기 스토레이지 캐파시터는 반도체 기판의 반도체 영역과 상기 반도체 영역의 표면을 덮어서 형성된 실리콘 질화막과 상기 실리콘 질화막을 덮어서 형성된 도전층으로 되며, 그리고, 상기 직열 연결의 일단에 접속되며, 또한 어떤 신호 전압을 공급하기 위한 비트선과, 상기 반도체 영역과 상기 도전충과의 사이에 축적되는 상기 스토레이지 캐파시터의 전압이 상기 비트선에 공급된 상기 신호 전압 보다도 절대치 적으로 작게 되도록 상기 직열 연결의 상기 다른 쪽에 접속된 단자.
  2. 특허 청구 범위 제1항에 따른 반도체 메모리 장치에 있어서, 상기 실리콘 질화막은 상기 반도체 영역위에 형성된 실리콘 산화막 위에 형성 되여 있다.
  3. 특허 청구 범위 제1항 또는 제2항의 반도체 메모리 장치에 있어서, 상기 단자에는 상기신호 전압의 반분 전압 혹은 그와 가까운 전압이 인가 된다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830003760A 1982-09-22 1983-08-11 반도체메모리장치 KR910009548B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP163888 1982-09-22
JP57163888A JPH0612619B2 (ja) 1982-09-22 1982-09-22 半導体メモリ装置

Publications (2)

Publication Number Publication Date
KR840005887A true KR840005887A (ko) 1984-11-19
KR910009548B1 KR910009548B1 (ko) 1991-11-21

Family

ID=15782701

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830003760A KR910009548B1 (ko) 1982-09-22 1983-08-11 반도체메모리장치

Country Status (10)

Country Link
US (5) US4638460A (ko)
JP (1) JPH0612619B2 (ko)
KR (1) KR910009548B1 (ko)
DE (1) DE3330046A1 (ko)
FR (1) FR2533348B1 (ko)
GB (1) GB2128430B (ko)
HK (1) HK188A (ko)
IT (1) IT1168281B (ko)
MY (1) MY102019A (ko)
SG (1) SG88687G (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612619B2 (ja) * 1982-09-22 1994-02-16 株式会社日立製作所 半導体メモリ装置
JPS6018948A (ja) * 1983-07-12 1985-01-31 Nec Corp 半導体集積回路装置
DE151898T1 (de) * 1984-01-05 1985-11-21 Mostek Corp., Carrollton, Tex. Verfahren und anordnung zur ausgleichung einer speicherzelle.
US5187685A (en) * 1985-11-22 1993-02-16 Hitachi, Ltd. Complementary MISFET voltage generating circuit for a semiconductor memory
JPH0789433B2 (ja) * 1985-11-22 1995-09-27 株式会社日立製作所 ダイナミツク型ｒａｍ
JP2610830B2 (ja) * 1986-07-01 1997-05-14 株式会社日立製作所 半導体記憶装置のメモリセルの極板電圧設定方法
JPS6421788A (en) * 1987-07-16 1989-01-25 Nec Corp Semiconductor memory device
JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
JP2535084B2 (ja) * 1990-02-19 1996-09-18 シャープ株式会社 半導体装置の製造方法
JPH04218959A (ja) * 1990-10-18 1992-08-10 Mitsubishi Electric Corp 半導体装置およびその制御方法
JPH06243678A (ja) * 1993-02-19 1994-09-02 Hitachi Ltd ダイナミック型ｒａｍとそのプレート電圧設定方法及び情報処理システム
JPH0794600A (ja) * 1993-06-29 1995-04-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5570317A (en) * 1994-07-19 1996-10-29 Intel Corporation Memory circuit with stress circuitry for detecting defects
JP2000056323A (ja) * 1998-08-12 2000-02-25 Hitachi Ltd 液晶表示装置
US6552887B1 (en) * 2000-06-29 2003-04-22 Intel Corporation Voltage dependent capacitor configuration for higher soft error rate tolerance
JP2003006041A (ja) * 2001-06-20 2003-01-10 Hitachi Ltd 半導体装置
US9633710B2 (en) * 2015-01-23 2017-04-25 Semiconductor Energy Laboratory Co., Ltd. Method for operating semiconductor device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3893152A (en) * 1973-07-25 1975-07-01 Hung Chang Lin Metal nitride oxide semiconductor integrated circuit structure
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
US4094008A (en) * 1976-06-18 1978-06-06 Ncr Corporation Alterable capacitor memory array
JPS5457875A (en) * 1977-10-17 1979-05-10 Hitachi Ltd Semiconductor nonvolatile memory device
JPS607389B2 (ja) * 1978-12-26 1985-02-23 超エル・エス・アイ技術研究組合 半導体装置の製造方法
JPS5666065A (en) * 1979-11-01 1981-06-04 Mitsubishi Electric Corp Semiconductor memory unit
JPS5927102B2 (ja) * 1979-12-24 1984-07-03 富士通株式会社 半導体記憶装置
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JPH0612619B2 (ja) * 1982-09-22 1994-02-16 株式会社日立製作所 半導体メモリ装置

Also Published As

Publication number Publication date
US4887237A (en) 1989-12-12
IT1168281B (it) 1987-05-20
GB8320218D0 (en) 1983-09-01
US4740920A (en) 1988-04-26
SG88687G (en) 1988-06-03
HK188A (en) 1988-01-15
JPH0612619B2 (ja) 1994-02-16
DE3330046A1 (de) 1984-03-22
GB2128430A (en) 1984-04-26
US5148392A (en) 1992-09-15
GB2128430B (en) 1986-11-26
JPS5954097A (ja) 1984-03-28
US4991137A (en) 1991-02-05
US4638460A (en) 1987-01-20
MY102019A (en) 1992-02-29
KR910009548B1 (ko) 1991-11-21
IT8322951A0 (it) 1983-09-21
FR2533348B1 (fr) 1991-10-31
FR2533348A1 (fr) 1984-03-23

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